Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3904982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4483678

1

T1

903

T2

888

T3

1040

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4632079	1			T1	9		T2	5		T3	300
values[0x0]	1878647	1			T1	447		T2	448		T3	437
values[0x1]	1877934	1			T1	451		T2	440		T3	454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2764739	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5623921

1

T1

903

T2

888

T3

1069

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30531	1			T1	2		T9	1		T10	6
valid_sources[0x01]	29821	1			T1	5		T4	17		T9	1
valid_sources[0x02]	33768	1			T1	2		T5	2552		T10	6
valid_sources[0x03]	31830	1			T6	1		T10	8		T12	21
valid_sources[0x04]	33261	1			T1	2		T9	2		T10	10
valid_sources[0x05]	31517	1			T1	2		T9	1		T10	7
valid_sources[0x06]	38754	1			T1	2		T10	10		T11	4
valid_sources[0x07]	30725	1			T1	5		T10	7		T12	224
valid_sources[0x08]	28571	1			T1	1		T9	2		T10	7
valid_sources[0x09]	31067	1			T1	7		T10	8		T11	5
valid_sources[0x0a]	34365	1			T1	5		T10	5		T11	5
valid_sources[0x0b]	28792	1			T1	1		T6	1		T10	8
valid_sources[0x0c]	28949	1			T1	6		T10	11		T11	4
valid_sources[0x0d]	30195	1			T1	4		T10	8		T12	47
valid_sources[0x0e]	36946	1			T1	3		T9	1		T10	5
valid_sources[0x0f]	32233	1			T1	3		T9	1		T10	6
valid_sources[0x10]	31986	1			T1	4		T10	2		T11	13
valid_sources[0x11]	29755	1			T1	4		T10	8		T12	6
valid_sources[0x12]	33621	1			T1	5		T10	1		T11	1
valid_sources[0x13]	31344	1			T1	5		T10	5		T11	2
valid_sources[0x14]	32103	1			T1	3		T9	1		T10	5
valid_sources[0x15]	37656	1			T1	2		T10	5		T11	3
valid_sources[0x16]	32246	1			T1	3		T10	3		T12	14
valid_sources[0x17]	37718	1			T10	9		T13	7		T14	22
valid_sources[0x18]	32524	1			T1	4		T7	430		T10	6
valid_sources[0x19]	32308	1			T1	1		T10	6		T12	58
valid_sources[0x1a]	33036	1			T1	4		T10	5		T11	4
valid_sources[0x1b]	30228	1			T1	2		T7	451		T10	7
valid_sources[0x1c]	33597	1			T1	3		T9	1		T10	3
valid_sources[0x1d]	30697	1			T1	1		T3	449		T6	1
valid_sources[0x1e]	33591	1			T6	1		T9	1		T10	2
valid_sources[0x1f]	30033	1			T1	4		T10	5		T11	4
valid_sources[0x20]	33722	1			T1	5		T9	1		T10	6
valid_sources[0x21]	56023	1			T1	5		T9	1		T10	7
valid_sources[0x22]	42758	1			T1	3		T10	3		T12	2
valid_sources[0x23]	36504	1			T1	3		T10	3		T11	5
valid_sources[0x24]	32604	1			T1	5		T10	10		T11	5
valid_sources[0x25]	30778	1			T1	4		T9	3		T10	1
valid_sources[0x26]	32047	1			T1	2		T9	1		T10	4
valid_sources[0x27]	31343	1			T1	5		T10	4		T11	6
valid_sources[0x28]	36141	1			T1	2		T10	7		T12	59
valid_sources[0x29]	41184	1			T1	1		T4	8235		T11	1
valid_sources[0x2a]	32966	1			T1	6		T10	2		T12	2
valid_sources[0x2b]	31901	1			T1	1		T10	5		T11	3
valid_sources[0x2c]	31281	1			T1	5		T10	10		T11	1
valid_sources[0x2d]	30736	1			T1	1		T10	3		T11	2
valid_sources[0x2e]	32186	1			T1	1		T10	1		T11	1
valid_sources[0x2f]	28746	1			T1	9		T10	9		T11	4
valid_sources[0x30]	34606	1			T1	4		T10	4		T11	3
valid_sources[0x31]	31503	1			T1	1		T10	4		T11	4
valid_sources[0x32]	31670	1			T1	5		T9	1		T10	4
valid_sources[0x33]	35317	1			T1	4		T9	2		T10	5
valid_sources[0x34]	33041	1			T1	2		T9	3		T10	14
valid_sources[0x35]	32574	1			T1	5		T6	2		T10	11
valid_sources[0x36]	30695	1			T1	5		T10	3		T11	7
valid_sources[0x37]	37244	1			T1	5		T10	4		T11	1
valid_sources[0x38]	32883	1			T1	3		T8	1		T10	6
valid_sources[0x39]	32175	1			T1	3		T10	7		T11	5
valid_sources[0x3a]	31710	1			T1	3		T10	3		T11	3
valid_sources[0x3b]	35177	1			T1	5		T4	25		T10	4
valid_sources[0x3c]	31739	1			T1	1		T10	10		T11	2
valid_sources[0x3d]	33819	1			T10	9		T11	7		T12	3
valid_sources[0x3e]	30456	1			T1	2		T10	7		T12	7
valid_sources[0x3f]	32651	1			T1	2		T10	9		T12	15
valid_sources[0x40]	34954	1			T1	2		T10	1		T12	4
valid_sources[0x41]	31459	1			T1	5		T9	1		T10	1
valid_sources[0x42]	31673	1			T1	4		T10	3		T12	64
valid_sources[0x43]	35741	1			T1	4		T9	1		T10	10
valid_sources[0x44]	28538	1			T1	6		T10	6		T11	1
valid_sources[0x45]	32455	1			T1	3		T10	5		T11	1
valid_sources[0x46]	36815	1			T1	3		T10	3		T11	6
valid_sources[0x47]	34047	1			T1	4		T10	3		T11	4
valid_sources[0x48]	33173	1			T1	4		T10	3		T11	7
valid_sources[0x49]	29235	1			T1	6		T10	7		T11	5
valid_sources[0x4a]	33576	1			T1	2		T6	1		T10	7
valid_sources[0x4b]	32021	1			T1	3		T10	9		T11	2
valid_sources[0x4c]	32385	1			T1	8		T10	7		T11	5
valid_sources[0x4d]	28347	1			T1	3		T9	1		T10	6
valid_sources[0x4e]	32517	1			T1	1		T10	3		T11	7
valid_sources[0x4f]	31746	1			T9	2		T10	2		T11	13
valid_sources[0x50]	33843	1			T1	3		T9	1		T10	8
valid_sources[0x51]	31069	1			T1	4		T10	9		T13	4
valid_sources[0x52]	29186	1			T1	1		T9	2		T10	5
valid_sources[0x53]	35109	1			T1	3		T9	1		T10	5
valid_sources[0x54]	31684	1			T1	1		T10	4		T11	3
valid_sources[0x55]	34985	1			T1	2		T10	11		T12	129
valid_sources[0x56]	35734	1			T1	1		T8	1		T10	4
valid_sources[0x57]	31102	1			T1	3		T10	3		T11	3
valid_sources[0x58]	33347	1			T1	6		T10	5		T11	2
valid_sources[0x59]	29740	1			T1	6		T9	1		T10	5
valid_sources[0x5a]	34723	1			T1	5		T10	5		T12	73
valid_sources[0x5b]	35530	1			T1	2		T10	1		T11	3
valid_sources[0x5c]	36721	1			T1	1		T10	2		T11	2
valid_sources[0x5d]	31987	1			T1	3		T10	2		T11	7
valid_sources[0x5e]	30827	1			T1	9		T10	8		T11	4
valid_sources[0x5f]	37295	1			T1	2		T6	1		T10	2
valid_sources[0x60]	36547	1			T1	1		T10	4		T11	2
valid_sources[0x61]	30056	1			T1	7		T9	1		T10	7
valid_sources[0x62]	34563	1			T1	5		T10	9		T11	2
valid_sources[0x63]	29217	1			T1	4		T10	6		T12	159
valid_sources[0x64]	32142	1			T1	5		T10	9		T11	1
valid_sources[0x65]	31065	1			T1	3		T10	5		T11	4
valid_sources[0x66]	31774	1			T1	8		T10	4		T11	2
valid_sources[0x67]	32587	1			T1	3		T10	5		T13	9
valid_sources[0x68]	30012	1			T1	4		T10	2		T12	27
valid_sources[0x69]	30493	1			T1	1		T10	6		T12	577
valid_sources[0x6a]	33728	1			T1	8		T10	7		T11	1
valid_sources[0x6b]	31666	1			T8	1		T10	4		T11	10
valid_sources[0x6c]	33114	1			T1	8		T10	4		T12	172
valid_sources[0x6d]	32228	1			T10	3		T11	6		T12	2
valid_sources[0x6e]	30681	1			T1	5		T9	1		T10	2
valid_sources[0x6f]	31027	1			T1	3		T10	8		T11	14
valid_sources[0x70]	30361	1			T1	7		T10	11		T11	4
valid_sources[0x71]	31450	1			T1	4		T10	3		T11	6
valid_sources[0x72]	31157	1			T10	3		T11	1		T12	4
valid_sources[0x73]	37955	1			T1	6		T10	6		T11	4
valid_sources[0x74]	29513	1			T1	4		T10	5		T11	2
valid_sources[0x75]	33221	1			T1	4		T10	6		T11	1
valid_sources[0x76]	31148	1			T1	1		T10	10		T11	4
valid_sources[0x77]	30516	1			T1	1		T9	1		T10	6
valid_sources[0x78]	31704	1			T1	8		T6	1		T10	2
valid_sources[0x79]	45975	1			T1	5		T9	2		T10	6
valid_sources[0x7a]	30054	1			T1	2		T10	4		T12	219
valid_sources[0x7b]	31197	1			T1	5		T10	3		T11	5
valid_sources[0x7c]	39967	1			T1	8		T4	1530		T10	2
valid_sources[0x7d]	30664	1			T1	5		T10	6		T11	1
valid_sources[0x7e]	33302	1			T1	3		T10	3		T11	1
valid_sources[0x7f]	31858	1			T1	4		T10	3		T11	4
valid_sources[0x80]	31546	1			T1	4		T10	3		T11	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1093661

1

T1

6

T2

3

T3

154

values[0x0]

all_enables

biggest_size

1708713

1

T1

446

T2

447

T3

434

values[0x1]

all_enables

biggest_size

1681304

1

T1

451

T2

438

T3

452