Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3924665

1

T1

4

T2

5

T3

151

full_word

4482677

1

T1

903

T2

888

T3

1040

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8406922	1			T1	907		T2	893		T3	1191
auto[TlIntgErrCmd]	148	1			T107	9		T111	8		T112	8
auto[TlIntgErrData]	144	1			T107	11		T111	5		T112	6
auto[TlIntgErrBoth]	128	1			T107	10		T111	7		T112	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4633709

1

T1

9

T2

5

T3

300

auto[1]

3773633

1

T1

898

T2

888

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3539802	1			T1	3		T2	2		T3	146
auto[TlIntgErrNone]	partial	auto[1]	384487	1			T1	1		T2	3		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1093713	1			T1	6		T2	3		T3	154
auto[TlIntgErrNone]	full_word	auto[1]	3388920	1			T1	897		T2	885		T3	886
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T107	3		T111	4		T112	1
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T107	6		T111	3		T112	4
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T111	1		T112	2		T190	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T112	1		T191	1		T192	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T107	7		T111	2		T112	4
auto[TlIntgErrData]	partial	auto[1]	62	1			T107	4		T111	3		T112	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T187	1		T190	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T194	1		T161	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T107	4		T111	3		T112	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T107	5		T111	3		T112	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T187	2		T193	2		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T107	1		T111	1		T187	1