Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498530043	2951898	0	0
DepthKnown_A	498530043	498392979	0	0
RvalidKnown_A	498530043	498392979	0	0
WreadyKnown_A	498530043	498392979	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	2951898	0	0
T1	36610	1663	0	0
T2	604899	832	0	0
T3	217763	1663	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	1663	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	1663	0	0
T12	0	6655	0	0
T13	0	1343	0	0
T14	0	5828	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498530043	3318527	0	0
DepthKnown_A	498530043	498392979	0	0
RvalidKnown_A	498530043	498392979	0	0
WreadyKnown_A	498530043	498392979	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	3318527	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	5824	0	0
T13	0	1088	0	0
T14	0	6214	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498530043	202797	0	0
DepthKnown_A	498530043	498392979	0	0
RvalidKnown_A	498530043	498392979	0	0
WreadyKnown_A	498530043	498392979	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	202797	0	0
T12	309289	1220	0	0
T13	16933	0	0	0
T14	122339	444	0	0
T15	0	1632	0	0
T26	0	862	0	0
T28	0	192	0	0
T30	131766	225	0	0
T31	195011	0	0	0
T32	3024	0	0	0
T33	0	905	0	0
T34	0	503	0	0
T38	775229	129	0	0
T42	0	100	0	0
T45	17577	0	0	0
T46	107052	0	0	0
T47	19500	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498530043	474699	0	0
DepthKnown_A	498530043	498392979	0	0
RvalidKnown_A	498530043	498392979	0	0
WreadyKnown_A	498530043	498392979	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	474699	0	0
T12	309289	1220	0	0
T13	16933	0	0	0
T14	122339	1911	0	0
T15	0	7207	0	0
T26	0	862	0	0
T28	0	192	0	0
T30	131766	225	0	0
T31	195011	0	0	0
T32	3024	0	0	0
T33	0	905	0	0
T34	0	503	0	0
T38	775229	129	0	0
T42	0	333	0	0
T45	17577	0	0	0
T46	107052	0	0	0
T47	19500	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498530043	6691330	0	0
DepthKnown_A	498530043	498392979	0	0
RvalidKnown_A	498530043	498392979	0	0
WreadyKnown_A	498530043	498392979	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	6691330	0	0
T1	36610	75	0	0
T2	604899	61	0	0
T3	217763	360	0	0
T4	199394	8977	0	0
T5	183867	7034	0	0
T6	1035	17	0	0
T7	11039	49	0	0
T8	1402	5	0	0
T9	1897	73	0	0
T10	21939	592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498530043	14571546	0	0
DepthKnown_A	498530043	498392979	0	0
RvalidKnown_A	498530043	498392979	0	0
WreadyKnown_A	498530043	498392979	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	14571546	0	0
T1	36610	75	0	0
T2	604899	61	0	0
T3	217763	359	0	0
T4	199394	8975	0	0
T5	183867	7033	0	0
T6	1035	17	0	0
T7	11039	49	0	0
T8	1402	5	0	0
T9	1897	73	0	0
T10	21939	2378	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498530043	498392979	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0