Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T30
1	0	Covered	T12,T14,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T14
1	0	Unreachable
1	1	Covered	T12,T14,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T14,T38

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T38
1	0	Covered	T12,T14,T38

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T12,T14,T38

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T14,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T30
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	816016478	654560339	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	816016478	3965127	0	0
GntImpliesValid_A	816016478	3965127	0	0
GrantKnown_A	816016478	654560339	0	0
IdxKnown_A	816016478	654560339	0	0
IndexIsCorrect_A	816016478	3965127	0	0
LockArbDecision_A	816016478	0	0	0
NoReadyValidNoGrant_A	816016478	0	0	0
ReadyAndValidImplyGrant_A	816016478	3965127	0	0
ReqAndReadyImplyGrant_A	816016478	3965127	0	0
ReqImpliesValid_A	816016478	3965127	0	0
ReqStaysHighUntilGranted0_M	816016478	0	0	0
RoundRobin_A	816016478	8	0	975
ValidKnown_A	816016478	654560339	0	0
gen_data_port_assertion.DataFlow_A	816016478	3965127	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	654560339	0	0
T1	103592	103524	0	0
T2	705361	705062	0	0
T3	253431	253368	0	0
T4	223365	223297	0	0
T5	209170	208638	0	0
T6	1035	949	0	0
T7	15151	15093	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	40752	40692	0	0
T11	166060	79808	0	0
T12	1126884	554078	0	0
T13	18444	9222	0	0
T14	370758	369935	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	3965127	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	1126884	15025	0	0
T13	18444	1088	0	0
T14	741516	11429	0	0
T15	0	11046	0	0
T16	0	15464	0	0
T17	0	6061	0	0
T26	0	5155	0	0
T28	0	5326	0	0
T30	61116	1183	0	0
T31	174362	0	0	0
T32	432	0	0	0
T33	0	5608	0	0
T34	0	3398	0	0
T38	299964	1040	0	0
T45	21072	0	0	0
T46	29536	0	0	0
T47	33152	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	3965127	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	1126884	15025	0	0
T13	18444	1088	0	0
T14	741516	11429	0	0
T15	0	11046	0	0
T16	0	15464	0	0
T17	0	6061	0	0
T26	0	5155	0	0
T28	0	5326	0	0
T30	61116	1183	0	0
T31	174362	0	0	0
T32	432	0	0	0
T33	0	5608	0	0
T34	0	3398	0	0
T38	299964	1040	0	0
T45	21072	0	0	0
T46	29536	0	0	0
T47	33152	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	654560339	0	0
T1	103592	103524	0	0
T2	705361	705062	0	0
T3	253431	253368	0	0
T4	223365	223297	0	0
T5	209170	208638	0	0
T6	1035	949	0	0
T7	15151	15093	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	40752	40692	0	0
T11	166060	79808	0	0
T12	1126884	554078	0	0
T13	18444	9222	0	0
T14	370758	369935	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	654560339	0	0
T1	103592	103524	0	0
T2	705361	705062	0	0
T3	253431	253368	0	0
T4	223365	223297	0	0
T5	209170	208638	0	0
T6	1035	949	0	0
T7	15151	15093	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	40752	40692	0	0
T11	166060	79808	0	0
T12	1126884	554078	0	0
T13	18444	9222	0	0
T14	370758	369935	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	3965127	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	1126884	15025	0	0
T13	18444	1088	0	0
T14	741516	11429	0	0
T15	0	11046	0	0
T16	0	15464	0	0
T17	0	6061	0	0
T26	0	5155	0	0
T28	0	5326	0	0
T30	61116	1183	0	0
T31	174362	0	0	0
T32	432	0	0	0
T33	0	5608	0	0
T34	0	3398	0	0
T38	299964	1040	0	0
T45	21072	0	0	0
T46	29536	0	0	0
T47	33152	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	3965127	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	1126884	15025	0	0
T13	18444	1088	0	0
T14	741516	11429	0	0
T15	0	11046	0	0
T16	0	15464	0	0
T17	0	6061	0	0
T26	0	5155	0	0
T28	0	5326	0	0
T30	61116	1183	0	0
T31	174362	0	0	0
T32	432	0	0	0
T33	0	5608	0	0
T34	0	3398	0	0
T38	299964	1040	0	0
T45	21072	0	0	0
T46	29536	0	0	0
T47	33152	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	3965127	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	1126884	15025	0	0
T13	18444	1088	0	0
T14	741516	11429	0	0
T15	0	11046	0	0
T16	0	15464	0	0
T17	0	6061	0	0
T26	0	5155	0	0
T28	0	5326	0	0
T30	61116	1183	0	0
T31	174362	0	0	0
T32	432	0	0	0
T33	0	5608	0	0
T34	0	3398	0	0
T38	299964	1040	0	0
T45	21072	0	0	0
T46	29536	0	0	0
T47	33152	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	3965127	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	1126884	15025	0	0
T13	18444	1088	0	0
T14	741516	11429	0	0
T15	0	11046	0	0
T16	0	15464	0	0
T17	0	6061	0	0
T26	0	5155	0	0
T28	0	5326	0	0
T30	61116	1183	0	0
T31	174362	0	0	0
T32	432	0	0	0
T33	0	5608	0	0
T34	0	3398	0	0
T38	299964	1040	0	0
T45	21072	0	0	0
T46	29536	0	0	0
T47	33152	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	8	0	975
T57	917838	1	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	466763	0	0	1
T66	499448	0	0	1
T67	996524	0	0	1
T68	5867	0	0	1
T69	462081	0	0	1
T70	28259	0	0	1
T71	43668	0	0	1
T72	207614	0	0	1
T73	12965	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	654560339	0	0
T1	103592	103524	0	0
T2	705361	705062	0	0
T3	253431	253368	0	0
T4	223365	223297	0	0
T5	209170	208638	0	0
T6	1035	949	0	0
T7	15151	15093	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	40752	40692	0	0
T11	166060	79808	0	0
T12	1126884	554078	0	0
T13	18444	9222	0	0
T14	370758	369935	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	816016478	3965127	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	1126884	15025	0	0
T13	18444	1088	0	0
T14	741516	11429	0	0
T15	0	11046	0	0
T16	0	15464	0	0
T17	0	6061	0	0
T26	0	5155	0	0
T28	0	5326	0	0
T30	61116	1183	0	0
T31	174362	0	0	0
T32	432	0	0	0
T33	0	5608	0	0
T34	0	3398	0	0
T38	299964	1040	0	0
T45	21072	0	0	0
T46	29536	0	0	0
T47	33152	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T30
1	0	Covered	T12,T14,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T14
1	0	Unreachable
1	1	Covered	T12,T14,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T14,T30
0	0	1	Unreachable
0	0	0	Covered	T11,T12,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	159897064	32198855	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	159897064	680214	0	0
GntImpliesValid_A	159897064	680214	0	0
GrantKnown_A	159897064	32198855	0	0
IdxKnown_A	159897064	32198855	0	0
IndexIsCorrect_A	159897064	680214	0	0
LockArbDecision_A	159897064	0	0	0
NoReadyValidNoGrant_A	159897064	0	0	0
ReadyAndValidImplyGrant_A	159897064	680214	0	0
ReqAndReadyImplyGrant_A	159897064	680214	0	0
ReqImpliesValid_A	159897064	680214	0	0
ReqStaysHighUntilGranted0_M	159897064	0	0	0
RoundRobin_A	159897064	0	0	0
ValidKnown_A	159897064	32198855	0	0
gen_data_port_assertion.DataFlow_A	159897064	680214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	32198855	0	0
T11	83030	79808	0	0
T12	563442	269800	0	0
T13	9222	0	0	0
T14	370758	64704	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	680214	0	0
T12	563442	4997	0	0
T13	9222	0	0	0
T14	370758	564	0	0
T15	0	6331	0	0
T16	0	7419	0	0
T26	0	5148	0	0
T30	30558	1183	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	3839	0	0
T34	0	3398	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	680214	0	0
T12	563442	4997	0	0
T13	9222	0	0	0
T14	370758	564	0	0
T15	0	6331	0	0
T16	0	7419	0	0
T26	0	5148	0	0
T30	30558	1183	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	3839	0	0
T34	0	3398	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	32198855	0	0
T11	83030	79808	0	0
T12	563442	269800	0	0
T13	9222	0	0	0
T14	370758	64704	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	32198855	0	0
T11	83030	79808	0	0
T12	563442	269800	0	0
T13	9222	0	0	0
T14	370758	64704	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	680214	0	0
T12	563442	4997	0	0
T13	9222	0	0	0
T14	370758	564	0	0
T15	0	6331	0	0
T16	0	7419	0	0
T26	0	5148	0	0
T30	30558	1183	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	3839	0	0
T34	0	3398	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	680214	0	0
T12	563442	4997	0	0
T13	9222	0	0	0
T14	370758	564	0	0
T15	0	6331	0	0
T16	0	7419	0	0
T26	0	5148	0	0
T30	30558	1183	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	3839	0	0
T34	0	3398	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	680214	0	0
T12	563442	4997	0	0
T13	9222	0	0	0
T14	370758	564	0	0
T15	0	6331	0	0
T16	0	7419	0	0
T26	0	5148	0	0
T30	30558	1183	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	3839	0	0
T34	0	3398	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	680214	0	0
T12	563442	4997	0	0
T13	9222	0	0	0
T14	370758	564	0	0
T15	0	6331	0	0
T16	0	7419	0	0
T26	0	5148	0	0
T30	30558	1183	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	3839	0	0
T34	0	3398	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	32198855	0	0
T11	83030	79808	0	0
T12	563442	269800	0	0
T13	9222	0	0	0
T14	370758	64704	0	0
T15	0	419600	0	0
T26	0	128304	0	0
T30	30558	29456	0	0
T31	87181	83840	0	0
T32	216	216	0	0
T33	0	79720	0	0
T34	0	224792	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	680214	0	0
T12	563442	4997	0	0
T13	9222	0	0	0
T14	370758	564	0	0
T15	0	6331	0	0
T16	0	7419	0	0
T26	0	5148	0	0
T30	30558	1183	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	3839	0	0
T34	0	3398	0	0
T38	149982	0	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0
T55	0	51	0	0
T56	0	2067	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T14,T38

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T38
1	0	Covered	T12,T14,T38

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T12,T14,T38

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T14,T38
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T38
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	159897064	126229821	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	159897064	941245	0	0
GntImpliesValid_A	159897064	941245	0	0
GrantKnown_A	159897064	126229821	0	0
IdxKnown_A	159897064	126229821	0	0
IndexIsCorrect_A	159897064	941245	0	0
LockArbDecision_A	159897064	0	0	0
NoReadyValidNoGrant_A	159897064	0	0	0
ReadyAndValidImplyGrant_A	159897064	941245	0	0
ReqAndReadyImplyGrant_A	159897064	941245	0	0
ReqImpliesValid_A	159897064	941245	0	0
ReqStaysHighUntilGranted0_M	159897064	0	0	0
RoundRobin_A	159897064	0	0	0
ValidKnown_A	159897064	126229821	0	0
gen_data_port_assertion.DataFlow_A	159897064	941245	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	126229821	0	0
T1	66982	66982	0	0
T2	100462	100260	0	0
T3	35668	35668	0	0
T4	23971	23971	0	0
T5	25303	24864	0	0
T7	4112	4112	0	0
T10	18813	18813	0	0
T11	83030	0	0	0
T12	563442	284278	0	0
T13	9222	9222	0	0
T14	0	305231	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	941245	0	0
T12	563442	1700	0	0
T13	9222	0	0	0
T14	370758	6930	0	0
T15	0	4715	0	0
T16	0	8045	0	0
T17	0	6061	0	0
T18	0	316	0	0
T26	0	7	0	0
T28	0	5326	0	0
T30	30558	0	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	1769	0	0
T38	149982	1040	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	941245	0	0
T12	563442	1700	0	0
T13	9222	0	0	0
T14	370758	6930	0	0
T15	0	4715	0	0
T16	0	8045	0	0
T17	0	6061	0	0
T18	0	316	0	0
T26	0	7	0	0
T28	0	5326	0	0
T30	30558	0	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	1769	0	0
T38	149982	1040	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	126229821	0	0
T1	66982	66982	0	0
T2	100462	100260	0	0
T3	35668	35668	0	0
T4	23971	23971	0	0
T5	25303	24864	0	0
T7	4112	4112	0	0
T10	18813	18813	0	0
T11	83030	0	0	0
T12	563442	284278	0	0
T13	9222	9222	0	0
T14	0	305231	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	126229821	0	0
T1	66982	66982	0	0
T2	100462	100260	0	0
T3	35668	35668	0	0
T4	23971	23971	0	0
T5	25303	24864	0	0
T7	4112	4112	0	0
T10	18813	18813	0	0
T11	83030	0	0	0
T12	563442	284278	0	0
T13	9222	9222	0	0
T14	0	305231	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	941245	0	0
T12	563442	1700	0	0
T13	9222	0	0	0
T14	370758	6930	0	0
T15	0	4715	0	0
T16	0	8045	0	0
T17	0	6061	0	0
T18	0	316	0	0
T26	0	7	0	0
T28	0	5326	0	0
T30	30558	0	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	1769	0	0
T38	149982	1040	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	941245	0	0
T12	563442	1700	0	0
T13	9222	0	0	0
T14	370758	6930	0	0
T15	0	4715	0	0
T16	0	8045	0	0
T17	0	6061	0	0
T18	0	316	0	0
T26	0	7	0	0
T28	0	5326	0	0
T30	30558	0	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	1769	0	0
T38	149982	1040	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	941245	0	0
T12	563442	1700	0	0
T13	9222	0	0	0
T14	370758	6930	0	0
T15	0	4715	0	0
T16	0	8045	0	0
T17	0	6061	0	0
T18	0	316	0	0
T26	0	7	0	0
T28	0	5326	0	0
T30	30558	0	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	1769	0	0
T38	149982	1040	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	941245	0	0
T12	563442	1700	0	0
T13	9222	0	0	0
T14	370758	6930	0	0
T15	0	4715	0	0
T16	0	8045	0	0
T17	0	6061	0	0
T18	0	316	0	0
T26	0	7	0	0
T28	0	5326	0	0
T30	30558	0	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	1769	0	0
T38	149982	1040	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	126229821	0	0
T1	66982	66982	0	0
T2	100462	100260	0	0
T3	35668	35668	0	0
T4	23971	23971	0	0
T5	25303	24864	0	0
T7	4112	4112	0	0
T10	18813	18813	0	0
T11	83030	0	0	0
T12	563442	284278	0	0
T13	9222	9222	0	0
T14	0	305231	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159897064	941245	0	0
T12	563442	1700	0	0
T13	9222	0	0	0
T14	370758	6930	0	0
T15	0	4715	0	0
T16	0	8045	0	0
T17	0	6061	0	0
T18	0	316	0	0
T26	0	7	0	0
T28	0	5326	0	0
T30	30558	0	0	0
T31	87181	0	0	0
T32	216	0	0	0
T33	0	1769	0	0
T38	149982	1040	0	0
T45	10536	0	0	0
T46	14768	0	0	0
T47	16576	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T14,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T30
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	496222350	496131663	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	496222350	2343668	0	0
GntImpliesValid_A	496222350	2343668	0	0
GrantKnown_A	496222350	496131663	0	0
IdxKnown_A	496222350	496131663	0	0
IndexIsCorrect_A	496222350	2343668	0	0
LockArbDecision_A	496222350	0	0	0
NoReadyValidNoGrant_A	496222350	0	0	0
ReadyAndValidImplyGrant_A	496222350	2343668	0	0
ReqAndReadyImplyGrant_A	496222350	2343668	0	0
ReqImpliesValid_A	496222350	2343668	0	0
ReqStaysHighUntilGranted0_M	496222350	0	0	0
RoundRobin_A	496222350	8	0	975
ValidKnown_A	496222350	496131663	0	0
gen_data_port_assertion.DataFlow_A	496222350	2343668	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	496131663	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	2343668	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	8328	0	0
T13	0	1088	0	0
T14	0	3935	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	2343668	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	8328	0	0
T13	0	1088	0	0
T14	0	3935	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	496131663	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	496131663	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	2343668	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	8328	0	0
T13	0	1088	0	0
T14	0	3935	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	2343668	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	8328	0	0
T13	0	1088	0	0
T14	0	3935	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	2343668	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	8328	0	0
T13	0	1088	0	0
T14	0	3935	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	2343668	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	8328	0	0
T13	0	1088	0	0
T14	0	3935	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	8	0	975
T57	917838	1	0	1
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	466763	0	0	1
T66	499448	0	0	1
T67	996524	0	0	1
T68	5867	0	0	1
T69	462081	0	0	1
T70	28259	0	0	1
T71	43668	0	0	1
T72	207614	0	0	1
T73	12965	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	496131663	0	0
T1	36610	36542	0	0
T2	604899	604802	0	0
T3	217763	217700	0	0
T4	199394	199326	0	0
T5	183867	183774	0	0
T6	1035	949	0	0
T7	11039	10981	0	0
T8	1402	1326	0	0
T9	1897	1835	0	0
T10	21939	21879	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496222350	2343668	0	0
T1	36610	832	0	0
T2	604899	832	0	0
T3	217763	832	0	0
T4	199394	832	0	0
T5	183867	832	0	0
T6	1035	0	0	0
T7	11039	832	0	0
T8	1402	0	0	0
T9	1897	0	0	0
T10	21939	832	0	0
T12	0	8328	0	0
T13	0	1088	0	0
T14	0	3935	0	0