Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3699 | 
0 | 
0 | 
| T103 | 
8659 | 
6 | 
0 | 
0 | 
| T104 | 
4697 | 
16 | 
0 | 
0 | 
| T105 | 
8692 | 
57 | 
0 | 
0 | 
| T106 | 
5807 | 
269 | 
0 | 
0 | 
| T107 | 
29631 | 
2 | 
0 | 
0 | 
| T108 | 
3740 | 
16 | 
0 | 
0 | 
| T110 | 
4885 | 
197 | 
0 | 
0 | 
| T119 | 
3571 | 
122 | 
0 | 
0 | 
| T122 | 
5551 | 
21 | 
0 | 
0 | 
| T125 | 
9566 | 
7 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1352 | 
0 | 
0 | 
| T103 | 
8659 | 
15 | 
0 | 
0 | 
| T109 | 
5918 | 
15 | 
0 | 
0 | 
| T114 | 
18181 | 
6 | 
0 | 
0 | 
| T125 | 
9566 | 
21 | 
0 | 
0 | 
| T129 | 
10434 | 
8 | 
0 | 
0 | 
| T131 | 
8823 | 
13 | 
0 | 
0 | 
| T134 | 
11738 | 
9 | 
0 | 
0 | 
| T159 | 
32310 | 
26 | 
0 | 
0 | 
| T160 | 
4528 | 
6 | 
0 | 
0 | 
| T161 | 
32740 | 
46 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1329 | 
0 | 
0 | 
| T103 | 
8659 | 
7 | 
0 | 
0 | 
| T109 | 
5918 | 
10 | 
0 | 
0 | 
| T125 | 
9566 | 
4 | 
0 | 
0 | 
| T129 | 
10434 | 
15 | 
0 | 
0 | 
| T131 | 
8823 | 
3 | 
0 | 
0 | 
| T134 | 
11738 | 
12 | 
0 | 
0 | 
| T159 | 
32310 | 
18 | 
0 | 
0 | 
| T160 | 
4528 | 
9 | 
0 | 
0 | 
| T162 | 
3384 | 
4 | 
0 | 
0 | 
| T163 | 
5767 | 
3 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1705 | 
0 | 
0 | 
| T103 | 
8659 | 
15 | 
0 | 
0 | 
| T109 | 
5918 | 
7 | 
0 | 
0 | 
| T125 | 
9566 | 
4 | 
0 | 
0 | 
| T129 | 
10434 | 
18 | 
0 | 
0 | 
| T131 | 
8823 | 
2 | 
0 | 
0 | 
| T134 | 
11738 | 
26 | 
0 | 
0 | 
| T159 | 
32310 | 
48 | 
0 | 
0 | 
| T160 | 
4528 | 
5 | 
0 | 
0 | 
| T161 | 
32740 | 
66 | 
0 | 
0 | 
| T163 | 
5767 | 
12 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
7248 | 
0 | 
0 | 
| T103 | 
8659 | 
14 | 
0 | 
0 | 
| T109 | 
5918 | 
18 | 
0 | 
0 | 
| T125 | 
9566 | 
67 | 
0 | 
0 | 
| T129 | 
10434 | 
143 | 
0 | 
0 | 
| T131 | 
8823 | 
285 | 
0 | 
0 | 
| T134 | 
11738 | 
250 | 
0 | 
0 | 
| T159 | 
32310 | 
268 | 
0 | 
0 | 
| T160 | 
4528 | 
108 | 
0 | 
0 | 
| T161 | 
32740 | 
586 | 
0 | 
0 | 
| T163 | 
5767 | 
26 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
8466 | 
0 | 
0 | 
| T103 | 
8659 | 
2 | 
0 | 
0 | 
| T109 | 
5918 | 
138 | 
0 | 
0 | 
| T125 | 
9566 | 
88 | 
0 | 
0 | 
| T129 | 
10434 | 
243 | 
0 | 
0 | 
| T131 | 
8823 | 
244 | 
0 | 
0 | 
| T134 | 
11738 | 
222 | 
0 | 
0 | 
| T159 | 
32310 | 
287 | 
0 | 
0 | 
| T160 | 
4528 | 
129 | 
0 | 
0 | 
| T162 | 
3384 | 
6 | 
0 | 
0 | 
| T163 | 
5767 | 
4 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
7759 | 
0 | 
0 | 
| T103 | 
8659 | 
67 | 
0 | 
0 | 
| T109 | 
5918 | 
6 | 
0 | 
0 | 
| T125 | 
9566 | 
61 | 
0 | 
0 | 
| T129 | 
10434 | 
203 | 
0 | 
0 | 
| T131 | 
8823 | 
257 | 
0 | 
0 | 
| T134 | 
11738 | 
221 | 
0 | 
0 | 
| T159 | 
32310 | 
215 | 
0 | 
0 | 
| T160 | 
4528 | 
164 | 
0 | 
0 | 
| T162 | 
3384 | 
9 | 
0 | 
0 | 
| T163 | 
5767 | 
13 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
8086 | 
0 | 
0 | 
| T103 | 
8659 | 
48 | 
0 | 
0 | 
| T109 | 
5918 | 
7 | 
0 | 
0 | 
| T120 | 
8056 | 
1 | 
0 | 
0 | 
| T125 | 
9566 | 
79 | 
0 | 
0 | 
| T129 | 
10434 | 
162 | 
0 | 
0 | 
| T131 | 
8823 | 
116 | 
0 | 
0 | 
| T159 | 
32310 | 
357 | 
0 | 
0 | 
| T160 | 
4528 | 
124 | 
0 | 
0 | 
| T162 | 
3384 | 
57 | 
0 | 
0 | 
| T163 | 
5767 | 
37 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
6550 | 
0 | 
0 | 
| T103 | 
8659 | 
9 | 
0 | 
0 | 
| T109 | 
5918 | 
7 | 
0 | 
0 | 
| T125 | 
9566 | 
95 | 
0 | 
0 | 
| T129 | 
10434 | 
121 | 
0 | 
0 | 
| T131 | 
8823 | 
159 | 
0 | 
0 | 
| T134 | 
11738 | 
80 | 
0 | 
0 | 
| T159 | 
32310 | 
604 | 
0 | 
0 | 
| T160 | 
4528 | 
9 | 
0 | 
0 | 
| T161 | 
32740 | 
414 | 
0 | 
0 | 
| T162 | 
3384 | 
2 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
7431 | 
0 | 
0 | 
| T103 | 
8659 | 
1 | 
0 | 
0 | 
| T109 | 
5918 | 
95 | 
0 | 
0 | 
| T125 | 
9566 | 
8 | 
0 | 
0 | 
| T129 | 
10434 | 
146 | 
0 | 
0 | 
| T131 | 
8823 | 
13 | 
0 | 
0 | 
| T134 | 
11738 | 
235 | 
0 | 
0 | 
| T159 | 
32310 | 
527 | 
0 | 
0 | 
| T160 | 
4528 | 
115 | 
0 | 
0 | 
| T162 | 
3384 | 
69 | 
0 | 
0 | 
| T163 | 
5767 | 
9 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
8070 | 
0 | 
0 | 
| T103 | 
8659 | 
93 | 
0 | 
0 | 
| T109 | 
5918 | 
115 | 
0 | 
0 | 
| T125 | 
9566 | 
70 | 
0 | 
0 | 
| T129 | 
10434 | 
134 | 
0 | 
0 | 
| T131 | 
8823 | 
244 | 
0 | 
0 | 
| T134 | 
11738 | 
231 | 
0 | 
0 | 
| T159 | 
32310 | 
394 | 
0 | 
0 | 
| T160 | 
4528 | 
130 | 
0 | 
0 | 
| T161 | 
32740 | 
726 | 
0 | 
0 | 
| T163 | 
5767 | 
7 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
7497 | 
0 | 
0 | 
| T103 | 
8659 | 
61 | 
0 | 
0 | 
| T109 | 
5918 | 
112 | 
0 | 
0 | 
| T125 | 
9566 | 
68 | 
0 | 
0 | 
| T129 | 
10434 | 
233 | 
0 | 
0 | 
| T131 | 
8823 | 
109 | 
0 | 
0 | 
| T134 | 
11738 | 
377 | 
0 | 
0 | 
| T159 | 
32310 | 
349 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T162 | 
3384 | 
10 | 
0 | 
0 | 
| T163 | 
5767 | 
1 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3907 | 
0 | 
0 | 
| T103 | 
8659 | 
4 | 
0 | 
0 | 
| T109 | 
5918 | 
67 | 
0 | 
0 | 
| T125 | 
9566 | 
22 | 
0 | 
0 | 
| T129 | 
10434 | 
91 | 
0 | 
0 | 
| T131 | 
8823 | 
38 | 
0 | 
0 | 
| T134 | 
11738 | 
89 | 
0 | 
0 | 
| T159 | 
32310 | 
182 | 
0 | 
0 | 
| T160 | 
4528 | 
51 | 
0 | 
0 | 
| T162 | 
3384 | 
20 | 
0 | 
0 | 
| T163 | 
5767 | 
17 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3590 | 
0 | 
0 | 
| T103 | 
8659 | 
22 | 
0 | 
0 | 
| T109 | 
5918 | 
32 | 
0 | 
0 | 
| T125 | 
9566 | 
49 | 
0 | 
0 | 
| T129 | 
10434 | 
72 | 
0 | 
0 | 
| T131 | 
8823 | 
105 | 
0 | 
0 | 
| T134 | 
11738 | 
9 | 
0 | 
0 | 
| T159 | 
32310 | 
111 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T162 | 
3384 | 
28 | 
0 | 
0 | 
| T163 | 
5767 | 
2 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
4205 | 
0 | 
0 | 
| T103 | 
8659 | 
34 | 
0 | 
0 | 
| T109 | 
5918 | 
11 | 
0 | 
0 | 
| T125 | 
9566 | 
12 | 
0 | 
0 | 
| T129 | 
10434 | 
98 | 
0 | 
0 | 
| T131 | 
8823 | 
95 | 
0 | 
0 | 
| T134 | 
11738 | 
102 | 
0 | 
0 | 
| T159 | 
32310 | 
146 | 
0 | 
0 | 
| T160 | 
4528 | 
1 | 
0 | 
0 | 
| T162 | 
3384 | 
33 | 
0 | 
0 | 
| T163 | 
5767 | 
9 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3339 | 
0 | 
0 | 
| T103 | 
8659 | 
25 | 
0 | 
0 | 
| T109 | 
5918 | 
5 | 
0 | 
0 | 
| T125 | 
9566 | 
37 | 
0 | 
0 | 
| T129 | 
10434 | 
100 | 
0 | 
0 | 
| T131 | 
8823 | 
10 | 
0 | 
0 | 
| T134 | 
11738 | 
57 | 
0 | 
0 | 
| T159 | 
32310 | 
113 | 
0 | 
0 | 
| T160 | 
4528 | 
1 | 
0 | 
0 | 
| T162 | 
3384 | 
19 | 
0 | 
0 | 
| T163 | 
5767 | 
15 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
4313 | 
0 | 
0 | 
| T103 | 
8659 | 
26 | 
0 | 
0 | 
| T109 | 
5918 | 
62 | 
0 | 
0 | 
| T125 | 
9566 | 
41 | 
0 | 
0 | 
| T129 | 
10434 | 
113 | 
0 | 
0 | 
| T131 | 
8823 | 
53 | 
0 | 
0 | 
| T134 | 
11738 | 
85 | 
0 | 
0 | 
| T159 | 
32310 | 
202 | 
0 | 
0 | 
| T160 | 
4528 | 
49 | 
0 | 
0 | 
| T162 | 
3384 | 
36 | 
0 | 
0 | 
| T163 | 
5767 | 
6 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3852 | 
0 | 
0 | 
| T103 | 
8659 | 
11 | 
0 | 
0 | 
| T109 | 
5918 | 
56 | 
0 | 
0 | 
| T125 | 
9566 | 
43 | 
0 | 
0 | 
| T129 | 
10434 | 
57 | 
0 | 
0 | 
| T131 | 
8823 | 
14 | 
0 | 
0 | 
| T134 | 
11738 | 
103 | 
0 | 
0 | 
| T159 | 
32310 | 
259 | 
0 | 
0 | 
| T160 | 
4528 | 
42 | 
0 | 
0 | 
| T161 | 
32740 | 
341 | 
0 | 
0 | 
| T163 | 
5767 | 
38 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3794 | 
0 | 
0 | 
| T103 | 
8659 | 
16 | 
0 | 
0 | 
| T109 | 
5918 | 
54 | 
0 | 
0 | 
| T125 | 
9566 | 
40 | 
0 | 
0 | 
| T129 | 
10434 | 
112 | 
0 | 
0 | 
| T131 | 
8823 | 
5 | 
0 | 
0 | 
| T134 | 
11738 | 
95 | 
0 | 
0 | 
| T159 | 
32310 | 
80 | 
0 | 
0 | 
| T160 | 
4528 | 
53 | 
0 | 
0 | 
| T162 | 
3384 | 
12 | 
0 | 
0 | 
| T163 | 
5767 | 
17 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3678 | 
0 | 
0 | 
| T103 | 
8659 | 
43 | 
0 | 
0 | 
| T109 | 
5918 | 
38 | 
0 | 
0 | 
| T125 | 
9566 | 
65 | 
0 | 
0 | 
| T129 | 
10434 | 
114 | 
0 | 
0 | 
| T131 | 
8823 | 
16 | 
0 | 
0 | 
| T134 | 
11738 | 
97 | 
0 | 
0 | 
| T159 | 
32310 | 
235 | 
0 | 
0 | 
| T160 | 
4528 | 
1 | 
0 | 
0 | 
| T162 | 
3384 | 
1 | 
0 | 
0 | 
| T163 | 
5767 | 
23 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3920 | 
0 | 
0 | 
| T103 | 
8659 | 
40 | 
0 | 
0 | 
| T109 | 
5918 | 
42 | 
0 | 
0 | 
| T125 | 
9566 | 
50 | 
0 | 
0 | 
| T129 | 
10434 | 
6 | 
0 | 
0 | 
| T131 | 
8823 | 
57 | 
0 | 
0 | 
| T134 | 
11738 | 
97 | 
0 | 
0 | 
| T159 | 
32310 | 
232 | 
0 | 
0 | 
| T160 | 
4528 | 
46 | 
0 | 
0 | 
| T161 | 
32740 | 
176 | 
0 | 
0 | 
| T162 | 
3384 | 
9 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3513 | 
0 | 
0 | 
| T103 | 
8659 | 
30 | 
0 | 
0 | 
| T109 | 
5918 | 
46 | 
0 | 
0 | 
| T125 | 
9566 | 
26 | 
0 | 
0 | 
| T129 | 
10434 | 
31 | 
0 | 
0 | 
| T131 | 
8823 | 
51 | 
0 | 
0 | 
| T134 | 
11738 | 
71 | 
0 | 
0 | 
| T159 | 
32310 | 
214 | 
0 | 
0 | 
| T160 | 
4528 | 
48 | 
0 | 
0 | 
| T161 | 
32740 | 
233 | 
0 | 
0 | 
| T163 | 
5767 | 
22 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
4070 | 
0 | 
0 | 
| T103 | 
8659 | 
16 | 
0 | 
0 | 
| T109 | 
5918 | 
8 | 
0 | 
0 | 
| T125 | 
9566 | 
5 | 
0 | 
0 | 
| T129 | 
10434 | 
81 | 
0 | 
0 | 
| T131 | 
8823 | 
57 | 
0 | 
0 | 
| T134 | 
11738 | 
150 | 
0 | 
0 | 
| T159 | 
32310 | 
144 | 
0 | 
0 | 
| T160 | 
4528 | 
55 | 
0 | 
0 | 
| T162 | 
3384 | 
5 | 
0 | 
0 | 
| T163 | 
5767 | 
1 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3878 | 
0 | 
0 | 
| T103 | 
8659 | 
35 | 
0 | 
0 | 
| T109 | 
5918 | 
41 | 
0 | 
0 | 
| T117 | 
5882 | 
4 | 
0 | 
0 | 
| T125 | 
9566 | 
44 | 
0 | 
0 | 
| T129 | 
10434 | 
55 | 
0 | 
0 | 
| T134 | 
11738 | 
54 | 
0 | 
0 | 
| T159 | 
32310 | 
178 | 
0 | 
0 | 
| T160 | 
4528 | 
2 | 
0 | 
0 | 
| T161 | 
32740 | 
268 | 
0 | 
0 | 
| T162 | 
3384 | 
4 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3441 | 
0 | 
0 | 
| T103 | 
8659 | 
49 | 
0 | 
0 | 
| T109 | 
5918 | 
43 | 
0 | 
0 | 
| T125 | 
9566 | 
73 | 
0 | 
0 | 
| T129 | 
10434 | 
61 | 
0 | 
0 | 
| T131 | 
8823 | 
73 | 
0 | 
0 | 
| T134 | 
11738 | 
62 | 
0 | 
0 | 
| T159 | 
32310 | 
107 | 
0 | 
0 | 
| T160 | 
4528 | 
7 | 
0 | 
0 | 
| T161 | 
32740 | 
161 | 
0 | 
0 | 
| T163 | 
5767 | 
13 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3530 | 
0 | 
0 | 
| T103 | 
8659 | 
3 | 
0 | 
0 | 
| T109 | 
5918 | 
5 | 
0 | 
0 | 
| T125 | 
9566 | 
59 | 
0 | 
0 | 
| T129 | 
10434 | 
39 | 
0 | 
0 | 
| T131 | 
8823 | 
54 | 
0 | 
0 | 
| T134 | 
11738 | 
53 | 
0 | 
0 | 
| T159 | 
32310 | 
96 | 
0 | 
0 | 
| T160 | 
4528 | 
39 | 
0 | 
0 | 
| T162 | 
3384 | 
26 | 
0 | 
0 | 
| T163 | 
5767 | 
9 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3799 | 
0 | 
0 | 
| T103 | 
8659 | 
64 | 
0 | 
0 | 
| T109 | 
5918 | 
62 | 
0 | 
0 | 
| T120 | 
8056 | 
6 | 
0 | 
0 | 
| T125 | 
9566 | 
63 | 
0 | 
0 | 
| T129 | 
10434 | 
167 | 
0 | 
0 | 
| T131 | 
8823 | 
37 | 
0 | 
0 | 
| T134 | 
11738 | 
109 | 
0 | 
0 | 
| T159 | 
32310 | 
157 | 
0 | 
0 | 
| T160 | 
4528 | 
53 | 
0 | 
0 | 
| T163 | 
5767 | 
17 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3604 | 
0 | 
0 | 
| T103 | 
8659 | 
2 | 
0 | 
0 | 
| T109 | 
5918 | 
51 | 
0 | 
0 | 
| T117 | 
5882 | 
2 | 
0 | 
0 | 
| T125 | 
9566 | 
7 | 
0 | 
0 | 
| T129 | 
10434 | 
132 | 
0 | 
0 | 
| T131 | 
8823 | 
52 | 
0 | 
0 | 
| T159 | 
32310 | 
172 | 
0 | 
0 | 
| T160 | 
4528 | 
64 | 
0 | 
0 | 
| T162 | 
3384 | 
1 | 
0 | 
0 | 
| T163 | 
5767 | 
5 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3690 | 
0 | 
0 | 
| T103 | 
8659 | 
13 | 
0 | 
0 | 
| T109 | 
5918 | 
44 | 
0 | 
0 | 
| T125 | 
9566 | 
39 | 
0 | 
0 | 
| T129 | 
10434 | 
146 | 
0 | 
0 | 
| T131 | 
8823 | 
46 | 
0 | 
0 | 
| T134 | 
11738 | 
75 | 
0 | 
0 | 
| T159 | 
32310 | 
86 | 
0 | 
0 | 
| T160 | 
4528 | 
2 | 
0 | 
0 | 
| T162 | 
3384 | 
1 | 
0 | 
0 | 
| T163 | 
5767 | 
19 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3808 | 
0 | 
0 | 
| T103 | 
8659 | 
4 | 
0 | 
0 | 
| T125 | 
9566 | 
36 | 
0 | 
0 | 
| T129 | 
10434 | 
11 | 
0 | 
0 | 
| T131 | 
8823 | 
10 | 
0 | 
0 | 
| T134 | 
11738 | 
125 | 
0 | 
0 | 
| T159 | 
32310 | 
180 | 
0 | 
0 | 
| T160 | 
4528 | 
6 | 
0 | 
0 | 
| T161 | 
32740 | 
240 | 
0 | 
0 | 
| T162 | 
3384 | 
25 | 
0 | 
0 | 
| T163 | 
5767 | 
21 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3799 | 
0 | 
0 | 
| T103 | 
8659 | 
59 | 
0 | 
0 | 
| T109 | 
5918 | 
39 | 
0 | 
0 | 
| T114 | 
18181 | 
5 | 
0 | 
0 | 
| T125 | 
9566 | 
32 | 
0 | 
0 | 
| T129 | 
10434 | 
10 | 
0 | 
0 | 
| T131 | 
8823 | 
37 | 
0 | 
0 | 
| T134 | 
11738 | 
108 | 
0 | 
0 | 
| T159 | 
32310 | 
142 | 
0 | 
0 | 
| T160 | 
4528 | 
54 | 
0 | 
0 | 
| T163 | 
5767 | 
2 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
4174 | 
0 | 
0 | 
| T103 | 
8659 | 
38 | 
0 | 
0 | 
| T109 | 
5918 | 
49 | 
0 | 
0 | 
| T125 | 
9566 | 
23 | 
0 | 
0 | 
| T129 | 
10434 | 
68 | 
0 | 
0 | 
| T131 | 
8823 | 
90 | 
0 | 
0 | 
| T134 | 
11738 | 
54 | 
0 | 
0 | 
| T159 | 
32310 | 
149 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T162 | 
3384 | 
18 | 
0 | 
0 | 
| T163 | 
5767 | 
14 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3994 | 
0 | 
0 | 
| T103 | 
8659 | 
19 | 
0 | 
0 | 
| T109 | 
5918 | 
31 | 
0 | 
0 | 
| T125 | 
9566 | 
30 | 
0 | 
0 | 
| T129 | 
10434 | 
61 | 
0 | 
0 | 
| T131 | 
8823 | 
70 | 
0 | 
0 | 
| T134 | 
11738 | 
86 | 
0 | 
0 | 
| T159 | 
32310 | 
77 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T162 | 
3384 | 
35 | 
0 | 
0 | 
| T163 | 
5767 | 
8 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3259 | 
0 | 
0 | 
| T103 | 
8659 | 
6 | 
0 | 
0 | 
| T109 | 
5918 | 
46 | 
0 | 
0 | 
| T125 | 
9566 | 
43 | 
0 | 
0 | 
| T129 | 
10434 | 
97 | 
0 | 
0 | 
| T131 | 
8823 | 
42 | 
0 | 
0 | 
| T134 | 
11738 | 
67 | 
0 | 
0 | 
| T159 | 
32310 | 
206 | 
0 | 
0 | 
| T160 | 
4528 | 
2 | 
0 | 
0 | 
| T162 | 
3384 | 
10 | 
0 | 
0 | 
| T163 | 
5767 | 
5 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
4084 | 
0 | 
0 | 
| T103 | 
8659 | 
22 | 
0 | 
0 | 
| T109 | 
5918 | 
9 | 
0 | 
0 | 
| T125 | 
9566 | 
46 | 
0 | 
0 | 
| T129 | 
10434 | 
172 | 
0 | 
0 | 
| T131 | 
8823 | 
56 | 
0 | 
0 | 
| T134 | 
11738 | 
78 | 
0 | 
0 | 
| T159 | 
32310 | 
186 | 
0 | 
0 | 
| T160 | 
4528 | 
6 | 
0 | 
0 | 
| T162 | 
3384 | 
5 | 
0 | 
0 | 
| T163 | 
5767 | 
21 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3831 | 
0 | 
0 | 
| T103 | 
8659 | 
35 | 
0 | 
0 | 
| T105 | 
8692 | 
3 | 
0 | 
0 | 
| T109 | 
5918 | 
8 | 
0 | 
0 | 
| T125 | 
9566 | 
25 | 
0 | 
0 | 
| T129 | 
10434 | 
52 | 
0 | 
0 | 
| T131 | 
8823 | 
125 | 
0 | 
0 | 
| T134 | 
11738 | 
100 | 
0 | 
0 | 
| T159 | 
32310 | 
227 | 
0 | 
0 | 
| T160 | 
4528 | 
66 | 
0 | 
0 | 
| T163 | 
5767 | 
41 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1534 | 
0 | 
0 | 
| T103 | 
8659 | 
11 | 
0 | 
0 | 
| T109 | 
5918 | 
9 | 
0 | 
0 | 
| T125 | 
9566 | 
13 | 
0 | 
0 | 
| T129 | 
10434 | 
17 | 
0 | 
0 | 
| T131 | 
8823 | 
7 | 
0 | 
0 | 
| T134 | 
11738 | 
19 | 
0 | 
0 | 
| T159 | 
32310 | 
40 | 
0 | 
0 | 
| T160 | 
4528 | 
1 | 
0 | 
0 | 
| T161 | 
32740 | 
63 | 
0 | 
0 | 
| T163 | 
5767 | 
3 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1510 | 
0 | 
0 | 
| T103 | 
8659 | 
4 | 
0 | 
0 | 
| T109 | 
5918 | 
3 | 
0 | 
0 | 
| T125 | 
9566 | 
6 | 
0 | 
0 | 
| T129 | 
10434 | 
25 | 
0 | 
0 | 
| T131 | 
8823 | 
15 | 
0 | 
0 | 
| T134 | 
11738 | 
22 | 
0 | 
0 | 
| T159 | 
32310 | 
39 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T161 | 
32740 | 
45 | 
0 | 
0 | 
| T163 | 
5767 | 
9 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1551 | 
0 | 
0 | 
| T103 | 
8659 | 
1 | 
0 | 
0 | 
| T109 | 
5918 | 
11 | 
0 | 
0 | 
| T125 | 
9566 | 
3 | 
0 | 
0 | 
| T129 | 
10434 | 
7 | 
0 | 
0 | 
| T131 | 
8823 | 
7 | 
0 | 
0 | 
| T134 | 
11738 | 
22 | 
0 | 
0 | 
| T159 | 
32310 | 
21 | 
0 | 
0 | 
| T160 | 
4528 | 
2 | 
0 | 
0 | 
| T162 | 
3384 | 
3 | 
0 | 
0 | 
| T163 | 
5767 | 
22 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1585 | 
0 | 
0 | 
| T103 | 
8659 | 
6 | 
0 | 
0 | 
| T109 | 
5918 | 
8 | 
0 | 
0 | 
| T125 | 
9566 | 
9 | 
0 | 
0 | 
| T129 | 
10434 | 
19 | 
0 | 
0 | 
| T131 | 
8823 | 
11 | 
0 | 
0 | 
| T134 | 
11738 | 
19 | 
0 | 
0 | 
| T159 | 
32310 | 
26 | 
0 | 
0 | 
| T160 | 
4528 | 
7 | 
0 | 
0 | 
| T162 | 
3384 | 
8 | 
0 | 
0 | 
| T163 | 
5767 | 
18 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1963 | 
0 | 
0 | 
| T103 | 
8659 | 
14 | 
0 | 
0 | 
| T109 | 
5918 | 
21 | 
0 | 
0 | 
| T125 | 
9566 | 
6 | 
0 | 
0 | 
| T129 | 
10434 | 
28 | 
0 | 
0 | 
| T131 | 
8823 | 
17 | 
0 | 
0 | 
| T134 | 
11738 | 
27 | 
0 | 
0 | 
| T159 | 
32310 | 
41 | 
0 | 
0 | 
| T160 | 
4528 | 
14 | 
0 | 
0 | 
| T162 | 
3384 | 
12 | 
0 | 
0 | 
| T163 | 
5767 | 
23 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
3525 | 
0 | 
0 | 
| T17 | 
362173 | 
15 | 
0 | 
0 | 
| T20 | 
0 | 
40 | 
0 | 
0 | 
| T22 | 
0 | 
2 | 
0 | 
0 | 
| T41 | 
0 | 
70 | 
0 | 
0 | 
| T51 | 
284583 | 
0 | 
0 | 
0 | 
| T60 | 
0 | 
35 | 
0 | 
0 | 
| T164 | 
0 | 
51 | 
0 | 
0 | 
| T165 | 
0 | 
8 | 
0 | 
0 | 
| T166 | 
0 | 
3 | 
0 | 
0 | 
| T167 | 
0 | 
21 | 
0 | 
0 | 
| T168 | 
0 | 
49 | 
0 | 
0 | 
| T169 | 
85587 | 
0 | 
0 | 
0 | 
| T170 | 
312824 | 
0 | 
0 | 
0 | 
| T171 | 
545917 | 
0 | 
0 | 
0 | 
| T172 | 
8131 | 
0 | 
0 | 
0 | 
| T173 | 
388457 | 
0 | 
0 | 
0 | 
| T174 | 
3273 | 
0 | 
0 | 
0 | 
| T175 | 
67513 | 
0 | 
0 | 
0 | 
| T176 | 
244246 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1471 | 
0 | 
0 | 
| T103 | 
8659 | 
18 | 
0 | 
0 | 
| T109 | 
5918 | 
7 | 
0 | 
0 | 
| T129 | 
10434 | 
22 | 
0 | 
0 | 
| T131 | 
8823 | 
10 | 
0 | 
0 | 
| T134 | 
11738 | 
15 | 
0 | 
0 | 
| T159 | 
32310 | 
32 | 
0 | 
0 | 
| T160 | 
4528 | 
11 | 
0 | 
0 | 
| T161 | 
32740 | 
76 | 
0 | 
0 | 
| T162 | 
3384 | 
12 | 
0 | 
0 | 
| T163 | 
5767 | 
16 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1433 | 
0 | 
0 | 
| T103 | 
8659 | 
4 | 
0 | 
0 | 
| T109 | 
5918 | 
11 | 
0 | 
0 | 
| T125 | 
9566 | 
8 | 
0 | 
0 | 
| T129 | 
10434 | 
22 | 
0 | 
0 | 
| T131 | 
8823 | 
12 | 
0 | 
0 | 
| T134 | 
11738 | 
14 | 
0 | 
0 | 
| T159 | 
32310 | 
12 | 
0 | 
0 | 
| T160 | 
4528 | 
7 | 
0 | 
0 | 
| T162 | 
3384 | 
7 | 
0 | 
0 | 
| T163 | 
5767 | 
2 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1264 | 
0 | 
0 | 
| T103 | 
8659 | 
17 | 
0 | 
0 | 
| T109 | 
5918 | 
9 | 
0 | 
0 | 
| T125 | 
9566 | 
5 | 
0 | 
0 | 
| T129 | 
10434 | 
15 | 
0 | 
0 | 
| T131 | 
8823 | 
8 | 
0 | 
0 | 
| T134 | 
11738 | 
16 | 
0 | 
0 | 
| T159 | 
32310 | 
8 | 
0 | 
0 | 
| T160 | 
4528 | 
6 | 
0 | 
0 | 
| T161 | 
32740 | 
56 | 
0 | 
0 | 
| T162 | 
3384 | 
9 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1177 | 
0 | 
0 | 
| T103 | 
8659 | 
2 | 
0 | 
0 | 
| T109 | 
5918 | 
7 | 
0 | 
0 | 
| T125 | 
9566 | 
14 | 
0 | 
0 | 
| T129 | 
10434 | 
10 | 
0 | 
0 | 
| T131 | 
8823 | 
8 | 
0 | 
0 | 
| T134 | 
11738 | 
14 | 
0 | 
0 | 
| T159 | 
32310 | 
7 | 
0 | 
0 | 
| T160 | 
4528 | 
6 | 
0 | 
0 | 
| T161 | 
32740 | 
37 | 
0 | 
0 | 
| T163 | 
5767 | 
2 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1281 | 
0 | 
0 | 
| T109 | 
5918 | 
1 | 
0 | 
0 | 
| T114 | 
18181 | 
7 | 
0 | 
0 | 
| T125 | 
9566 | 
14 | 
0 | 
0 | 
| T129 | 
10434 | 
22 | 
0 | 
0 | 
| T131 | 
8823 | 
5 | 
0 | 
0 | 
| T134 | 
11738 | 
7 | 
0 | 
0 | 
| T159 | 
32310 | 
21 | 
0 | 
0 | 
| T160 | 
4528 | 
1 | 
0 | 
0 | 
| T161 | 
32740 | 
34 | 
0 | 
0 | 
| T177 | 
10067 | 
7 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1233 | 
0 | 
0 | 
| T103 | 
8659 | 
4 | 
0 | 
0 | 
| T109 | 
5918 | 
5 | 
0 | 
0 | 
| T125 | 
9566 | 
4 | 
0 | 
0 | 
| T129 | 
10434 | 
18 | 
0 | 
0 | 
| T131 | 
8823 | 
3 | 
0 | 
0 | 
| T134 | 
11738 | 
5 | 
0 | 
0 | 
| T159 | 
32310 | 
25 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T161 | 
32740 | 
47 | 
0 | 
0 | 
| T163 | 
5767 | 
7 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1965 | 
0 | 
0 | 
| T103 | 
8659 | 
4 | 
0 | 
0 | 
| T109 | 
5918 | 
1 | 
0 | 
0 | 
| T125 | 
9566 | 
13 | 
0 | 
0 | 
| T129 | 
10434 | 
36 | 
0 | 
0 | 
| T131 | 
8823 | 
30 | 
0 | 
0 | 
| T134 | 
11738 | 
27 | 
0 | 
0 | 
| T159 | 
32310 | 
48 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T161 | 
32740 | 
129 | 
0 | 
0 | 
| T162 | 
3384 | 
15 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1335 | 
0 | 
0 | 
| T103 | 
8659 | 
10 | 
0 | 
0 | 
| T109 | 
5918 | 
7 | 
0 | 
0 | 
| T125 | 
9566 | 
2 | 
0 | 
0 | 
| T129 | 
10434 | 
16 | 
0 | 
0 | 
| T131 | 
8823 | 
10 | 
0 | 
0 | 
| T134 | 
11738 | 
1 | 
0 | 
0 | 
| T159 | 
32310 | 
21 | 
0 | 
0 | 
| T160 | 
4528 | 
8 | 
0 | 
0 | 
| T161 | 
32740 | 
27 | 
0 | 
0 | 
| T163 | 
5767 | 
17 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
2284 | 
0 | 
0 | 
| T103 | 
8659 | 
30 | 
0 | 
0 | 
| T109 | 
5918 | 
24 | 
0 | 
0 | 
| T125 | 
9566 | 
32 | 
0 | 
0 | 
| T129 | 
10434 | 
63 | 
0 | 
0 | 
| T131 | 
8823 | 
20 | 
0 | 
0 | 
| T134 | 
11738 | 
32 | 
0 | 
0 | 
| T159 | 
32310 | 
47 | 
0 | 
0 | 
| T160 | 
4528 | 
22 | 
0 | 
0 | 
| T162 | 
3384 | 
2 | 
0 | 
0 | 
| T163 | 
5767 | 
15 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1463 | 
0 | 
0 | 
| T103 | 
8659 | 
8 | 
0 | 
0 | 
| T109 | 
5918 | 
12 | 
0 | 
0 | 
| T125 | 
9566 | 
12 | 
0 | 
0 | 
| T129 | 
10434 | 
25 | 
0 | 
0 | 
| T131 | 
8823 | 
11 | 
0 | 
0 | 
| T134 | 
11738 | 
7 | 
0 | 
0 | 
| T159 | 
32310 | 
20 | 
0 | 
0 | 
| T161 | 
32740 | 
68 | 
0 | 
0 | 
| T163 | 
5767 | 
16 | 
0 | 
0 | 
| T177 | 
10067 | 
5 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1301 | 
0 | 
0 | 
| T103 | 
8659 | 
11 | 
0 | 
0 | 
| T109 | 
5918 | 
5 | 
0 | 
0 | 
| T125 | 
9566 | 
7 | 
0 | 
0 | 
| T129 | 
10434 | 
14 | 
0 | 
0 | 
| T131 | 
8823 | 
11 | 
0 | 
0 | 
| T134 | 
11738 | 
13 | 
0 | 
0 | 
| T159 | 
32310 | 
46 | 
0 | 
0 | 
| T160 | 
4528 | 
3 | 
0 | 
0 | 
| T161 | 
32740 | 
40 | 
0 | 
0 | 
| T163 | 
5767 | 
6 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1300 | 
0 | 
0 | 
| T103 | 
8659 | 
8 | 
0 | 
0 | 
| T109 | 
5918 | 
5 | 
0 | 
0 | 
| T125 | 
9566 | 
18 | 
0 | 
0 | 
| T129 | 
10434 | 
6 | 
0 | 
0 | 
| T131 | 
8823 | 
6 | 
0 | 
0 | 
| T134 | 
11738 | 
17 | 
0 | 
0 | 
| T159 | 
32310 | 
17 | 
0 | 
0 | 
| T160 | 
4528 | 
6 | 
0 | 
0 | 
| T161 | 
32740 | 
50 | 
0 | 
0 | 
| T163 | 
5767 | 
14 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1401 | 
0 | 
0 | 
| T103 | 
8659 | 
5 | 
0 | 
0 | 
| T109 | 
5918 | 
7 | 
0 | 
0 | 
| T125 | 
9566 | 
7 | 
0 | 
0 | 
| T129 | 
10434 | 
18 | 
0 | 
0 | 
| T131 | 
8823 | 
16 | 
0 | 
0 | 
| T134 | 
11738 | 
19 | 
0 | 
0 | 
| T159 | 
32310 | 
26 | 
0 | 
0 | 
| T160 | 
4528 | 
1 | 
0 | 
0 | 
| T161 | 
32740 | 
34 | 
0 | 
0 | 
| T163 | 
5767 | 
12 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1431 | 
0 | 
0 | 
| T109 | 
5918 | 
2 | 
0 | 
0 | 
| T125 | 
9566 | 
3 | 
0 | 
0 | 
| T129 | 
10434 | 
8 | 
0 | 
0 | 
| T131 | 
8823 | 
8 | 
0 | 
0 | 
| T134 | 
11738 | 
11 | 
0 | 
0 | 
| T159 | 
32310 | 
23 | 
0 | 
0 | 
| T160 | 
4528 | 
1 | 
0 | 
0 | 
| T161 | 
32740 | 
36 | 
0 | 
0 | 
| T163 | 
5767 | 
17 | 
0 | 
0 | 
| T177 | 
10067 | 
11 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1283 | 
0 | 
0 | 
| T103 | 
8659 | 
2 | 
0 | 
0 | 
| T125 | 
9566 | 
10 | 
0 | 
0 | 
| T129 | 
10434 | 
5 | 
0 | 
0 | 
| T131 | 
8823 | 
1 | 
0 | 
0 | 
| T134 | 
11738 | 
8 | 
0 | 
0 | 
| T159 | 
32310 | 
27 | 
0 | 
0 | 
| T160 | 
4528 | 
4 | 
0 | 
0 | 
| T161 | 
32740 | 
25 | 
0 | 
0 | 
| T162 | 
3384 | 
6 | 
0 | 
0 | 
| T177 | 
10067 | 
15 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
498530043 | 
1377 | 
0 | 
0 | 
| T103 | 
8659 | 
7 | 
0 | 
0 | 
| T109 | 
5918 | 
14 | 
0 | 
0 | 
| T125 | 
9566 | 
12 | 
0 | 
0 | 
| T129 | 
10434 | 
12 | 
0 | 
0 | 
| T131 | 
8823 | 
2 | 
0 | 
0 | 
| T134 | 
11738 | 
24 | 
0 | 
0 | 
| T159 | 
32310 | 
13 | 
0 | 
0 | 
| T160 | 
4528 | 
7 | 
0 | 
0 | 
| T161 | 
32740 | 
48 | 
0 | 
0 | 
| T163 | 
5767 | 
20 | 
0 | 
0 |