Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3400463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4243071

1

T1

8

T2

1356

T3

10718

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4121545	1			T1	1		T2	889		T3	9407
values[0x0]	1760270	1			T1	5		T2	433		T3	5325
values[0x1]	1761719	1			T1	4		T2	481		T3	5367

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2419678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5223856

1

T1

9

T2

1456

T3

13539

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27722	1			T2	11		T3	87		T4	18
valid_sources[0x01]	29093	1			T2	3		T3	64		T4	5
valid_sources[0x02]	34032	1			T2	2		T3	84		T4	1
valid_sources[0x03]	36476	1			T2	7		T3	61		T4	1
valid_sources[0x04]	34956	1			T2	6		T3	77		T4	4
valid_sources[0x05]	29541	1			T2	6		T3	98		T4	1
valid_sources[0x06]	29466	1			T2	6		T3	71		T4	1
valid_sources[0x07]	28612	1			T2	7		T3	65		T4	12
valid_sources[0x08]	27840	1			T2	7		T3	80		T4	2
valid_sources[0x09]	30286	1			T2	7		T3	89		T5	55
valid_sources[0x0a]	28134	1			T2	9		T3	74		T4	5
valid_sources[0x0b]	39713	1			T2	7		T3	58		T5	486
valid_sources[0x0c]	29254	1			T2	10		T3	61		T5	231
valid_sources[0x0d]	31827	1			T2	13		T3	60		T4	3
valid_sources[0x0e]	26176	1			T2	5		T3	94		T5	73
valid_sources[0x0f]	28880	1			T2	5		T3	76		T5	255
valid_sources[0x10]	25493	1			T2	3		T3	69		T4	2
valid_sources[0x11]	26649	1			T2	5		T3	78		T4	3
valid_sources[0x12]	26250	1			T2	12		T3	74		T4	3
valid_sources[0x13]	28041	1			T2	4		T3	77		T4	4
valid_sources[0x14]	32300	1			T2	12		T3	68		T5	1292
valid_sources[0x15]	32883	1			T2	12		T3	88		T4	2
valid_sources[0x16]	28678	1			T2	8		T3	60		T4	16
valid_sources[0x17]	29745	1			T2	12		T3	67		T4	9
valid_sources[0x18]	31533	1			T2	5		T3	96		T4	3
valid_sources[0x19]	26548	1			T2	6		T3	68		T4	5
valid_sources[0x1a]	28398	1			T2	12		T3	75		T5	559
valid_sources[0x1b]	26961	1			T2	12		T3	71		T4	17
valid_sources[0x1c]	27197	1			T2	15		T3	84		T5	296
valid_sources[0x1d]	27134	1			T2	5		T3	92		T4	8
valid_sources[0x1e]	27019	1			T2	8		T3	94		T5	184
valid_sources[0x1f]	25917	1			T2	9		T3	94		T5	173
valid_sources[0x20]	34040	1			T2	9		T3	93		T4	2
valid_sources[0x21]	33467	1			T2	9		T3	79		T4	1
valid_sources[0x22]	30228	1			T2	4		T3	72		T4	1
valid_sources[0x23]	27058	1			T2	3		T3	93		T5	155
valid_sources[0x24]	31896	1			T2	7		T3	82		T4	7
valid_sources[0x25]	29030	1			T2	6		T3	46		T5	420
valid_sources[0x26]	29671	1			T2	9		T3	75		T5	70
valid_sources[0x27]	30632	1			T2	6		T3	70		T4	1
valid_sources[0x28]	33482	1			T2	7		T3	88		T4	1
valid_sources[0x29]	27021	1			T1	1		T2	9		T3	87
valid_sources[0x2a]	30707	1			T2	7		T3	73		T4	1
valid_sources[0x2b]	27805	1			T2	7		T3	89		T4	3
valid_sources[0x2c]	33214	1			T2	9		T3	89		T4	5
valid_sources[0x2d]	28449	1			T2	12		T3	66		T4	1
valid_sources[0x2e]	27431	1			T2	2		T3	69		T4	4
valid_sources[0x2f]	27595	1			T2	2		T3	75		T5	155
valid_sources[0x30]	27335	1			T2	4		T3	81		T4	13
valid_sources[0x31]	29886	1			T2	5		T3	77		T4	2
valid_sources[0x32]	38979	1			T2	4		T3	99		T4	8
valid_sources[0x33]	32055	1			T2	12		T3	75		T4	3
valid_sources[0x34]	29694	1			T2	9		T3	60		T4	1
valid_sources[0x35]	29016	1			T2	5		T3	71		T4	4
valid_sources[0x36]	29904	1			T2	7		T3	77		T4	5
valid_sources[0x37]	34928	1			T2	9		T3	58		T4	2
valid_sources[0x38]	29032	1			T2	5		T3	85		T4	6
valid_sources[0x39]	31611	1			T2	6		T3	88		T4	1
valid_sources[0x3a]	26523	1			T2	8		T3	73		T4	2
valid_sources[0x3b]	30761	1			T1	1		T2	4		T3	86
valid_sources[0x3c]	31533	1			T2	11		T3	96		T4	6
valid_sources[0x3d]	31218	1			T2	9		T3	71		T4	7
valid_sources[0x3e]	31180	1			T2	4		T3	72		T4	4
valid_sources[0x3f]	27300	1			T2	8		T3	74		T4	5
valid_sources[0x40]	32239	1			T2	9		T3	83		T4	3
valid_sources[0x41]	28712	1			T2	6		T3	78		T4	2
valid_sources[0x42]	27959	1			T2	4		T3	83		T5	290
valid_sources[0x43]	28490	1			T2	9		T3	57		T4	7
valid_sources[0x44]	29904	1			T2	6		T3	82		T4	4
valid_sources[0x45]	34123	1			T2	3		T3	78		T5	468
valid_sources[0x46]	27038	1			T2	5		T3	80		T4	7
valid_sources[0x47]	32392	1			T2	11		T3	95		T4	15
valid_sources[0x48]	32872	1			T2	5		T3	99		T4	9
valid_sources[0x49]	32728	1			T2	6		T3	77		T4	4
valid_sources[0x4a]	25203	1			T2	6		T3	93		T4	1
valid_sources[0x4b]	32002	1			T2	8		T3	108		T4	1
valid_sources[0x4c]	29852	1			T2	11		T3	89		T5	112
valid_sources[0x4d]	28969	1			T2	13		T3	84		T4	4
valid_sources[0x4e]	28717	1			T2	12		T3	89		T4	1
valid_sources[0x4f]	29584	1			T2	6		T3	89		T4	10
valid_sources[0x50]	29107	1			T2	7		T3	47		T4	3
valid_sources[0x51]	30732	1			T2	5		T3	95		T5	260
valid_sources[0x52]	29867	1			T2	7		T3	64		T5	1038
valid_sources[0x53]	26831	1			T2	4		T3	75		T4	4
valid_sources[0x54]	28183	1			T2	8		T3	93		T5	556
valid_sources[0x55]	28543	1			T2	5		T3	65		T4	2
valid_sources[0x56]	28031	1			T2	12		T3	69		T4	1
valid_sources[0x57]	27427	1			T2	7		T3	70		T4	4
valid_sources[0x58]	32437	1			T2	5		T3	84		T5	209
valid_sources[0x59]	28440	1			T2	7		T3	56		T4	1
valid_sources[0x5a]	42422	1			T2	4		T3	86		T4	1
valid_sources[0x5b]	31046	1			T2	7		T3	87		T4	5
valid_sources[0x5c]	29158	1			T2	7		T3	77		T4	3
valid_sources[0x5d]	30800	1			T2	13		T3	93		T4	2
valid_sources[0x5e]	29552	1			T2	3		T3	81		T4	9
valid_sources[0x5f]	30153	1			T2	6		T3	73		T4	2
valid_sources[0x60]	29580	1			T2	5		T3	87		T5	152
valid_sources[0x61]	30944	1			T2	4		T3	64		T4	2
valid_sources[0x62]	29519	1			T2	9		T3	67		T4	2
valid_sources[0x63]	28263	1			T3	76		T5	476		T7	6
valid_sources[0x64]	30183	1			T2	4		T3	66		T4	1
valid_sources[0x65]	34941	1			T2	5		T3	90		T4	4
valid_sources[0x66]	29430	1			T2	3		T3	103		T4	1
valid_sources[0x67]	30370	1			T2	3		T3	83		T4	3
valid_sources[0x68]	26865	1			T2	4		T3	83		T4	2
valid_sources[0x69]	28373	1			T2	8		T3	63		T5	193
valid_sources[0x6a]	29729	1			T1	1		T2	7		T3	69
valid_sources[0x6b]	28049	1			T2	8		T3	103		T4	2
valid_sources[0x6c]	27671	1			T2	12		T3	76		T5	514
valid_sources[0x6d]	28318	1			T2	4		T3	72		T4	5
valid_sources[0x6e]	27328	1			T1	1		T2	10		T3	70
valid_sources[0x6f]	31367	1			T1	1		T2	4		T3	76
valid_sources[0x70]	28274	1			T2	3		T3	82		T5	464
valid_sources[0x71]	29065	1			T2	5		T3	62		T5	89
valid_sources[0x72]	29518	1			T2	7		T3	92		T4	7
valid_sources[0x73]	32341	1			T2	8		T3	75		T5	324
valid_sources[0x74]	31652	1			T2	8		T3	81		T5	424
valid_sources[0x75]	28090	1			T2	12		T3	83		T4	2
valid_sources[0x76]	29770	1			T2	3		T3	93		T4	7
valid_sources[0x77]	30457	1			T2	5		T3	75		T4	9
valid_sources[0x78]	26686	1			T2	6		T3	96		T4	3
valid_sources[0x79]	62601	1			T2	2		T3	70		T4	4
valid_sources[0x7a]	33235	1			T2	6		T3	91		T4	1
valid_sources[0x7b]	28846	1			T2	8		T3	71		T5	594
valid_sources[0x7c]	28180	1			T2	2		T3	70		T4	1
valid_sources[0x7d]	32168	1			T2	9		T3	77		T5	537
valid_sources[0x7e]	31423	1			T2	14		T3	81		T4	1
valid_sources[0x7f]	30547	1			T1	1		T2	1		T3	97
valid_sources[0x80]	28205	1			T2	6		T3	103		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1042342

1

T1

1

T2

450

T3

1326

values[0x0]

all_enables

biggest_size

1612328

1

T1

4

T2

431

T3

4734

values[0x1]

all_enables

biggest_size

1588401

1

T1

3

T2

475

T3

4658