Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3422501

1

T1

2

T2

447

T3

9381

full_word

4242225

1

T1

8

T2

1356

T3

10718

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7664316	1			T1	10		T2	1803		T3	20099
auto[TlIntgErrCmd]	148	1			T104	6		T106	10		T108	8
auto[TlIntgErrData]	127	1			T104	5		T106	10		T108	5
auto[TlIntgErrBoth]	135	1			T104	9		T106	10		T108	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4124503

1

T1

1

T2

889

T3

9407

auto[1]

3540223

1

T1

9

T2

914

T3

10692

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3081796	1			T2	439		T3	8081		T4	4
auto[TlIntgErrNone]	partial	auto[1]	340328	1			T1	2		T2	8		T3	1300
auto[TlIntgErrNone]	full_word	auto[0]	1042505	1			T1	1		T2	450		T3	1326
auto[TlIntgErrNone]	full_word	auto[1]	3199687	1			T1	7		T2	906		T3	9392
auto[TlIntgErrCmd]	partial	auto[0]	66	1			T104	1		T106	5		T108	4
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T104	3		T106	4		T108	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T106	1		T166	1		T169	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T104	2		T170	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T104	3		T106	6		T108	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T104	2		T106	4		T108	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T170	1		T169	1		T172	4
auto[TlIntgErrData]	full_word	auto[1]	3	1			T158	1		T172	1		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T104	4		T106	3		T108	5
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T104	5		T106	7		T108	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T174	1		T175	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T168	1		T166	3		T169	1