Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	736859303	585529696	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	736859303	3820233	0	0
GntImpliesValid_A	736859303	3820233	0	0
GrantKnown_A	736859303	585529696	0	0
IdxKnown_A	736859303	585529696	0	0
IndexIsCorrect_A	736859303	3820233	0	0
LockArbDecision_A	736859303	0	0	0
NoReadyValidNoGrant_A	736859303	0	0	0
ReadyAndValidImplyGrant_A	736859303	3820233	0	0
ReqAndReadyImplyGrant_A	736859303	3820233	0	0
ReqImpliesValid_A	736859303	3820233	0	0
ReqStaysHighUntilGranted0_M	736859303	0	0	0
RoundRobin_A	736859303	6	0	975
ValidKnown_A	736859303	585529696	0	0
gen_data_port_assertion.DataFlow_A	736859303	3820233	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	585529696	0	0
T1	1291	1216	0	0
T2	45852	45544	0	0
T3	1369311	1032829	0	0
T4	33461	22967	0	0
T5	2233736	1333842	0	0
T6	1071	993	0	0
T7	399630	295733	0	0
T8	4314	3479	0	0
T9	1119741	653032	0	0
T10	428272	273044	0	0
T11	254552	127270	0	0
T12	148222	74080	0	0
T13	422200	420152	0	0
T14	0	50592	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	3820233	0	0
T2	24832	832	0	0
T3	1369311	11008	0	0
T4	33461	832	0	0
T5	2233736	22138	0	0
T6	1071	0	0	0
T7	399630	0	0	0
T8	4314	0	0	0
T9	1119741	8999	0	0
T10	428272	4178	0	0
T11	385674	832	0	0
T12	148222	832	0	0
T13	844400	9927	0	0
T14	0	832	0	0
T15	0	9265	0	0
T29	0	6834	0	0
T33	0	4847	0	0
T36	0	4362	0	0
T44	0	2874	0	0
T45	0	209	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	3820233	0	0
T2	24832	832	0	0
T3	1369311	11008	0	0
T4	33461	832	0	0
T5	2233736	22138	0	0
T6	1071	0	0	0
T7	399630	0	0	0
T8	4314	0	0	0
T9	1119741	8999	0	0
T10	428272	4178	0	0
T11	385674	832	0	0
T12	148222	832	0	0
T13	844400	9927	0	0
T14	0	832	0	0
T15	0	9265	0	0
T29	0	6834	0	0
T33	0	4847	0	0
T36	0	4362	0	0
T44	0	2874	0	0
T45	0	209	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	585529696	0	0
T1	1291	1216	0	0
T2	45852	45544	0	0
T3	1369311	1032829	0	0
T4	33461	22967	0	0
T5	2233736	1333842	0	0
T6	1071	993	0	0
T7	399630	295733	0	0
T8	4314	3479	0	0
T9	1119741	653032	0	0
T10	428272	273044	0	0
T11	254552	127270	0	0
T12	148222	74080	0	0
T13	422200	420152	0	0
T14	0	50592	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	585529696	0	0
T1	1291	1216	0	0
T2	45852	45544	0	0
T3	1369311	1032829	0	0
T4	33461	22967	0	0
T5	2233736	1333842	0	0
T6	1071	993	0	0
T7	399630	295733	0	0
T8	4314	3479	0	0
T9	1119741	653032	0	0
T10	428272	273044	0	0
T11	254552	127270	0	0
T12	148222	74080	0	0
T13	422200	420152	0	0
T14	0	50592	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	3820233	0	0
T2	24832	832	0	0
T3	1369311	11008	0	0
T4	33461	832	0	0
T5	2233736	22138	0	0
T6	1071	0	0	0
T7	399630	0	0	0
T8	4314	0	0	0
T9	1119741	8999	0	0
T10	428272	4178	0	0
T11	385674	832	0	0
T12	148222	832	0	0
T13	844400	9927	0	0
T14	0	832	0	0
T15	0	9265	0	0
T29	0	6834	0	0
T33	0	4847	0	0
T36	0	4362	0	0
T44	0	2874	0	0
T45	0	209	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	3820233	0	0
T2	24832	832	0	0
T3	1369311	11008	0	0
T4	33461	832	0	0
T5	2233736	22138	0	0
T6	1071	0	0	0
T7	399630	0	0	0
T8	4314	0	0	0
T9	1119741	8999	0	0
T10	428272	4178	0	0
T11	385674	832	0	0
T12	148222	832	0	0
T13	844400	9927	0	0
T14	0	832	0	0
T15	0	9265	0	0
T29	0	6834	0	0
T33	0	4847	0	0
T36	0	4362	0	0
T44	0	2874	0	0
T45	0	209	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	3820233	0	0
T2	24832	832	0	0
T3	1369311	11008	0	0
T4	33461	832	0	0
T5	2233736	22138	0	0
T6	1071	0	0	0
T7	399630	0	0	0
T8	4314	0	0	0
T9	1119741	8999	0	0
T10	428272	4178	0	0
T11	385674	832	0	0
T12	148222	832	0	0
T13	844400	9927	0	0
T14	0	832	0	0
T15	0	9265	0	0
T29	0	6834	0	0
T33	0	4847	0	0
T36	0	4362	0	0
T44	0	2874	0	0
T45	0	209	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	3820233	0	0
T2	24832	832	0	0
T3	1369311	11008	0	0
T4	33461	832	0	0
T5	2233736	22138	0	0
T6	1071	0	0	0
T7	399630	0	0	0
T8	4314	0	0	0
T9	1119741	8999	0	0
T10	428272	4178	0	0
T11	385674	832	0	0
T12	148222	832	0	0
T13	844400	9927	0	0
T14	0	832	0	0
T15	0	9265	0	0
T29	0	6834	0	0
T33	0	4847	0	0
T36	0	4362	0	0
T44	0	2874	0	0
T45	0	209	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	6	0	975
T35	614802	1	0	1
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	240302	0	0	1
T62	22392	0	0	1
T63	100091	0	0	1
T64	423237	0	0	1
T65	117487	0	0	1
T66	46624	0	0	1
T67	42490	0	0	1
T68	2987	0	0	1
T69	167623	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	585529696	0	0
T1	1291	1216	0	0
T2	45852	45544	0	0
T3	1369311	1032829	0	0
T4	33461	22967	0	0
T5	2233736	1333842	0	0
T6	1071	993	0	0
T7	399630	295733	0	0
T8	4314	3479	0	0
T9	1119741	653032	0	0
T10	428272	273044	0	0
T11	254552	127270	0	0
T12	148222	74080	0	0
T13	422200	420152	0	0
T14	0	50592	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	736859303	3820233	0	0
T2	24832	832	0	0
T3	1369311	11008	0	0
T4	33461	832	0	0
T5	2233736	22138	0	0
T6	1071	0	0	0
T7	399630	0	0	0
T8	4314	0	0	0
T9	1119741	8999	0	0
T10	428272	4178	0	0
T11	385674	832	0	0
T12	148222	832	0	0
T13	844400	9927	0	0
T14	0	832	0	0
T15	0	9265	0	0
T29	0	6834	0	0
T33	0	4847	0	0
T36	0	4362	0	0
T44	0	2874	0	0
T45	0	209	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T9
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149824627	29721568	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	149824627	638703	0	0
GntImpliesValid_A	149824627	638703	0	0
GrantKnown_A	149824627	29721568	0	0
IdxKnown_A	149824627	29721568	0	0
IndexIsCorrect_A	149824627	638703	0	0
LockArbDecision_A	149824627	0	0	0
NoReadyValidNoGrant_A	149824627	0	0	0
ReadyAndValidImplyGrant_A	149824627	638703	0	0
ReqAndReadyImplyGrant_A	149824627	638703	0	0
ReqImpliesValid_A	149824627	638703	0	0
ReqStaysHighUntilGranted0_M	149824627	0	0	0
RoundRobin_A	149824627	0	0	0
ValidKnown_A	149824627	29721568	0	0
gen_data_port_assertion.DataFlow_A	149824627	638703	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	29721568	0	0
T3	331713	99984	0	0
T4	10400	0	0	0
T5	893792	122608	0	0
T7	99063	94312	0	0
T8	729	720	0	0
T9	465465	11000	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	302664	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	638703	0	0
T3	331713	3609	0	0
T4	10400	0	0	0
T5	893792	5126	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	399	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	3907	0	0
T15	0	4036	0	0
T29	0	4399	0	0
T33	0	4819	0	0
T36	0	3179	0	0
T44	0	266	0	0
T45	0	209	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	638703	0	0
T3	331713	3609	0	0
T4	10400	0	0	0
T5	893792	5126	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	399	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	3907	0	0
T15	0	4036	0	0
T29	0	4399	0	0
T33	0	4819	0	0
T36	0	3179	0	0
T44	0	266	0	0
T45	0	209	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	29721568	0	0
T3	331713	99984	0	0
T4	10400	0	0	0
T5	893792	122608	0	0
T7	99063	94312	0	0
T8	729	720	0	0
T9	465465	11000	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	302664	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	29721568	0	0
T3	331713	99984	0	0
T4	10400	0	0	0
T5	893792	122608	0	0
T7	99063	94312	0	0
T8	729	720	0	0
T9	465465	11000	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	302664	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	638703	0	0
T3	331713	3609	0	0
T4	10400	0	0	0
T5	893792	5126	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	399	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	3907	0	0
T15	0	4036	0	0
T29	0	4399	0	0
T33	0	4819	0	0
T36	0	3179	0	0
T44	0	266	0	0
T45	0	209	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	638703	0	0
T3	331713	3609	0	0
T4	10400	0	0	0
T5	893792	5126	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	399	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	3907	0	0
T15	0	4036	0	0
T29	0	4399	0	0
T33	0	4819	0	0
T36	0	3179	0	0
T44	0	266	0	0
T45	0	209	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	638703	0	0
T3	331713	3609	0	0
T4	10400	0	0	0
T5	893792	5126	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	399	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	3907	0	0
T15	0	4036	0	0
T29	0	4399	0	0
T33	0	4819	0	0
T36	0	3179	0	0
T44	0	266	0	0
T45	0	209	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	638703	0	0
T3	331713	3609	0	0
T4	10400	0	0	0
T5	893792	5126	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	399	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	3907	0	0
T15	0	4036	0	0
T29	0	4399	0	0
T33	0	4819	0	0
T36	0	3179	0	0
T44	0	266	0	0
T45	0	209	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	29721568	0	0
T3	331713	99984	0	0
T4	10400	0	0	0
T5	893792	122608	0	0
T7	99063	94312	0	0
T8	729	720	0	0
T9	465465	11000	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	302664	0	0
T31	0	112440	0	0
T32	0	100712	0	0
T33	0	112504	0	0
T34	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	638703	0	0
T3	331713	3609	0	0
T4	10400	0	0	0
T5	893792	5126	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	399	0	0
T10	152757	0	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	3907	0	0
T15	0	4036	0	0
T29	0	4399	0	0
T33	0	4819	0	0
T36	0	3179	0	0
T44	0	266	0	0
T45	0	209	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T3,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T9
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149824627	118687432	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	149824627	858145	0	0
GntImpliesValid_A	149824627	858145	0	0
GrantKnown_A	149824627	118687432	0	0
IdxKnown_A	149824627	118687432	0	0
IndexIsCorrect_A	149824627	858145	0	0
LockArbDecision_A	149824627	0	0	0
NoReadyValidNoGrant_A	149824627	0	0	0
ReadyAndValidImplyGrant_A	149824627	858145	0	0
ReqAndReadyImplyGrant_A	149824627	858145	0	0
ReqImpliesValid_A	149824627	858145	0	0
ReqStaysHighUntilGranted0_M	149824627	0	0	0
RoundRobin_A	149824627	0	0	0
ValidKnown_A	149824627	118687432	0	0
gen_data_port_assertion.DataFlow_A	149824627	858145	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	118687432	0	0
T2	21020	20784	0	0
T3	331713	227021	0	0
T4	10400	10400	0	0
T5	893792	765088	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	453230	0	0
T10	152757	150293	0	0
T11	127276	127270	0	0
T12	74111	74080	0	0
T13	0	117488	0	0
T14	0	50592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	858145	0	0
T3	331713	548	0	0
T4	10400	0	0	0
T5	893792	6069	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	3185	0	0
T10	152757	10	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	650	0	0
T15	0	5229	0	0
T29	0	2435	0	0
T33	0	28	0	0
T36	0	1183	0	0
T44	0	2608	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	858145	0	0
T3	331713	548	0	0
T4	10400	0	0	0
T5	893792	6069	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	3185	0	0
T10	152757	10	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	650	0	0
T15	0	5229	0	0
T29	0	2435	0	0
T33	0	28	0	0
T36	0	1183	0	0
T44	0	2608	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	118687432	0	0
T2	21020	20784	0	0
T3	331713	227021	0	0
T4	10400	10400	0	0
T5	893792	765088	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	453230	0	0
T10	152757	150293	0	0
T11	127276	127270	0	0
T12	74111	74080	0	0
T13	0	117488	0	0
T14	0	50592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	118687432	0	0
T2	21020	20784	0	0
T3	331713	227021	0	0
T4	10400	10400	0	0
T5	893792	765088	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	453230	0	0
T10	152757	150293	0	0
T11	127276	127270	0	0
T12	74111	74080	0	0
T13	0	117488	0	0
T14	0	50592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	858145	0	0
T3	331713	548	0	0
T4	10400	0	0	0
T5	893792	6069	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	3185	0	0
T10	152757	10	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	650	0	0
T15	0	5229	0	0
T29	0	2435	0	0
T33	0	28	0	0
T36	0	1183	0	0
T44	0	2608	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	858145	0	0
T3	331713	548	0	0
T4	10400	0	0	0
T5	893792	6069	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	3185	0	0
T10	152757	10	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	650	0	0
T15	0	5229	0	0
T29	0	2435	0	0
T33	0	28	0	0
T36	0	1183	0	0
T44	0	2608	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	858145	0	0
T3	331713	548	0	0
T4	10400	0	0	0
T5	893792	6069	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	3185	0	0
T10	152757	10	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	650	0	0
T15	0	5229	0	0
T29	0	2435	0	0
T33	0	28	0	0
T36	0	1183	0	0
T44	0	2608	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	858145	0	0
T3	331713	548	0	0
T4	10400	0	0	0
T5	893792	6069	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	3185	0	0
T10	152757	10	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	650	0	0
T15	0	5229	0	0
T29	0	2435	0	0
T33	0	28	0	0
T36	0	1183	0	0
T44	0	2608	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	118687432	0	0
T2	21020	20784	0	0
T3	331713	227021	0	0
T4	10400	10400	0	0
T5	893792	765088	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	453230	0	0
T10	152757	150293	0	0
T11	127276	127270	0	0
T12	74111	74080	0	0
T13	0	117488	0	0
T14	0	50592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	858145	0	0
T3	331713	548	0	0
T4	10400	0	0	0
T5	893792	6069	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	3185	0	0
T10	152757	10	0	0
T11	127276	0	0	0
T12	74111	0	0	0
T13	422200	650	0	0
T15	0	5229	0	0
T29	0	2435	0	0
T33	0	28	0	0
T36	0	1183	0	0
T44	0	2608	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T9
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	437210049	437120696	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	437210049	2323385	0	0
GntImpliesValid_A	437210049	2323385	0	0
GrantKnown_A	437210049	437120696	0	0
IdxKnown_A	437210049	437120696	0	0
IndexIsCorrect_A	437210049	2323385	0	0
LockArbDecision_A	437210049	0	0	0
NoReadyValidNoGrant_A	437210049	0	0	0
ReadyAndValidImplyGrant_A	437210049	2323385	0	0
ReqAndReadyImplyGrant_A	437210049	2323385	0	0
ReqImpliesValid_A	437210049	2323385	0	0
ReqStaysHighUntilGranted0_M	437210049	0	0	0
RoundRobin_A	437210049	6	0	975
ValidKnown_A	437210049	437120696	0	0
gen_data_port_assertion.DataFlow_A	437210049	2323385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	437120696	0	0
T1	1291	1216	0	0
T2	24832	24760	0	0
T3	705885	705824	0	0
T4	12661	12567	0	0
T5	446152	446146	0	0
T6	1071	993	0	0
T7	201504	201421	0	0
T8	2856	2759	0	0
T9	188811	188802	0	0
T10	122758	122751	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	2323385	0	0
T2	24832	832	0	0
T3	705885	6851	0	0
T4	12661	832	0	0
T5	446152	10943	0	0
T6	1071	0	0	0
T7	201504	0	0	0
T8	2856	0	0	0
T9	188811	5415	0	0
T10	122758	4168	0	0
T11	131122	832	0	0
T12	0	832	0	0
T13	0	5370	0	0
T14	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	2323385	0	0
T2	24832	832	0	0
T3	705885	6851	0	0
T4	12661	832	0	0
T5	446152	10943	0	0
T6	1071	0	0	0
T7	201504	0	0	0
T8	2856	0	0	0
T9	188811	5415	0	0
T10	122758	4168	0	0
T11	131122	832	0	0
T12	0	832	0	0
T13	0	5370	0	0
T14	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	437120696	0	0
T1	1291	1216	0	0
T2	24832	24760	0	0
T3	705885	705824	0	0
T4	12661	12567	0	0
T5	446152	446146	0	0
T6	1071	993	0	0
T7	201504	201421	0	0
T8	2856	2759	0	0
T9	188811	188802	0	0
T10	122758	122751	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	437120696	0	0
T1	1291	1216	0	0
T2	24832	24760	0	0
T3	705885	705824	0	0
T4	12661	12567	0	0
T5	446152	446146	0	0
T6	1071	993	0	0
T7	201504	201421	0	0
T8	2856	2759	0	0
T9	188811	188802	0	0
T10	122758	122751	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	2323385	0	0
T2	24832	832	0	0
T3	705885	6851	0	0
T4	12661	832	0	0
T5	446152	10943	0	0
T6	1071	0	0	0
T7	201504	0	0	0
T8	2856	0	0	0
T9	188811	5415	0	0
T10	122758	4168	0	0
T11	131122	832	0	0
T12	0	832	0	0
T13	0	5370	0	0
T14	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	2323385	0	0
T2	24832	832	0	0
T3	705885	6851	0	0
T4	12661	832	0	0
T5	446152	10943	0	0
T6	1071	0	0	0
T7	201504	0	0	0
T8	2856	0	0	0
T9	188811	5415	0	0
T10	122758	4168	0	0
T11	131122	832	0	0
T12	0	832	0	0
T13	0	5370	0	0
T14	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	2323385	0	0
T2	24832	832	0	0
T3	705885	6851	0	0
T4	12661	832	0	0
T5	446152	10943	0	0
T6	1071	0	0	0
T7	201504	0	0	0
T8	2856	0	0	0
T9	188811	5415	0	0
T10	122758	4168	0	0
T11	131122	832	0	0
T12	0	832	0	0
T13	0	5370	0	0
T14	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	2323385	0	0
T2	24832	832	0	0
T3	705885	6851	0	0
T4	12661	832	0	0
T5	446152	10943	0	0
T6	1071	0	0	0
T7	201504	0	0	0
T8	2856	0	0	0
T9	188811	5415	0	0
T10	122758	4168	0	0
T11	131122	832	0	0
T12	0	832	0	0
T13	0	5370	0	0
T14	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	6	0	975
T35	614802	1	0	1
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	240302	0	0	1
T62	22392	0	0	1
T63	100091	0	0	1
T64	423237	0	0	1
T65	117487	0	0	1
T66	46624	0	0	1
T67	42490	0	0	1
T68	2987	0	0	1
T69	167623	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	437120696	0	0
T1	1291	1216	0	0
T2	24832	24760	0	0
T3	705885	705824	0	0
T4	12661	12567	0	0
T5	446152	446146	0	0
T6	1071	993	0	0
T7	201504	201421	0	0
T8	2856	2759	0	0
T9	188811	188802	0	0
T10	122758	122751	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437210049	2323385	0	0
T2	24832	832	0	0
T3	705885	6851	0	0
T4	12661	832	0	0
T5	446152	10943	0	0
T6	1071	0	0	0
T7	201504	0	0	0
T8	2856	0	0	0
T9	188811	5415	0	0
T10	122758	4168	0	0
T11	131122	832	0	0
T12	0	832	0	0
T13	0	5370	0	0
T14	0	832	0	0