Unified Coverage Report :: Module :: spid_readbuffer

Module : spid_readbuffer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.97	87.76	97.14			75.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_readcmd.u_readbuffer	89.97	87.76	97.14			75.00	100.00

---

Module Instance : tb.dut.u_readcmd.u_readbuffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.97	87.76	97.14			75.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.17	83.51	82.93			72.92	33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.19	96.32	100.00		80.00	84.62	100.00	u_readcmd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sys2spi_clr	37.29	79.17	0.00			70.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_readbuffer

	Line No.	Total	Covered	Percent
TOTAL		49	43	87.76
ALWAYS	105	6	4	66.67
ALWAYS	130	6	5	83.33
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
ALWAYS	147	6	5	83.33
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	163	8	7	87.50
ALWAYS	177	6	5	83.33
ALWAYS	196	5	5	100.00
ALWAYS	205	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
108	0	1
109	1	1
110	0	1
			MISSING_ELSE
130	1	1
131	1	1
132	1	1
133	0	1
134	1	1
135	1	1
			MISSING_ELSE
140	1	1
141	1	1
147	1	1
148	1	1
149	1	1
150	0	1
151	1	1
152	1	1
			MISSING_ELSE
156	1	1
159	1	1
163	1	1
164	1	1
165	1	1
166	0	1
167	1	1
170	1	1
171	1	1
172	1	1
			MISSING_ELSE
177	1	1
179	1	1
180	1	1
181	1	1
182	1	1
187	0	1
			MISSING_ELSE
			MISSING_ELSE
196	2	2
197	1	1
198	1	1
200	1	1
205	1	1
207	1	1
209	1	1
211	1	1
213	1	1
215	1	1
			MISSING_ELSE
221	1	1
223	1	1

---

Cond Coverage for Module : spid_readbuffer

	Total	Covered	Percent
Conditions	35	34	97.14
Logical	35	34	97.14
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (active && flip)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T9,T36,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T50,T51

 LINE       141
 EXPRESSION (current_buffer_idx == next_buffer_addr)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T47,T36

 LINE       156
 EXPRESSION (active && flip && ((!flip_q)))
             ---1--    --2-    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T36,T46
1	0	1	Covered	T47,T48,T49
1	1	0	Not Covered
1	1	1	Covered	T47,T50,T51

 LINE       159
 EXPRESSION ((current_address_i[(spi_device_pkg::SramBufferAw - 1):0] >= threshold_i) && ((|threshold_i)))
             ------------------------------------1-----------------------------------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T9

 LINE       167
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T9
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T48,T50

 LINE       171
 EXPRESSION (active && flip)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T9,T36,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T50,T51

 LINE       179
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T9
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T48,T50

 LINE       197
 EXPRESSION (spi_mode_i != FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T2,T4,T5

 LINE       211
 EXPRESSION (start_i && (spi_mode_i == FlashMode) && ((!sfdp_hit_i)) && ( ! (mailbox_en_i && mailbox_hit_i) ))
             ---1---    ------------2------------    -------3-------    ------------------4------------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T5,T9,T11
1	1	0	1	Covered	T3,T10,T13
1	1	1	0	Covered	T3,T10,T13
1	1	1	1	Covered	T47,T48,T49

 LINE       211
 SUB-EXPRESSION (spi_mode_i == FlashMode)
                ------------1------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION ( ! (mailbox_en_i && mailbox_hit_i) )
                    ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T9

 LINE       211
 SUB-EXPRESSION (mailbox_en_i && mailbox_hit_i)
                 ------1-----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T5,T9

---

Branch Coverage for Module : spid_readbuffer

	Line No.	Total	Covered	Percent
Branches		28	21	75.00
IF	105	4	2	50.00
IF	130	4	3	75.00
IF	147	4	3	75.00
IF	163	5	4	80.00
IF	179	4	3	75.00
IF	196	3	3	100.00
CASE	209	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	105	if ((!sys_rst_ni))
-2-:	107	if (sys_clr_i)
-3-:	109	if (sys_clr_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!sys_rst_ni))
-2-:	132	if (spi_clr)
-3-:	134	if ((active && flip))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T47,T50,T51
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	147	if ((!sys_rst_ni))
-2-:	149	if (spi_clr)
-3-:	151	if (active)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T47,T48,T49
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	163	if ((!sys_rst_ni))
-2-:	165	if (spi_clr)
-3-:	167	if ((active && watermark_cross))
-4-:	171	if ((active && flip))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T47,T48,T50
0	0	0	1	Covered	T47,T50,T51
0	0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	179	if ((active && watermark_cross))
-2-:	180	if ((!watermark_crossed))
-3-:	182	if (flip)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T47,T48,T50
1	0	1	Not Covered
1	0	0	Covered	T47,T50,T51
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))
-2-:	197	if ((spi_mode_i != FlashMode))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T3,T10,T13

	LineNo.	Expression
-1-:	209	case (st_q)
-2-:	211	if ((((start_i && (spi_mode_i == FlashMode)) && (!sfdp_hit_i)) && (!(mailbox_en_i && mailbox_hit_i))))

Branches:

-1-	-2-	Status	Tests
StIdle	1	Covered	T47,T48,T49
StIdle	0	Covered	T1,T2,T3
StActive	-	Covered	T47,T48,T49
default	-	Not Covered

---

Assert Coverage for Module : spid_readbuffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StartWithAddressUpdate_A	149824627	7715	0	0

StartWithAddressUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149824627	7715	0	0
T3	331713	13	0	0
T4	10400	0	0	0
T5	893792	49	0	0
T7	99063	0	0	0
T8	729	0	0	0
T9	465465	28	0	0
T10	152757	9	0	0
T11	127276	16	0	0
T12	74111	0	0	0
T13	422200	9	0	0
T15	0	22	0	0
T29	0	26	0	0
T33	0	12	0	0
T47	0	8	0	0