Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
3421 | 
0 | 
0 | 
| T102 | 
2634 | 
8 | 
0 | 
0 | 
| T103 | 
9747 | 
4 | 
0 | 
0 | 
| T104 | 
55323 | 
5 | 
0 | 
0 | 
| T105 | 
14727 | 
126 | 
0 | 
0 | 
| T106 | 
91319 | 
3 | 
0 | 
0 | 
| T107 | 
12439 | 
156 | 
0 | 
0 | 
| T108 | 
53670 | 
5 | 
0 | 
0 | 
| T109 | 
13191 | 
10 | 
0 | 
0 | 
| T113 | 
20364 | 
231 | 
0 | 
0 | 
| T118 | 
5383 | 
1 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4154 | 
0 | 
0 | 
| T103 | 
9747 | 
14 | 
0 | 
0 | 
| T106 | 
91319 | 
59 | 
0 | 
0 | 
| T118 | 
5383 | 
1 | 
0 | 
0 | 
| T122 | 
269812 | 
635 | 
0 | 
0 | 
| T123 | 
180326 | 
429 | 
0 | 
0 | 
| T153 | 
14063 | 
75 | 
0 | 
0 | 
| T154 | 
13262 | 
44 | 
0 | 
0 | 
| T155 | 
14655 | 
22 | 
0 | 
0 | 
| T156 | 
106514 | 
98 | 
0 | 
0 | 
| T157 | 
13350 | 
45 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4340 | 
0 | 
0 | 
| T103 | 
9747 | 
18 | 
0 | 
0 | 
| T106 | 
91319 | 
60 | 
0 | 
0 | 
| T118 | 
5383 | 
13 | 
0 | 
0 | 
| T122 | 
269812 | 
691 | 
0 | 
0 | 
| T123 | 
180326 | 
431 | 
0 | 
0 | 
| T153 | 
14063 | 
13 | 
0 | 
0 | 
| T154 | 
13262 | 
60 | 
0 | 
0 | 
| T155 | 
14655 | 
26 | 
0 | 
0 | 
| T156 | 
106514 | 
133 | 
0 | 
0 | 
| T157 | 
13350 | 
32 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4808 | 
0 | 
0 | 
| T103 | 
9747 | 
23 | 
0 | 
0 | 
| T106 | 
91319 | 
164 | 
0 | 
0 | 
| T118 | 
5383 | 
16 | 
0 | 
0 | 
| T122 | 
269812 | 
643 | 
0 | 
0 | 
| T123 | 
180326 | 
501 | 
0 | 
0 | 
| T153 | 
14063 | 
42 | 
0 | 
0 | 
| T154 | 
13262 | 
83 | 
0 | 
0 | 
| T155 | 
14655 | 
11 | 
0 | 
0 | 
| T156 | 
106514 | 
211 | 
0 | 
0 | 
| T157 | 
13350 | 
76 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
12513 | 
0 | 
0 | 
| T103 | 
9747 | 
151 | 
0 | 
0 | 
| T106 | 
91319 | 
980 | 
0 | 
0 | 
| T118 | 
5383 | 
6 | 
0 | 
0 | 
| T122 | 
269812 | 
603 | 
0 | 
0 | 
| T123 | 
180326 | 
446 | 
0 | 
0 | 
| T153 | 
14063 | 
46 | 
0 | 
0 | 
| T154 | 
13262 | 
42 | 
0 | 
0 | 
| T155 | 
14655 | 
171 | 
0 | 
0 | 
| T156 | 
106514 | 
2304 | 
0 | 
0 | 
| T157 | 
13350 | 
59 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
11919 | 
0 | 
0 | 
| T103 | 
9747 | 
219 | 
0 | 
0 | 
| T106 | 
91319 | 
1110 | 
0 | 
0 | 
| T118 | 
5383 | 
73 | 
0 | 
0 | 
| T122 | 
269812 | 
597 | 
0 | 
0 | 
| T123 | 
180326 | 
471 | 
0 | 
0 | 
| T153 | 
14063 | 
17 | 
0 | 
0 | 
| T154 | 
13262 | 
42 | 
0 | 
0 | 
| T155 | 
14655 | 
89 | 
0 | 
0 | 
| T156 | 
106514 | 
1637 | 
0 | 
0 | 
| T157 | 
13350 | 
51 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
11248 | 
0 | 
0 | 
| T103 | 
9747 | 
111 | 
0 | 
0 | 
| T106 | 
91319 | 
1353 | 
0 | 
0 | 
| T122 | 
269812 | 
738 | 
0 | 
0 | 
| T123 | 
180326 | 
425 | 
0 | 
0 | 
| T153 | 
14063 | 
79 | 
0 | 
0 | 
| T154 | 
13262 | 
39 | 
0 | 
0 | 
| T155 | 
14655 | 
18 | 
0 | 
0 | 
| T156 | 
106514 | 
1434 | 
0 | 
0 | 
| T157 | 
13350 | 
52 | 
0 | 
0 | 
| T158 | 
102384 | 
2087 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
11326 | 
0 | 
0 | 
| T103 | 
9747 | 
249 | 
0 | 
0 | 
| T106 | 
91319 | 
1157 | 
0 | 
0 | 
| T118 | 
5383 | 
3 | 
0 | 
0 | 
| T122 | 
269812 | 
657 | 
0 | 
0 | 
| T123 | 
180326 | 
456 | 
0 | 
0 | 
| T153 | 
14063 | 
34 | 
0 | 
0 | 
| T154 | 
13262 | 
42 | 
0 | 
0 | 
| T155 | 
14655 | 
110 | 
0 | 
0 | 
| T156 | 
106514 | 
2191 | 
0 | 
0 | 
| T157 | 
13350 | 
27 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
11933 | 
0 | 
0 | 
| T103 | 
9747 | 
253 | 
0 | 
0 | 
| T106 | 
91319 | 
946 | 
0 | 
0 | 
| T118 | 
5383 | 
52 | 
0 | 
0 | 
| T122 | 
269812 | 
679 | 
0 | 
0 | 
| T123 | 
180326 | 
394 | 
0 | 
0 | 
| T153 | 
14063 | 
58 | 
0 | 
0 | 
| T154 | 
13262 | 
36 | 
0 | 
0 | 
| T155 | 
14655 | 
165 | 
0 | 
0 | 
| T156 | 
106514 | 
2239 | 
0 | 
0 | 
| T157 | 
13350 | 
33 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
11108 | 
0 | 
0 | 
| T103 | 
9747 | 
23 | 
0 | 
0 | 
| T106 | 
91319 | 
1047 | 
0 | 
0 | 
| T118 | 
5383 | 
104 | 
0 | 
0 | 
| T122 | 
269812 | 
614 | 
0 | 
0 | 
| T123 | 
180326 | 
383 | 
0 | 
0 | 
| T153 | 
14063 | 
19 | 
0 | 
0 | 
| T154 | 
13262 | 
48 | 
0 | 
0 | 
| T155 | 
14655 | 
235 | 
0 | 
0 | 
| T156 | 
106514 | 
2008 | 
0 | 
0 | 
| T157 | 
13350 | 
43 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
11938 | 
0 | 
0 | 
| T103 | 
9747 | 
143 | 
0 | 
0 | 
| T106 | 
91319 | 
1289 | 
0 | 
0 | 
| T118 | 
5383 | 
78 | 
0 | 
0 | 
| T122 | 
269812 | 
609 | 
0 | 
0 | 
| T123 | 
180326 | 
454 | 
0 | 
0 | 
| T153 | 
14063 | 
52 | 
0 | 
0 | 
| T154 | 
13262 | 
21 | 
0 | 
0 | 
| T155 | 
14655 | 
102 | 
0 | 
0 | 
| T156 | 
106514 | 
2176 | 
0 | 
0 | 
| T157 | 
13350 | 
6 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
11574 | 
0 | 
0 | 
| T103 | 
9747 | 
145 | 
0 | 
0 | 
| T106 | 
91319 | 
1108 | 
0 | 
0 | 
| T118 | 
5383 | 
3 | 
0 | 
0 | 
| T122 | 
269812 | 
659 | 
0 | 
0 | 
| T123 | 
180326 | 
509 | 
0 | 
0 | 
| T153 | 
14063 | 
56 | 
0 | 
0 | 
| T154 | 
13262 | 
89 | 
0 | 
0 | 
| T155 | 
14655 | 
127 | 
0 | 
0 | 
| T156 | 
106514 | 
1352 | 
0 | 
0 | 
| T157 | 
13350 | 
44 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7128 | 
0 | 
0 | 
| T103 | 
9747 | 
23 | 
0 | 
0 | 
| T105 | 
14727 | 
5 | 
0 | 
0 | 
| T106 | 
91319 | 
371 | 
0 | 
0 | 
| T118 | 
5383 | 
1 | 
0 | 
0 | 
| T122 | 
269812 | 
694 | 
0 | 
0 | 
| T123 | 
180326 | 
464 | 
0 | 
0 | 
| T153 | 
14063 | 
15 | 
0 | 
0 | 
| T154 | 
13262 | 
51 | 
0 | 
0 | 
| T155 | 
14655 | 
13 | 
0 | 
0 | 
| T156 | 
106514 | 
659 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6899 | 
0 | 
0 | 
| T103 | 
9747 | 
28 | 
0 | 
0 | 
| T106 | 
91319 | 
442 | 
0 | 
0 | 
| T118 | 
5383 | 
17 | 
0 | 
0 | 
| T122 | 
269812 | 
648 | 
0 | 
0 | 
| T123 | 
180326 | 
465 | 
0 | 
0 | 
| T153 | 
14063 | 
50 | 
0 | 
0 | 
| T154 | 
13262 | 
23 | 
0 | 
0 | 
| T155 | 
14655 | 
47 | 
0 | 
0 | 
| T156 | 
106514 | 
973 | 
0 | 
0 | 
| T157 | 
13350 | 
43 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6700 | 
0 | 
0 | 
| T103 | 
9747 | 
75 | 
0 | 
0 | 
| T106 | 
91319 | 
397 | 
0 | 
0 | 
| T118 | 
5383 | 
42 | 
0 | 
0 | 
| T122 | 
269812 | 
678 | 
0 | 
0 | 
| T123 | 
180326 | 
451 | 
0 | 
0 | 
| T153 | 
14063 | 
67 | 
0 | 
0 | 
| T154 | 
13262 | 
32 | 
0 | 
0 | 
| T155 | 
14655 | 
54 | 
0 | 
0 | 
| T156 | 
106514 | 
760 | 
0 | 
0 | 
| T157 | 
13350 | 
6 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7301 | 
0 | 
0 | 
| T103 | 
9747 | 
117 | 
0 | 
0 | 
| T106 | 
91319 | 
394 | 
0 | 
0 | 
| T113 | 
20364 | 
5 | 
0 | 
0 | 
| T118 | 
5383 | 
2 | 
0 | 
0 | 
| T122 | 
269812 | 
612 | 
0 | 
0 | 
| T123 | 
180326 | 
443 | 
0 | 
0 | 
| T153 | 
14063 | 
63 | 
0 | 
0 | 
| T154 | 
13262 | 
40 | 
0 | 
0 | 
| T155 | 
14655 | 
100 | 
0 | 
0 | 
| T156 | 
106514 | 
647 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6639 | 
0 | 
0 | 
| T103 | 
9747 | 
106 | 
0 | 
0 | 
| T106 | 
91319 | 
409 | 
0 | 
0 | 
| T118 | 
5383 | 
6 | 
0 | 
0 | 
| T122 | 
269812 | 
681 | 
0 | 
0 | 
| T123 | 
180326 | 
432 | 
0 | 
0 | 
| T153 | 
14063 | 
31 | 
0 | 
0 | 
| T154 | 
13262 | 
29 | 
0 | 
0 | 
| T155 | 
14655 | 
53 | 
0 | 
0 | 
| T156 | 
106514 | 
507 | 
0 | 
0 | 
| T157 | 
13350 | 
57 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7510 | 
0 | 
0 | 
| T103 | 
9747 | 
20 | 
0 | 
0 | 
| T106 | 
91319 | 
488 | 
0 | 
0 | 
| T118 | 
5383 | 
5 | 
0 | 
0 | 
| T122 | 
269812 | 
614 | 
0 | 
0 | 
| T123 | 
180326 | 
430 | 
0 | 
0 | 
| T153 | 
14063 | 
70 | 
0 | 
0 | 
| T154 | 
13262 | 
23 | 
0 | 
0 | 
| T155 | 
14655 | 
75 | 
0 | 
0 | 
| T156 | 
106514 | 
1112 | 
0 | 
0 | 
| T157 | 
13350 | 
15 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7131 | 
0 | 
0 | 
| T103 | 
9747 | 
78 | 
0 | 
0 | 
| T106 | 
91319 | 
513 | 
0 | 
0 | 
| T118 | 
5383 | 
40 | 
0 | 
0 | 
| T122 | 
269812 | 
653 | 
0 | 
0 | 
| T123 | 
180326 | 
452 | 
0 | 
0 | 
| T153 | 
14063 | 
73 | 
0 | 
0 | 
| T154 | 
13262 | 
64 | 
0 | 
0 | 
| T155 | 
14655 | 
62 | 
0 | 
0 | 
| T156 | 
106514 | 
824 | 
0 | 
0 | 
| T157 | 
13350 | 
33 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7380 | 
0 | 
0 | 
| T103 | 
9747 | 
60 | 
0 | 
0 | 
| T106 | 
91319 | 
472 | 
0 | 
0 | 
| T113 | 
20364 | 
6 | 
0 | 
0 | 
| T118 | 
5383 | 
33 | 
0 | 
0 | 
| T122 | 
269812 | 
613 | 
0 | 
0 | 
| T123 | 
180326 | 
423 | 
0 | 
0 | 
| T153 | 
14063 | 
53 | 
0 | 
0 | 
| T154 | 
13262 | 
83 | 
0 | 
0 | 
| T155 | 
14655 | 
72 | 
0 | 
0 | 
| T156 | 
106514 | 
1005 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7167 | 
0 | 
0 | 
| T103 | 
9747 | 
23 | 
0 | 
0 | 
| T106 | 
91319 | 
446 | 
0 | 
0 | 
| T118 | 
5383 | 
13 | 
0 | 
0 | 
| T122 | 
269812 | 
665 | 
0 | 
0 | 
| T123 | 
180326 | 
437 | 
0 | 
0 | 
| T153 | 
14063 | 
29 | 
0 | 
0 | 
| T154 | 
13262 | 
17 | 
0 | 
0 | 
| T155 | 
14655 | 
36 | 
0 | 
0 | 
| T156 | 
106514 | 
994 | 
0 | 
0 | 
| T157 | 
13350 | 
13 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7209 | 
0 | 
0 | 
| T103 | 
9747 | 
116 | 
0 | 
0 | 
| T106 | 
91319 | 
345 | 
0 | 
0 | 
| T118 | 
5383 | 
11 | 
0 | 
0 | 
| T122 | 
269812 | 
670 | 
0 | 
0 | 
| T123 | 
180326 | 
483 | 
0 | 
0 | 
| T153 | 
14063 | 
37 | 
0 | 
0 | 
| T154 | 
13262 | 
55 | 
0 | 
0 | 
| T155 | 
14655 | 
49 | 
0 | 
0 | 
| T156 | 
106514 | 
931 | 
0 | 
0 | 
| T157 | 
13350 | 
16 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7407 | 
0 | 
0 | 
| T103 | 
9747 | 
69 | 
0 | 
0 | 
| T106 | 
91319 | 
551 | 
0 | 
0 | 
| T113 | 
20364 | 
8 | 
0 | 
0 | 
| T118 | 
5383 | 
30 | 
0 | 
0 | 
| T122 | 
269812 | 
658 | 
0 | 
0 | 
| T123 | 
180326 | 
434 | 
0 | 
0 | 
| T153 | 
14063 | 
29 | 
0 | 
0 | 
| T154 | 
13262 | 
14 | 
0 | 
0 | 
| T155 | 
14655 | 
33 | 
0 | 
0 | 
| T156 | 
106514 | 
887 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7021 | 
0 | 
0 | 
| T103 | 
9747 | 
43 | 
0 | 
0 | 
| T106 | 
91319 | 
268 | 
0 | 
0 | 
| T122 | 
269812 | 
655 | 
0 | 
0 | 
| T123 | 
180326 | 
443 | 
0 | 
0 | 
| T153 | 
14063 | 
52 | 
0 | 
0 | 
| T154 | 
13262 | 
30 | 
0 | 
0 | 
| T155 | 
14655 | 
41 | 
0 | 
0 | 
| T156 | 
106514 | 
950 | 
0 | 
0 | 
| T157 | 
13350 | 
16 | 
0 | 
0 | 
| T158 | 
102384 | 
892 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7139 | 
0 | 
0 | 
| T103 | 
9747 | 
13 | 
0 | 
0 | 
| T106 | 
91319 | 
552 | 
0 | 
0 | 
| T118 | 
5383 | 
29 | 
0 | 
0 | 
| T122 | 
269812 | 
705 | 
0 | 
0 | 
| T123 | 
180326 | 
433 | 
0 | 
0 | 
| T153 | 
14063 | 
61 | 
0 | 
0 | 
| T154 | 
13262 | 
29 | 
0 | 
0 | 
| T155 | 
14655 | 
31 | 
0 | 
0 | 
| T156 | 
106514 | 
766 | 
0 | 
0 | 
| T157 | 
13350 | 
53 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7207 | 
0 | 
0 | 
| T103 | 
9747 | 
40 | 
0 | 
0 | 
| T106 | 
91319 | 
422 | 
0 | 
0 | 
| T118 | 
5383 | 
3 | 
0 | 
0 | 
| T122 | 
269812 | 
688 | 
0 | 
0 | 
| T123 | 
180326 | 
406 | 
0 | 
0 | 
| T153 | 
14063 | 
25 | 
0 | 
0 | 
| T154 | 
13262 | 
17 | 
0 | 
0 | 
| T155 | 
14655 | 
118 | 
0 | 
0 | 
| T156 | 
106514 | 
905 | 
0 | 
0 | 
| T157 | 
13350 | 
71 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7278 | 
0 | 
0 | 
| T103 | 
9747 | 
13 | 
0 | 
0 | 
| T106 | 
91319 | 
389 | 
0 | 
0 | 
| T118 | 
5383 | 
5 | 
0 | 
0 | 
| T122 | 
269812 | 
735 | 
0 | 
0 | 
| T123 | 
180326 | 
456 | 
0 | 
0 | 
| T153 | 
14063 | 
100 | 
0 | 
0 | 
| T154 | 
13262 | 
11 | 
0 | 
0 | 
| T155 | 
14655 | 
6 | 
0 | 
0 | 
| T156 | 
106514 | 
1107 | 
0 | 
0 | 
| T157 | 
13350 | 
22 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7077 | 
0 | 
0 | 
| T103 | 
9747 | 
85 | 
0 | 
0 | 
| T105 | 
14727 | 
6 | 
0 | 
0 | 
| T106 | 
91319 | 
376 | 
0 | 
0 | 
| T113 | 
20364 | 
4 | 
0 | 
0 | 
| T118 | 
5383 | 
7 | 
0 | 
0 | 
| T122 | 
269812 | 
654 | 
0 | 
0 | 
| T123 | 
180326 | 
446 | 
0 | 
0 | 
| T153 | 
14063 | 
54 | 
0 | 
0 | 
| T154 | 
13262 | 
53 | 
0 | 
0 | 
| T155 | 
14655 | 
29 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6764 | 
0 | 
0 | 
| T103 | 
9747 | 
62 | 
0 | 
0 | 
| T106 | 
91319 | 
390 | 
0 | 
0 | 
| T118 | 
5383 | 
20 | 
0 | 
0 | 
| T122 | 
269812 | 
723 | 
0 | 
0 | 
| T123 | 
180326 | 
441 | 
0 | 
0 | 
| T153 | 
14063 | 
38 | 
0 | 
0 | 
| T154 | 
13262 | 
46 | 
0 | 
0 | 
| T155 | 
14655 | 
43 | 
0 | 
0 | 
| T156 | 
106514 | 
676 | 
0 | 
0 | 
| T157 | 
13350 | 
61 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6677 | 
0 | 
0 | 
| T103 | 
9747 | 
64 | 
0 | 
0 | 
| T106 | 
91319 | 
489 | 
0 | 
0 | 
| T118 | 
5383 | 
5 | 
0 | 
0 | 
| T122 | 
269812 | 
659 | 
0 | 
0 | 
| T123 | 
180326 | 
465 | 
0 | 
0 | 
| T153 | 
14063 | 
93 | 
0 | 
0 | 
| T154 | 
13262 | 
37 | 
0 | 
0 | 
| T155 | 
14655 | 
40 | 
0 | 
0 | 
| T156 | 
106514 | 
545 | 
0 | 
0 | 
| T157 | 
13350 | 
40 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7201 | 
0 | 
0 | 
| T103 | 
9747 | 
20 | 
0 | 
0 | 
| T106 | 
91319 | 
415 | 
0 | 
0 | 
| T118 | 
5383 | 
30 | 
0 | 
0 | 
| T122 | 
269812 | 
695 | 
0 | 
0 | 
| T123 | 
180326 | 
516 | 
0 | 
0 | 
| T153 | 
14063 | 
40 | 
0 | 
0 | 
| T154 | 
13262 | 
55 | 
0 | 
0 | 
| T155 | 
14655 | 
69 | 
0 | 
0 | 
| T156 | 
106514 | 
674 | 
0 | 
0 | 
| T157 | 
13350 | 
34 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6926 | 
0 | 
0 | 
| T103 | 
9747 | 
12 | 
0 | 
0 | 
| T106 | 
91319 | 
439 | 
0 | 
0 | 
| T118 | 
5383 | 
1 | 
0 | 
0 | 
| T122 | 
269812 | 
699 | 
0 | 
0 | 
| T123 | 
180326 | 
447 | 
0 | 
0 | 
| T153 | 
14063 | 
45 | 
0 | 
0 | 
| T154 | 
13262 | 
86 | 
0 | 
0 | 
| T155 | 
14655 | 
100 | 
0 | 
0 | 
| T156 | 
106514 | 
820 | 
0 | 
0 | 
| T157 | 
13350 | 
35 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6924 | 
0 | 
0 | 
| T103 | 
9747 | 
16 | 
0 | 
0 | 
| T106 | 
91319 | 
370 | 
0 | 
0 | 
| T118 | 
5383 | 
21 | 
0 | 
0 | 
| T122 | 
269812 | 
711 | 
0 | 
0 | 
| T123 | 
180326 | 
426 | 
0 | 
0 | 
| T153 | 
14063 | 
67 | 
0 | 
0 | 
| T154 | 
13262 | 
59 | 
0 | 
0 | 
| T155 | 
14655 | 
40 | 
0 | 
0 | 
| T156 | 
106514 | 
816 | 
0 | 
0 | 
| T157 | 
13350 | 
68 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6770 | 
0 | 
0 | 
| T103 | 
9747 | 
17 | 
0 | 
0 | 
| T105 | 
14727 | 
3 | 
0 | 
0 | 
| T106 | 
91319 | 
332 | 
0 | 
0 | 
| T118 | 
5383 | 
30 | 
0 | 
0 | 
| T122 | 
269812 | 
680 | 
0 | 
0 | 
| T123 | 
180326 | 
479 | 
0 | 
0 | 
| T153 | 
14063 | 
36 | 
0 | 
0 | 
| T154 | 
13262 | 
58 | 
0 | 
0 | 
| T155 | 
14655 | 
24 | 
0 | 
0 | 
| T156 | 
106514 | 
693 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7180 | 
0 | 
0 | 
| T103 | 
9747 | 
45 | 
0 | 
0 | 
| T106 | 
91319 | 
409 | 
0 | 
0 | 
| T118 | 
5383 | 
34 | 
0 | 
0 | 
| T122 | 
269812 | 
625 | 
0 | 
0 | 
| T123 | 
180326 | 
536 | 
0 | 
0 | 
| T153 | 
14063 | 
18 | 
0 | 
0 | 
| T154 | 
13262 | 
35 | 
0 | 
0 | 
| T155 | 
14655 | 
79 | 
0 | 
0 | 
| T156 | 
106514 | 
837 | 
0 | 
0 | 
| T157 | 
13350 | 
76 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
7067 | 
0 | 
0 | 
| T103 | 
9747 | 
11 | 
0 | 
0 | 
| T106 | 
91319 | 
372 | 
0 | 
0 | 
| T118 | 
5383 | 
26 | 
0 | 
0 | 
| T122 | 
269812 | 
641 | 
0 | 
0 | 
| T123 | 
180326 | 
481 | 
0 | 
0 | 
| T153 | 
14063 | 
22 | 
0 | 
0 | 
| T154 | 
13262 | 
67 | 
0 | 
0 | 
| T155 | 
14655 | 
12 | 
0 | 
0 | 
| T156 | 
106514 | 
754 | 
0 | 
0 | 
| T157 | 
13350 | 
77 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4507 | 
0 | 
0 | 
| T103 | 
9747 | 
21 | 
0 | 
0 | 
| T106 | 
91319 | 
120 | 
0 | 
0 | 
| T118 | 
5383 | 
16 | 
0 | 
0 | 
| T122 | 
269812 | 
709 | 
0 | 
0 | 
| T123 | 
180326 | 
434 | 
0 | 
0 | 
| T153 | 
14063 | 
25 | 
0 | 
0 | 
| T154 | 
13262 | 
57 | 
0 | 
0 | 
| T155 | 
14655 | 
5 | 
0 | 
0 | 
| T156 | 
106514 | 
160 | 
0 | 
0 | 
| T157 | 
13350 | 
40 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4660 | 
0 | 
0 | 
| T103 | 
9747 | 
6 | 
0 | 
0 | 
| T106 | 
91319 | 
114 | 
0 | 
0 | 
| T118 | 
5383 | 
9 | 
0 | 
0 | 
| T122 | 
269812 | 
636 | 
0 | 
0 | 
| T123 | 
180326 | 
403 | 
0 | 
0 | 
| T153 | 
14063 | 
45 | 
0 | 
0 | 
| T154 | 
13262 | 
72 | 
0 | 
0 | 
| T155 | 
14655 | 
32 | 
0 | 
0 | 
| T156 | 
106514 | 
148 | 
0 | 
0 | 
| T157 | 
13350 | 
32 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4653 | 
0 | 
0 | 
| T103 | 
9747 | 
11 | 
0 | 
0 | 
| T106 | 
91319 | 
82 | 
0 | 
0 | 
| T118 | 
5383 | 
9 | 
0 | 
0 | 
| T122 | 
269812 | 
707 | 
0 | 
0 | 
| T123 | 
180326 | 
453 | 
0 | 
0 | 
| T153 | 
14063 | 
51 | 
0 | 
0 | 
| T154 | 
13262 | 
34 | 
0 | 
0 | 
| T155 | 
14655 | 
21 | 
0 | 
0 | 
| T156 | 
106514 | 
163 | 
0 | 
0 | 
| T157 | 
13350 | 
38 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4656 | 
0 | 
0 | 
| T103 | 
9747 | 
38 | 
0 | 
0 | 
| T106 | 
91319 | 
101 | 
0 | 
0 | 
| T118 | 
5383 | 
14 | 
0 | 
0 | 
| T122 | 
269812 | 
679 | 
0 | 
0 | 
| T123 | 
180326 | 
490 | 
0 | 
0 | 
| T153 | 
14063 | 
29 | 
0 | 
0 | 
| T154 | 
13262 | 
41 | 
0 | 
0 | 
| T155 | 
14655 | 
25 | 
0 | 
0 | 
| T156 | 
106514 | 
143 | 
0 | 
0 | 
| T157 | 
13350 | 
47 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4758 | 
0 | 
0 | 
| T103 | 
9747 | 
1 | 
0 | 
0 | 
| T106 | 
91319 | 
175 | 
0 | 
0 | 
| T118 | 
5383 | 
3 | 
0 | 
0 | 
| T122 | 
269812 | 
614 | 
0 | 
0 | 
| T123 | 
180326 | 
422 | 
0 | 
0 | 
| T153 | 
14063 | 
51 | 
0 | 
0 | 
| T154 | 
13262 | 
59 | 
0 | 
0 | 
| T155 | 
14655 | 
23 | 
0 | 
0 | 
| T156 | 
106514 | 
159 | 
0 | 
0 | 
| T157 | 
13350 | 
27 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
6497 | 
0 | 
0 | 
| T5 | 
446152 | 
4 | 
0 | 
0 | 
| T6 | 
1071 | 
0 | 
0 | 
0 | 
| T7 | 
201504 | 
0 | 
0 | 
0 | 
| T8 | 
2856 | 
0 | 
0 | 
0 | 
| T9 | 
188811 | 
0 | 
0 | 
0 | 
| T10 | 
122758 | 
0 | 
0 | 
0 | 
| T11 | 
131122 | 
0 | 
0 | 
0 | 
| T12 | 
225633 | 
0 | 
0 | 
0 | 
| T13 | 
155600 | 
0 | 
0 | 
0 | 
| T15 | 
0 | 
22 | 
0 | 
0 | 
| T17 | 
0 | 
28 | 
0 | 
0 | 
| T20 | 
0 | 
5 | 
0 | 
0 | 
| T31 | 
152008 | 
0 | 
0 | 
0 | 
| T142 | 
0 | 
24 | 
0 | 
0 | 
| T145 | 
0 | 
34 | 
0 | 
0 | 
| T159 | 
0 | 
27 | 
0 | 
0 | 
| T160 | 
0 | 
78 | 
0 | 
0 | 
| T161 | 
0 | 
17 | 
0 | 
0 | 
| T162 | 
0 | 
18 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4420 | 
0 | 
0 | 
| T103 | 
9747 | 
19 | 
0 | 
0 | 
| T106 | 
91319 | 
122 | 
0 | 
0 | 
| T122 | 
269812 | 
623 | 
0 | 
0 | 
| T123 | 
180326 | 
448 | 
0 | 
0 | 
| T153 | 
14063 | 
13 | 
0 | 
0 | 
| T154 | 
13262 | 
40 | 
0 | 
0 | 
| T155 | 
14655 | 
28 | 
0 | 
0 | 
| T156 | 
106514 | 
170 | 
0 | 
0 | 
| T157 | 
13350 | 
17 | 
0 | 
0 | 
| T158 | 
102384 | 
185 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4548 | 
0 | 
0 | 
| T103 | 
9747 | 
22 | 
0 | 
0 | 
| T106 | 
91319 | 
99 | 
0 | 
0 | 
| T118 | 
5383 | 
11 | 
0 | 
0 | 
| T122 | 
269812 | 
683 | 
0 | 
0 | 
| T123 | 
180326 | 
467 | 
0 | 
0 | 
| T153 | 
14063 | 
42 | 
0 | 
0 | 
| T154 | 
13262 | 
30 | 
0 | 
0 | 
| T155 | 
14655 | 
19 | 
0 | 
0 | 
| T156 | 
106514 | 
154 | 
0 | 
0 | 
| T157 | 
13350 | 
75 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4240 | 
0 | 
0 | 
| T103 | 
9747 | 
20 | 
0 | 
0 | 
| T106 | 
91319 | 
44 | 
0 | 
0 | 
| T118 | 
5383 | 
10 | 
0 | 
0 | 
| T122 | 
269812 | 
619 | 
0 | 
0 | 
| T123 | 
180326 | 
432 | 
0 | 
0 | 
| T153 | 
14063 | 
30 | 
0 | 
0 | 
| T154 | 
13262 | 
77 | 
0 | 
0 | 
| T155 | 
14655 | 
23 | 
0 | 
0 | 
| T156 | 
106514 | 
120 | 
0 | 
0 | 
| T157 | 
13350 | 
33 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4429 | 
0 | 
0 | 
| T103 | 
9747 | 
22 | 
0 | 
0 | 
| T106 | 
91319 | 
56 | 
0 | 
0 | 
| T118 | 
5383 | 
4 | 
0 | 
0 | 
| T122 | 
269812 | 
602 | 
0 | 
0 | 
| T123 | 
180326 | 
449 | 
0 | 
0 | 
| T153 | 
14063 | 
61 | 
0 | 
0 | 
| T154 | 
13262 | 
44 | 
0 | 
0 | 
| T155 | 
14655 | 
5 | 
0 | 
0 | 
| T156 | 
106514 | 
141 | 
0 | 
0 | 
| T157 | 
13350 | 
62 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4111 | 
0 | 
0 | 
| T103 | 
9747 | 
19 | 
0 | 
0 | 
| T106 | 
91319 | 
67 | 
0 | 
0 | 
| T122 | 
269812 | 
698 | 
0 | 
0 | 
| T123 | 
180326 | 
408 | 
0 | 
0 | 
| T153 | 
14063 | 
26 | 
0 | 
0 | 
| T154 | 
13262 | 
19 | 
0 | 
0 | 
| T155 | 
14655 | 
7 | 
0 | 
0 | 
| T156 | 
106514 | 
132 | 
0 | 
0 | 
| T157 | 
13350 | 
26 | 
0 | 
0 | 
| T158 | 
102384 | 
118 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4339 | 
0 | 
0 | 
| T103 | 
9747 | 
16 | 
0 | 
0 | 
| T106 | 
91319 | 
60 | 
0 | 
0 | 
| T118 | 
5383 | 
8 | 
0 | 
0 | 
| T122 | 
269812 | 
645 | 
0 | 
0 | 
| T123 | 
180326 | 
460 | 
0 | 
0 | 
| T153 | 
14063 | 
100 | 
0 | 
0 | 
| T154 | 
13262 | 
11 | 
0 | 
0 | 
| T155 | 
14655 | 
7 | 
0 | 
0 | 
| T156 | 
106514 | 
109 | 
0 | 
0 | 
| T157 | 
13350 | 
48 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4898 | 
0 | 
0 | 
| T103 | 
9747 | 
31 | 
0 | 
0 | 
| T105 | 
14727 | 
3 | 
0 | 
0 | 
| T106 | 
91319 | 
113 | 
0 | 
0 | 
| T118 | 
5383 | 
9 | 
0 | 
0 | 
| T122 | 
269812 | 
738 | 
0 | 
0 | 
| T123 | 
180326 | 
442 | 
0 | 
0 | 
| T153 | 
14063 | 
38 | 
0 | 
0 | 
| T154 | 
13262 | 
30 | 
0 | 
0 | 
| T155 | 
14655 | 
11 | 
0 | 
0 | 
| T156 | 
106514 | 
288 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4198 | 
0 | 
0 | 
| T103 | 
9747 | 
17 | 
0 | 
0 | 
| T106 | 
91319 | 
59 | 
0 | 
0 | 
| T122 | 
269812 | 
630 | 
0 | 
0 | 
| T123 | 
180326 | 
409 | 
0 | 
0 | 
| T153 | 
14063 | 
35 | 
0 | 
0 | 
| T154 | 
13262 | 
20 | 
0 | 
0 | 
| T155 | 
14655 | 
15 | 
0 | 
0 | 
| T156 | 
106514 | 
114 | 
0 | 
0 | 
| T157 | 
13350 | 
37 | 
0 | 
0 | 
| T158 | 
102384 | 
117 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
5027 | 
0 | 
0 | 
| T103 | 
9747 | 
23 | 
0 | 
0 | 
| T106 | 
91319 | 
251 | 
0 | 
0 | 
| T118 | 
5383 | 
6 | 
0 | 
0 | 
| T122 | 
269812 | 
641 | 
0 | 
0 | 
| T123 | 
180326 | 
462 | 
0 | 
0 | 
| T153 | 
14063 | 
15 | 
0 | 
0 | 
| T154 | 
13262 | 
22 | 
0 | 
0 | 
| T155 | 
14655 | 
16 | 
0 | 
0 | 
| T156 | 
106514 | 
374 | 
0 | 
0 | 
| T157 | 
13350 | 
9 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4586 | 
0 | 
0 | 
| T103 | 
9747 | 
24 | 
0 | 
0 | 
| T106 | 
91319 | 
98 | 
0 | 
0 | 
| T113 | 
20364 | 
3 | 
0 | 
0 | 
| T118 | 
5383 | 
15 | 
0 | 
0 | 
| T122 | 
269812 | 
740 | 
0 | 
0 | 
| T123 | 
180326 | 
461 | 
0 | 
0 | 
| T153 | 
14063 | 
80 | 
0 | 
0 | 
| T154 | 
13262 | 
28 | 
0 | 
0 | 
| T155 | 
14655 | 
12 | 
0 | 
0 | 
| T156 | 
106514 | 
161 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4336 | 
0 | 
0 | 
| T103 | 
9747 | 
14 | 
0 | 
0 | 
| T106 | 
91319 | 
56 | 
0 | 
0 | 
| T118 | 
5383 | 
1 | 
0 | 
0 | 
| T122 | 
269812 | 
679 | 
0 | 
0 | 
| T123 | 
180326 | 
509 | 
0 | 
0 | 
| T153 | 
14063 | 
34 | 
0 | 
0 | 
| T154 | 
13262 | 
32 | 
0 | 
0 | 
| T155 | 
14655 | 
21 | 
0 | 
0 | 
| T156 | 
106514 | 
107 | 
0 | 
0 | 
| T157 | 
13350 | 
58 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4101 | 
0 | 
0 | 
| T103 | 
9747 | 
14 | 
0 | 
0 | 
| T106 | 
91319 | 
82 | 
0 | 
0 | 
| T118 | 
5383 | 
3 | 
0 | 
0 | 
| T122 | 
269812 | 
634 | 
0 | 
0 | 
| T123 | 
180326 | 
482 | 
0 | 
0 | 
| T153 | 
14063 | 
66 | 
0 | 
0 | 
| T154 | 
13262 | 
43 | 
0 | 
0 | 
| T155 | 
14655 | 
8 | 
0 | 
0 | 
| T156 | 
106514 | 
109 | 
0 | 
0 | 
| T157 | 
13350 | 
10 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4224 | 
0 | 
0 | 
| T103 | 
9747 | 
19 | 
0 | 
0 | 
| T106 | 
91319 | 
42 | 
0 | 
0 | 
| T115 | 
15683 | 
4 | 
0 | 
0 | 
| T118 | 
5383 | 
4 | 
0 | 
0 | 
| T122 | 
269812 | 
611 | 
0 | 
0 | 
| T123 | 
180326 | 
431 | 
0 | 
0 | 
| T153 | 
14063 | 
33 | 
0 | 
0 | 
| T154 | 
13262 | 
80 | 
0 | 
0 | 
| T155 | 
14655 | 
6 | 
0 | 
0 | 
| T156 | 
106514 | 
108 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4180 | 
0 | 
0 | 
| T103 | 
9747 | 
12 | 
0 | 
0 | 
| T106 | 
91319 | 
62 | 
0 | 
0 | 
| T122 | 
269812 | 
602 | 
0 | 
0 | 
| T123 | 
180326 | 
418 | 
0 | 
0 | 
| T153 | 
14063 | 
60 | 
0 | 
0 | 
| T154 | 
13262 | 
28 | 
0 | 
0 | 
| T155 | 
14655 | 
17 | 
0 | 
0 | 
| T156 | 
106514 | 
131 | 
0 | 
0 | 
| T157 | 
13350 | 
47 | 
0 | 
0 | 
| T158 | 
102384 | 
97 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4388 | 
0 | 
0 | 
| T103 | 
9747 | 
11 | 
0 | 
0 | 
| T106 | 
91319 | 
50 | 
0 | 
0 | 
| T118 | 
5383 | 
10 | 
0 | 
0 | 
| T122 | 
269812 | 
707 | 
0 | 
0 | 
| T123 | 
180326 | 
461 | 
0 | 
0 | 
| T153 | 
14063 | 
23 | 
0 | 
0 | 
| T154 | 
13262 | 
57 | 
0 | 
0 | 
| T155 | 
14655 | 
19 | 
0 | 
0 | 
| T156 | 
106514 | 
107 | 
0 | 
0 | 
| T157 | 
13350 | 
34 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
440128918 | 
4264 | 
0 | 
0 | 
| T103 | 
9747 | 
22 | 
0 | 
0 | 
| T106 | 
91319 | 
54 | 
0 | 
0 | 
| T118 | 
5383 | 
8 | 
0 | 
0 | 
| T122 | 
269812 | 
659 | 
0 | 
0 | 
| T123 | 
180326 | 
459 | 
0 | 
0 | 
| T153 | 
14063 | 
76 | 
0 | 
0 | 
| T154 | 
13262 | 
28 | 
0 | 
0 | 
| T155 | 
14655 | 
12 | 
0 | 
0 | 
| T156 | 
106514 | 
91 | 
0 | 
0 | 
| T157 | 
13350 | 
17 | 
0 | 
0 |