Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3277457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4135190

1

T1

900

T2

15127

T3

919

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4111007	1			T1	37		T2	10897		T3	71
values[0x0]	1649564	1			T1	411		T2	4818		T3	410
values[0x1]	1652076	1			T1	472		T2	4871		T3	475

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2346066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5066581

1

T1

901

T2

16207

T3

923

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30268	1			T2	62		T3	12		T4	30
valid_sources[0x01]	28025	1			T2	65		T3	2		T4	10
valid_sources[0x02]	26320	1			T2	17		T3	4		T4	30
valid_sources[0x03]	29714	1			T2	183		T4	39		T5	16
valid_sources[0x04]	28208	1			T2	60		T4	7		T5	14
valid_sources[0x05]	31743	1			T2	31		T4	18		T5	14
valid_sources[0x06]	27089	1			T2	91		T4	27		T5	16
valid_sources[0x07]	32802	1			T2	173		T3	10		T4	12
valid_sources[0x08]	30178	1			T2	60		T3	28		T4	15
valid_sources[0x09]	32225	1			T2	40		T3	4		T4	21
valid_sources[0x0a]	26801	1			T2	92		T4	28		T5	21
valid_sources[0x0b]	28782	1			T2	159		T4	28		T5	18
valid_sources[0x0c]	26245	1			T2	86		T4	13		T5	14
valid_sources[0x0d]	31109	1			T2	74		T4	14		T5	25
valid_sources[0x0e]	26231	1			T2	35		T4	9		T5	24
valid_sources[0x0f]	26103	1			T2	72		T4	22		T5	20
valid_sources[0x10]	25624	1			T2	89		T3	33		T4	17
valid_sources[0x11]	28270	1			T2	102		T3	2		T4	23
valid_sources[0x12]	36988	1			T2	110		T4	27		T5	26
valid_sources[0x13]	28786	1			T2	77		T4	27		T5	20
valid_sources[0x14]	28684	1			T2	127		T4	24		T5	18
valid_sources[0x15]	31935	1			T2	79		T3	1		T4	2
valid_sources[0x16]	32252	1			T2	92		T3	40		T4	28
valid_sources[0x17]	30782	1			T2	68		T4	30		T5	22
valid_sources[0x18]	26039	1			T1	502		T2	26		T3	30
valid_sources[0x19]	26342	1			T1	1		T2	99		T4	46
valid_sources[0x1a]	29801	1			T2	38		T3	6		T4	21
valid_sources[0x1b]	30966	1			T2	61		T3	5		T4	21
valid_sources[0x1c]	30220	1			T2	55		T3	4		T4	5
valid_sources[0x1d]	29982	1			T2	56		T4	35		T5	19
valid_sources[0x1e]	26719	1			T2	76		T3	9		T4	27
valid_sources[0x1f]	26005	1			T2	60		T3	1		T4	18
valid_sources[0x20]	26195	1			T2	157		T4	7		T5	22
valid_sources[0x21]	59198	1			T2	79		T3	1		T4	23
valid_sources[0x22]	27260	1			T2	168		T4	18		T5	20
valid_sources[0x23]	27215	1			T2	49		T3	5		T4	15
valid_sources[0x24]	25926	1			T2	138		T4	20		T5	16
valid_sources[0x25]	29228	1			T2	33		T4	25		T5	16
valid_sources[0x26]	26551	1			T2	83		T3	2		T4	39
valid_sources[0x27]	29020	1			T2	109		T3	8		T4	34
valid_sources[0x28]	28329	1			T2	20		T3	13		T4	31
valid_sources[0x29]	27479	1			T2	78		T4	13		T5	11
valid_sources[0x2a]	28920	1			T2	160		T4	16		T5	19
valid_sources[0x2b]	25998	1			T2	91		T3	1		T4	35
valid_sources[0x2c]	27313	1			T2	11		T3	2		T4	9
valid_sources[0x2d]	28232	1			T2	57		T3	5		T4	32
valid_sources[0x2e]	24952	1			T2	49		T4	10		T5	17
valid_sources[0x2f]	28160	1			T2	73		T3	2		T4	23
valid_sources[0x30]	28404	1			T2	81		T4	19		T5	21
valid_sources[0x31]	29168	1			T2	87		T4	18		T5	30
valid_sources[0x32]	27183	1			T1	416		T2	73		T3	18
valid_sources[0x33]	26748	1			T2	59		T3	1		T4	29
valid_sources[0x34]	27390	1			T2	94		T3	13		T4	4
valid_sources[0x35]	25643	1			T2	101		T4	23		T5	26
valid_sources[0x36]	28670	1			T2	39		T4	14		T5	15
valid_sources[0x37]	32032	1			T2	88		T4	13		T5	20
valid_sources[0x38]	27153	1			T2	46		T4	21		T5	20
valid_sources[0x39]	27119	1			T2	70		T3	16		T4	23
valid_sources[0x3a]	27074	1			T2	123		T4	33		T5	25
valid_sources[0x3b]	29925	1			T2	108		T4	17		T5	14
valid_sources[0x3c]	30838	1			T2	166		T3	7		T4	20
valid_sources[0x3d]	31052	1			T2	78		T4	32		T5	22
valid_sources[0x3e]	28294	1			T2	54		T4	26		T5	18
valid_sources[0x3f]	29932	1			T2	99		T4	14		T5	9
valid_sources[0x40]	25903	1			T2	9		T3	10		T4	35
valid_sources[0x41]	32309	1			T2	120		T5	24		T6	1
valid_sources[0x42]	27886	1			T2	44		T3	16		T4	49
valid_sources[0x43]	25745	1			T2	60		T3	1		T4	13
valid_sources[0x44]	28428	1			T2	92		T4	54		T5	8
valid_sources[0x45]	27219	1			T2	60		T4	18		T5	17
valid_sources[0x46]	27614	1			T2	41		T3	2		T4	34
valid_sources[0x47]	27827	1			T2	35		T3	27		T4	51
valid_sources[0x48]	31258	1			T2	44		T4	32		T5	22
valid_sources[0x49]	26295	1			T2	11		T4	12		T5	22
valid_sources[0x4a]	28240	1			T2	156		T4	41		T5	14
valid_sources[0x4b]	30224	1			T2	150		T3	2		T4	5
valid_sources[0x4c]	27185	1			T2	97		T3	4		T4	28
valid_sources[0x4d]	25754	1			T2	106		T3	8		T4	43
valid_sources[0x4e]	29301	1			T2	54		T4	9		T5	23
valid_sources[0x4f]	30455	1			T2	109		T4	9		T5	19
valid_sources[0x50]	25974	1			T2	16		T4	26		T5	19
valid_sources[0x51]	42895	1			T2	34		T4	26		T5	13
valid_sources[0x52]	25499	1			T2	25		T4	24		T5	14
valid_sources[0x53]	26125	1			T2	191		T3	26		T5	20
valid_sources[0x54]	32519	1			T2	167		T4	13		T5	28
valid_sources[0x55]	29384	1			T2	103		T3	1		T4	52
valid_sources[0x56]	25516	1			T2	56		T3	11		T4	14
valid_sources[0x57]	25509	1			T2	62		T4	10		T5	14
valid_sources[0x58]	27985	1			T2	106		T4	46		T5	18
valid_sources[0x59]	26640	1			T2	5		T4	10		T5	20
valid_sources[0x5a]	28820	1			T2	121		T4	25		T5	15
valid_sources[0x5b]	32913	1			T2	153		T4	3		T5	15
valid_sources[0x5c]	27169	1			T2	72		T4	35		T5	12
valid_sources[0x5d]	25427	1			T2	51		T3	1		T4	26
valid_sources[0x5e]	28045	1			T2	64		T4	2		T5	20
valid_sources[0x5f]	26670	1			T2	54		T4	24		T5	17
valid_sources[0x60]	26566	1			T2	138		T4	13		T5	14
valid_sources[0x61]	29798	1			T2	88		T3	17		T4	29
valid_sources[0x62]	29921	1			T2	188		T4	21		T5	24
valid_sources[0x63]	26266	1			T2	102		T4	12		T5	10
valid_sources[0x64]	28880	1			T2	141		T4	8		T5	18
valid_sources[0x65]	27098	1			T2	101		T4	23		T5	17
valid_sources[0x66]	30300	1			T2	42		T3	16		T4	6
valid_sources[0x67]	27631	1			T2	6		T3	5		T4	29
valid_sources[0x68]	26106	1			T2	57		T4	27		T5	30
valid_sources[0x69]	29703	1			T2	101		T3	12		T4	31
valid_sources[0x6a]	27882	1			T2	142		T3	5		T4	7
valid_sources[0x6b]	26962	1			T2	117		T4	9		T5	24
valid_sources[0x6c]	28638	1			T2	43		T4	12		T5	13
valid_sources[0x6d]	24625	1			T2	149		T3	5		T4	28
valid_sources[0x6e]	29754	1			T2	69		T4	19		T5	12
valid_sources[0x6f]	34839	1			T2	91		T4	10		T5	21
valid_sources[0x70]	30060	1			T2	96		T4	7		T5	27
valid_sources[0x71]	26199	1			T2	128		T4	42		T5	19
valid_sources[0x72]	29125	1			T2	37		T3	13		T4	26
valid_sources[0x73]	29588	1			T2	27		T4	35		T5	17
valid_sources[0x74]	35901	1			T2	72		T4	17		T5	26
valid_sources[0x75]	29379	1			T2	118		T3	8		T4	21
valid_sources[0x76]	25702	1			T2	218		T3	1		T4	21
valid_sources[0x77]	30162	1			T2	84		T4	18		T5	15
valid_sources[0x78]	28506	1			T2	98		T3	1		T4	26
valid_sources[0x79]	29094	1			T2	158		T3	13		T4	2
valid_sources[0x7a]	26350	1			T2	43		T3	3		T4	13
valid_sources[0x7b]	27314	1			T2	40		T4	23		T5	21
valid_sources[0x7c]	27561	1			T2	35		T4	25		T5	9
valid_sources[0x7d]	24727	1			T2	217		T4	21		T5	18
valid_sources[0x7e]	27085	1			T2	55		T4	42		T5	14
valid_sources[0x7f]	28059	1			T2	60		T4	20		T5	24
valid_sources[0x80]	27559	1			T2	53		T3	4		T4	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1127285

1

T1

19

T2

5483

T3

36

values[0x0]

all_enables

biggest_size

1514974

1

T1

410

T2

4809

T3

408

values[0x1]

all_enables

biggest_size

1492931

1

T1

471

T2

4835

T3

475