Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3304129

1

T1

20

T2

5459

T3

37

full_word

4134654

1

T1

900

T2

15127

T3

919

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7438413	1			T1	920		T2	20586		T3	956
auto[TlIntgErrCmd]	125	1			T109	4		T111	9		T112	5
auto[TlIntgErrData]	130	1			T109	4		T111	8		T112	3
auto[TlIntgErrBoth]	115	1			T109	2		T111	13		T112	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4115522

1

T1

37

T2

10897

T3

71

auto[1]

3323261

1

T1

883

T2

9689

T3

885

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2987796	1			T1	18		T2	5414		T3	35
auto[TlIntgErrNone]	partial	auto[1]	315992	1			T1	2		T2	45		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1127552	1			T1	19		T2	5483		T3	36
auto[TlIntgErrNone]	full_word	auto[1]	3007073	1			T1	881		T2	9644		T3	883
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T109	2		T111	4		T112	3
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T109	2		T111	5		T112	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T188	1		T185	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T185	3		T190	1		T187	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T109	2		T111	5		T112	1
auto[TlIntgErrData]	partial	auto[1]	59	1			T109	1		T111	3		T112	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T128	1		T191	1		T185	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T109	1		T186	1		T192	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T109	2		T111	4		T112	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T111	9		T112	1		T115	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T115	1		T128	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T115	1		T128	1		T126	1