Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444238720	2873149	0	0
DepthKnown_A	444238720	444108827	0	0
RvalidKnown_A	444238720	444108827	0	0
WreadyKnown_A	444238720	444108827	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	2873149	0	0
T1	21973	1663	0	0
T2	814305	14985	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	4990	0	0
T6	587066	0	0	0
T7	543113	0	0	0
T8	211100	0	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	18298	0	0
T12	0	1663	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444238720	3070397	0	0
DepthKnown_A	444238720	444108827	0	0
RvalidKnown_A	444238720	444108827	0	0
WreadyKnown_A	444238720	444108827	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	3070397	0	0
T1	21973	832	0	0
T2	814305	16083	0	0
T3	54354	3732	0	0
T4	142606	832	0	0
T5	115730	3328	0	0
T6	587066	0	0	0
T7	543113	0	0	0
T8	211100	0	0	0
T9	6579	832	0	0
T10	11414	3730	0	0
T11	0	13312	0	0
T12	0	832	0	0
T13	0	3835	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444238720	188042	0	0
DepthKnown_A	444238720	444108827	0	0
RvalidKnown_A	444238720	444108827	0	0
WreadyKnown_A	444238720	444108827	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	188042	0	0
T2	814305	66	0	0
T3	54354	0	0	0
T4	142606	0	0	0
T5	115730	194	0	0
T6	587066	0	0	0
T7	543113	545	0	0
T8	211100	709	0	0
T9	6579	0	0	0
T10	11414	0	0	0
T11	578968	2129	0	0
T27	0	251	0	0
T28	0	959	0	0
T31	0	538	0	0
T35	0	100	0	0
T38	0	434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444238720	394164	0	0
DepthKnown_A	444238720	444108827	0	0
RvalidKnown_A	444238720	444108827	0	0
WreadyKnown_A	444238720	444108827	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	394164	0	0
T2	814305	213	0	0
T3	54354	0	0	0
T4	142606	0	0	0
T5	115730	194	0	0
T6	587066	0	0	0
T7	543113	545	0	0
T8	211100	2252	0	0
T9	6579	0	0	0
T10	11414	0	0	0
T11	578968	2117	0	0
T27	0	251	0	0
T28	0	3630	0	0
T31	0	2383	0	0
T35	0	100	0	0
T38	0	434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444238720	5692977	0	0
DepthKnown_A	444238720	444108827	0	0
RvalidKnown_A	444238720	444108827	0	0
WreadyKnown_A	444238720	444108827	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	5692977	0	0
T1	21973	88	0	0
T2	814305	11399	0	0
T3	54354	124	0	0
T4	142606	4775	0	0
T5	115730	1149	0	0
T6	587066	652	0	0
T7	543113	9067	0	0
T8	211100	5810	0	0
T9	6579	286	0	0
T10	11414	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444238720	10811596	0	0
DepthKnown_A	444238720	444108827	0	0
RvalidKnown_A	444238720	444108827	0	0
WreadyKnown_A	444238720	444108827	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	10811596	0	0
T1	21973	88	0	0
T2	814305	35053	0	0
T3	54354	528	0	0
T4	142606	4775	0	0
T5	115730	1116	0	0
T6	587066	652	0	0
T7	543113	9005	0	0
T8	211100	17346	0	0
T9	6579	286	0	0
T10	11414	257	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444238720	444108827	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0