Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T11
1	0	Covered	T2,T5,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T5,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	740814551	590024760	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	740814551	3637643	0	0
GntImpliesValid_A	740814551	3637643	0	0
GrantKnown_A	740814551	590024760	0	0
IdxKnown_A	740814551	590024760	0	0
IndexIsCorrect_A	740814551	3637643	0	0
LockArbDecision_A	740814551	0	0	0
NoReadyValidNoGrant_A	740814551	0	0	0
ReadyAndValidImplyGrant_A	740814551	3637643	0	0
ReqAndReadyImplyGrant_A	740814551	3637643	0	0
ReqImpliesValid_A	740814551	3637643	0	0
ReqStaysHighUntilGranted0_M	740814551	0	0	0
RoundRobin_A	740814551	3	0	976
ValidKnown_A	740814551	590024760	0	0
gen_data_port_assertion.DataFlow_A	740814551	3637643	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	590024760	0	0
T1	30377	30282	0	0
T2	915289	914981	0	0
T3	93437	93362	0	0
T4	165058	164970	0	0
T5	455258	284704	0	0
T6	736384	658775	0	0
T7	683587	608992	0	0
T8	576126	391060	0	0
T9	27347	16910	0	0
T10	11414	11329	0	0
T11	349842	814199	0	0
T12	149003	148942	0	0
T13	13608	13608	0	0
T14	6722	6272	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3637643	0	0
T1	21973	832	0	0
T2	915289	9508	0	0
T3	93437	832	0	0
T4	165058	832	0	0
T5	455258	7017	0	0
T6	736384	0	0	0
T7	683587	4739	0	0
T8	576126	6121	0	0
T9	27347	832	0	0
T10	11414	832	0	0
T11	349842	29895	0	0
T12	298006	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T27	0	2956	0	0
T28	0	10093	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T42	0	4	0	0
T44	0	6448	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0
T56	0	4	0	0
T57	0	1603	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3637643	0	0
T1	21973	832	0	0
T2	915289	9508	0	0
T3	93437	832	0	0
T4	165058	832	0	0
T5	455258	7017	0	0
T6	736384	0	0	0
T7	683587	4739	0	0
T8	576126	6121	0	0
T9	27347	832	0	0
T10	11414	832	0	0
T11	349842	29895	0	0
T12	298006	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T27	0	2956	0	0
T28	0	10093	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T42	0	4	0	0
T44	0	6448	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0
T56	0	4	0	0
T57	0	1603	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	590024760	0	0
T1	30377	30282	0	0
T2	915289	914981	0	0
T3	93437	93362	0	0
T4	165058	164970	0	0
T5	455258	284704	0	0
T6	736384	658775	0	0
T7	683587	608992	0	0
T8	576126	391060	0	0
T9	27347	16910	0	0
T10	11414	11329	0	0
T11	349842	814199	0	0
T12	149003	148942	0	0
T13	13608	13608	0	0
T14	6722	6272	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	590024760	0	0
T1	30377	30282	0	0
T2	915289	914981	0	0
T3	93437	93362	0	0
T4	165058	164970	0	0
T5	455258	284704	0	0
T6	736384	658775	0	0
T7	683587	608992	0	0
T8	576126	391060	0	0
T9	27347	16910	0	0
T10	11414	11329	0	0
T11	349842	814199	0	0
T12	149003	148942	0	0
T13	13608	13608	0	0
T14	6722	6272	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3637643	0	0
T1	21973	832	0	0
T2	915289	9508	0	0
T3	93437	832	0	0
T4	165058	832	0	0
T5	455258	7017	0	0
T6	736384	0	0	0
T7	683587	4739	0	0
T8	576126	6121	0	0
T9	27347	832	0	0
T10	11414	832	0	0
T11	349842	29895	0	0
T12	298006	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T27	0	2956	0	0
T28	0	10093	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T42	0	4	0	0
T44	0	6448	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0
T56	0	4	0	0
T57	0	1603	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3637643	0	0
T1	21973	832	0	0
T2	915289	9508	0	0
T3	93437	832	0	0
T4	165058	832	0	0
T5	455258	7017	0	0
T6	736384	0	0	0
T7	683587	4739	0	0
T8	576126	6121	0	0
T9	27347	832	0	0
T10	11414	832	0	0
T11	349842	29895	0	0
T12	298006	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T27	0	2956	0	0
T28	0	10093	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T42	0	4	0	0
T44	0	6448	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0
T56	0	4	0	0
T57	0	1603	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3637643	0	0
T1	21973	832	0	0
T2	915289	9508	0	0
T3	93437	832	0	0
T4	165058	832	0	0
T5	455258	7017	0	0
T6	736384	0	0	0
T7	683587	4739	0	0
T8	576126	6121	0	0
T9	27347	832	0	0
T10	11414	832	0	0
T11	349842	29895	0	0
T12	298006	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T27	0	2956	0	0
T28	0	10093	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T42	0	4	0	0
T44	0	6448	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0
T56	0	4	0	0
T57	0	1603	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3637643	0	0
T1	21973	832	0	0
T2	915289	9508	0	0
T3	93437	832	0	0
T4	165058	832	0	0
T5	455258	7017	0	0
T6	736384	0	0	0
T7	683587	4739	0	0
T8	576126	6121	0	0
T9	27347	832	0	0
T10	11414	832	0	0
T11	349842	29895	0	0
T12	298006	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T27	0	2956	0	0
T28	0	10093	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T42	0	4	0	0
T44	0	6448	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0
T56	0	4	0	0
T57	0	1603	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3	0	976
T18	428444	1	0	1
T33	0	1	0	0
T58	0	1	0	0
T59	321311	0	0	1
T60	1034	0	0	1
T61	10824	0	0	1
T62	397602	0	0	1
T63	124893	0	0	1
T64	79823	0	0	1
T65	100101	0	0	1
T66	1700	0	0	1
T67	303276	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	590024760	0	0
T1	30377	30282	0	0
T2	915289	914981	0	0
T3	93437	93362	0	0
T4	165058	164970	0	0
T5	455258	284704	0	0
T6	736384	658775	0	0
T7	683587	608992	0	0
T8	576126	391060	0	0
T9	27347	16910	0	0
T10	11414	11329	0	0
T11	349842	814199	0	0
T12	149003	148942	0	0
T13	13608	13608	0	0
T14	6722	6272	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740814551	3637643	0	0
T1	21973	832	0	0
T2	915289	9508	0	0
T3	93437	832	0	0
T4	165058	832	0	0
T5	455258	7017	0	0
T6	736384	0	0	0
T7	683587	4739	0	0
T8	576126	6121	0	0
T9	27347	832	0	0
T10	11414	832	0	0
T11	349842	29895	0	0
T12	298006	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T27	0	2956	0	0
T28	0	10093	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T42	0	4	0	0
T44	0	6448	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0
T56	0	4	0	0
T57	0	1603	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149363051	30003335	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	149363051	602437	0	0
GntImpliesValid_A	149363051	602437	0	0
GrantKnown_A	149363051	30003335	0	0
IdxKnown_A	149363051	30003335	0	0
IndexIsCorrect_A	149363051	602437	0	0
LockArbDecision_A	149363051	0	0	0
NoReadyValidNoGrant_A	149363051	0	0	0
ReadyAndValidImplyGrant_A	149363051	602437	0	0
ReqAndReadyImplyGrant_A	149363051	602437	0	0
ReqImpliesValid_A	149363051	602437	0	0
ReqStaysHighUntilGranted0_M	149363051	0	0	0
RoundRobin_A	149363051	0	0	0
ValidKnown_A	149363051	30003335	0	0
gen_data_port_assertion.DataFlow_A	149363051	602437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	30003335	0	0
T5	169764	29048	0	0
T6	74659	71768	0	0
T7	70237	65936	0	0
T8	182513	180024	0	0
T9	10384	0	0	0
T11	174921	711760	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	602437	0	0
T5	169764	617	0	0
T6	74659	0	0	0
T7	70237	3191	0	0
T8	182513	4127	0	0
T9	10384	0	0	0
T11	174921	7893	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T28	0	3414	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	602437	0	0
T5	169764	617	0	0
T6	74659	0	0	0
T7	70237	3191	0	0
T8	182513	4127	0	0
T9	10384	0	0	0
T11	174921	7893	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T28	0	3414	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	30003335	0	0
T5	169764	29048	0	0
T6	74659	71768	0	0
T7	70237	65936	0	0
T8	182513	180024	0	0
T9	10384	0	0	0
T11	174921	711760	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	30003335	0	0
T5	169764	29048	0	0
T6	74659	71768	0	0
T7	70237	65936	0	0
T8	182513	180024	0	0
T9	10384	0	0	0
T11	174921	711760	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	602437	0	0
T5	169764	617	0	0
T6	74659	0	0	0
T7	70237	3191	0	0
T8	182513	4127	0	0
T9	10384	0	0	0
T11	174921	7893	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T28	0	3414	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	602437	0	0
T5	169764	617	0	0
T6	74659	0	0	0
T7	70237	3191	0	0
T8	182513	4127	0	0
T9	10384	0	0	0
T11	174921	7893	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T28	0	3414	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	602437	0	0
T5	169764	617	0	0
T6	74659	0	0	0
T7	70237	3191	0	0
T8	182513	4127	0	0
T9	10384	0	0	0
T11	174921	7893	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T28	0	3414	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	602437	0	0
T5	169764	617	0	0
T6	74659	0	0	0
T7	70237	3191	0	0
T8	182513	4127	0	0
T9	10384	0	0	0
T11	174921	7893	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T28	0	3414	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	30003335	0	0
T5	169764	29048	0	0
T6	74659	71768	0	0
T7	70237	65936	0	0
T8	182513	180024	0	0
T9	10384	0	0	0
T11	174921	711760	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	792	0	0
T24	0	504	0	0
T28	0	155888	0	0
T30	0	720	0	0
T31	0	232088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	602437	0	0
T5	169764	617	0	0
T6	74659	0	0	0
T7	70237	3191	0	0
T8	182513	4127	0	0
T9	10384	0	0	0
T11	174921	7893	0	0
T12	149003	0	0	0
T13	13608	0	0	0
T14	6722	0	0	0
T23	792	0	0	0
T28	0	3414	0	0
T31	0	2835	0	0
T38	0	3320	0	0
T53	0	15	0	0
T54	0	52	0	0
T55	0	724	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T11
1	0	Covered	T2,T5,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T5,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149363051	118020593	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	149363051	808872	0	0
GntImpliesValid_A	149363051	808872	0	0
GrantKnown_A	149363051	118020593	0	0
IdxKnown_A	149363051	118020593	0	0
IndexIsCorrect_A	149363051	808872	0	0
LockArbDecision_A	149363051	0	0	0
NoReadyValidNoGrant_A	149363051	0	0	0
ReadyAndValidImplyGrant_A	149363051	808872	0	0
ReqAndReadyImplyGrant_A	149363051	808872	0	0
ReqImpliesValid_A	149363051	808872	0	0
ReqStaysHighUntilGranted0_M	149363051	0	0	0
RoundRobin_A	149363051	0	0	0
ValidKnown_A	149363051	118020593	0	0
gen_data_port_assertion.DataFlow_A	149363051	808872	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	118020593	0	0
T1	8404	8404	0	0
T2	100984	100682	0	0
T3	39083	39058	0	0
T4	22452	22428	0	0
T5	169764	139976	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	10384	0	0
T11	174921	102439	0	0
T12	0	148942	0	0
T13	0	13608	0	0
T14	0	6272	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	808872	0	0
T2	100984	278	0	0
T3	39083	0	0	0
T4	22452	0	0	0
T5	169764	2760	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	0	0	0
T11	174921	4392	0	0
T12	149003	0	0	0
T27	0	2956	0	0
T28	0	6679	0	0
T42	0	4	0	0
T44	0	6448	0	0
T50	0	1678	0	0
T56	0	4	0	0
T57	0	1603	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	808872	0	0
T2	100984	278	0	0
T3	39083	0	0	0
T4	22452	0	0	0
T5	169764	2760	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	0	0	0
T11	174921	4392	0	0
T12	149003	0	0	0
T27	0	2956	0	0
T28	0	6679	0	0
T42	0	4	0	0
T44	0	6448	0	0
T50	0	1678	0	0
T56	0	4	0	0
T57	0	1603	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	118020593	0	0
T1	8404	8404	0	0
T2	100984	100682	0	0
T3	39083	39058	0	0
T4	22452	22428	0	0
T5	169764	139976	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	10384	0	0
T11	174921	102439	0	0
T12	0	148942	0	0
T13	0	13608	0	0
T14	0	6272	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	118020593	0	0
T1	8404	8404	0	0
T2	100984	100682	0	0
T3	39083	39058	0	0
T4	22452	22428	0	0
T5	169764	139976	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	10384	0	0
T11	174921	102439	0	0
T12	0	148942	0	0
T13	0	13608	0	0
T14	0	6272	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	808872	0	0
T2	100984	278	0	0
T3	39083	0	0	0
T4	22452	0	0	0
T5	169764	2760	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	0	0	0
T11	174921	4392	0	0
T12	149003	0	0	0
T27	0	2956	0	0
T28	0	6679	0	0
T42	0	4	0	0
T44	0	6448	0	0
T50	0	1678	0	0
T56	0	4	0	0
T57	0	1603	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	808872	0	0
T2	100984	278	0	0
T3	39083	0	0	0
T4	22452	0	0	0
T5	169764	2760	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	0	0	0
T11	174921	4392	0	0
T12	149003	0	0	0
T27	0	2956	0	0
T28	0	6679	0	0
T42	0	4	0	0
T44	0	6448	0	0
T50	0	1678	0	0
T56	0	4	0	0
T57	0	1603	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	808872	0	0
T2	100984	278	0	0
T3	39083	0	0	0
T4	22452	0	0	0
T5	169764	2760	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	0	0	0
T11	174921	4392	0	0
T12	149003	0	0	0
T27	0	2956	0	0
T28	0	6679	0	0
T42	0	4	0	0
T44	0	6448	0	0
T50	0	1678	0	0
T56	0	4	0	0
T57	0	1603	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	808872	0	0
T2	100984	278	0	0
T3	39083	0	0	0
T4	22452	0	0	0
T5	169764	2760	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	0	0	0
T11	174921	4392	0	0
T12	149003	0	0	0
T27	0	2956	0	0
T28	0	6679	0	0
T42	0	4	0	0
T44	0	6448	0	0
T50	0	1678	0	0
T56	0	4	0	0
T57	0	1603	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	118020593	0	0
T1	8404	8404	0	0
T2	100984	100682	0	0
T3	39083	39058	0	0
T4	22452	22428	0	0
T5	169764	139976	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	10384	0	0
T11	174921	102439	0	0
T12	0	148942	0	0
T13	0	13608	0	0
T14	0	6272	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149363051	808872	0	0
T2	100984	278	0	0
T3	39083	0	0	0
T4	22452	0	0	0
T5	169764	2760	0	0
T6	74659	0	0	0
T7	70237	0	0	0
T8	182513	0	0	0
T9	10384	0	0	0
T11	174921	4392	0	0
T12	149003	0	0	0
T27	0	2956	0	0
T28	0	6679	0	0
T42	0	4	0	0
T44	0	6448	0	0
T50	0	1678	0	0
T56	0	4	0	0
T57	0	1603	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442088449	442000832	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	442088449	2226334	0	0
GntImpliesValid_A	442088449	2226334	0	0
GrantKnown_A	442088449	442000832	0	0
IdxKnown_A	442088449	442000832	0	0
IndexIsCorrect_A	442088449	2226334	0	0
LockArbDecision_A	442088449	0	0	0
NoReadyValidNoGrant_A	442088449	0	0	0
ReadyAndValidImplyGrant_A	442088449	2226334	0	0
ReqAndReadyImplyGrant_A	442088449	2226334	0	0
ReqImpliesValid_A	442088449	2226334	0	0
ReqStaysHighUntilGranted0_M	442088449	0	0	0
RoundRobin_A	442088449	3	0	976
ValidKnown_A	442088449	442000832	0	0
gen_data_port_assertion.DataFlow_A	442088449	2226334	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	442000832	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	2226334	0	0
T1	21973	832	0	0
T2	814305	9230	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	3640	0	0
T6	587066	0	0	0
T7	543113	1548	0	0
T8	211100	1994	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	17610	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	2226334	0	0
T1	21973	832	0	0
T2	814305	9230	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	3640	0	0
T6	587066	0	0	0
T7	543113	1548	0	0
T8	211100	1994	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	17610	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	442000832	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	442000832	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	2226334	0	0
T1	21973	832	0	0
T2	814305	9230	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	3640	0	0
T6	587066	0	0	0
T7	543113	1548	0	0
T8	211100	1994	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	17610	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	2226334	0	0
T1	21973	832	0	0
T2	814305	9230	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	3640	0	0
T6	587066	0	0	0
T7	543113	1548	0	0
T8	211100	1994	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	17610	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	2226334	0	0
T1	21973	832	0	0
T2	814305	9230	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	3640	0	0
T6	587066	0	0	0
T7	543113	1548	0	0
T8	211100	1994	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	17610	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	2226334	0	0
T1	21973	832	0	0
T2	814305	9230	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	3640	0	0
T6	587066	0	0	0
T7	543113	1548	0	0
T8	211100	1994	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	17610	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	3	0	976
T18	428444	1	0	1
T33	0	1	0	0
T58	0	1	0	0
T59	321311	0	0	1
T60	1034	0	0	1
T61	10824	0	0	1
T62	397602	0	0	1
T63	124893	0	0	1
T64	79823	0	0	1
T65	100101	0	0	1
T66	1700	0	0	1
T67	303276	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	442000832	0	0
T1	21973	21878	0	0
T2	814305	814299	0	0
T3	54354	54304	0	0
T4	142606	142542	0	0
T5	115730	115680	0	0
T6	587066	587007	0	0
T7	543113	543056	0	0
T8	211100	211036	0	0
T9	6579	6526	0	0
T10	11414	11329	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442088449	2226334	0	0
T1	21973	832	0	0
T2	814305	9230	0	0
T3	54354	832	0	0
T4	142606	832	0	0
T5	115730	3640	0	0
T6	587066	0	0	0
T7	543113	1548	0	0
T8	211100	1994	0	0
T9	6579	832	0	0
T10	11414	832	0	0
T11	0	17610	0	0