Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3240654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3942679

1

T1

8915

T2

1910

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3905188	1			T1	13856		T2	2062		T3	14
values[0x0]	1638233	1			T1	4639		T2	441		T3	2
values[0x1]	1639912	1			T1	4403		T2	451		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2298600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4884733

1

T1

13189

T2

2101

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25883	1			T1	138		T2	16		T4	52
valid_sources[0x01]	35081	1			T2	7		T4	42		T5	23
valid_sources[0x02]	25474	1			T1	1		T2	7		T4	53
valid_sources[0x03]	41248	1			T1	206		T2	13		T4	38
valid_sources[0x04]	24896	1			T1	67		T2	11		T4	56
valid_sources[0x05]	27963	1			T1	3		T2	13		T4	49
valid_sources[0x06]	27645	1			T1	53		T2	12		T4	50
valid_sources[0x07]	25590	1			T1	2		T2	11		T4	40
valid_sources[0x08]	27269	1			T1	209		T2	12		T4	47
valid_sources[0x09]	26591	1			T1	72		T2	11		T4	39
valid_sources[0x0a]	34502	1			T1	8		T2	18		T3	1
valid_sources[0x0b]	28311	1			T1	80		T2	16		T4	40
valid_sources[0x0c]	29581	1			T1	20		T2	7		T4	33
valid_sources[0x0d]	28948	1			T1	26		T2	9		T4	54
valid_sources[0x0e]	28328	1			T1	50		T2	6		T4	51
valid_sources[0x0f]	26879	1			T2	9		T4	38		T5	22
valid_sources[0x10]	27785	1			T1	121		T2	9		T4	52
valid_sources[0x11]	27753	1			T1	3		T2	13		T4	39
valid_sources[0x12]	25928	1			T1	56		T2	10		T4	48
valid_sources[0x13]	28372	1			T1	223		T2	13		T4	48
valid_sources[0x14]	26529	1			T1	40		T2	19		T4	55
valid_sources[0x15]	25891	1			T1	187		T2	7		T4	48
valid_sources[0x16]	27021	1			T1	1		T2	9		T4	42
valid_sources[0x17]	26827	1			T1	37		T2	15		T4	39
valid_sources[0x18]	28484	1			T2	9		T4	49		T5	17
valid_sources[0x19]	27210	1			T1	576		T2	6		T4	44
valid_sources[0x1a]	27697	1			T1	46		T2	12		T4	53
valid_sources[0x1b]	25607	1			T1	61		T2	8		T4	71
valid_sources[0x1c]	28897	1			T2	13		T4	47		T5	24
valid_sources[0x1d]	25174	1			T1	2		T2	10		T4	48
valid_sources[0x1e]	29817	1			T1	46		T2	13		T4	59
valid_sources[0x1f]	36613	1			T1	8		T2	9		T4	58
valid_sources[0x20]	24867	1			T2	13		T4	36		T5	21
valid_sources[0x21]	28161	1			T2	8		T4	56		T5	29
valid_sources[0x22]	24406	1			T1	24		T2	12		T4	58
valid_sources[0x23]	29862	1			T2	10		T4	45		T5	22
valid_sources[0x24]	29467	1			T1	504		T2	6		T4	44
valid_sources[0x25]	28069	1			T2	13		T4	48		T5	31
valid_sources[0x26]	28703	1			T1	2		T2	13		T4	47
valid_sources[0x27]	27951	1			T1	90		T2	15		T4	47
valid_sources[0x28]	28881	1			T1	100		T2	8		T4	38
valid_sources[0x29]	25707	1			T1	440		T2	11		T4	43
valid_sources[0x2a]	26450	1			T1	423		T2	11		T4	53
valid_sources[0x2b]	26361	1			T1	223		T2	9		T4	41
valid_sources[0x2c]	30208	1			T1	22		T2	7		T4	50
valid_sources[0x2d]	27898	1			T1	3		T2	18		T4	34
valid_sources[0x2e]	28466	1			T1	129		T2	15		T4	51
valid_sources[0x2f]	27031	1			T1	1		T2	13		T4	49
valid_sources[0x30]	27722	1			T1	23		T2	11		T4	40
valid_sources[0x31]	27495	1			T1	540		T2	11		T4	46
valid_sources[0x32]	27075	1			T1	2		T2	18		T4	39
valid_sources[0x33]	25181	1			T1	47		T2	13		T4	48
valid_sources[0x34]	30613	1			T2	10		T4	51		T5	26
valid_sources[0x35]	27370	1			T1	534		T2	9		T4	24
valid_sources[0x36]	25489	1			T1	61		T2	17		T4	61
valid_sources[0x37]	28003	1			T1	967		T2	6		T4	49
valid_sources[0x38]	24980	1			T1	1		T2	11		T4	47
valid_sources[0x39]	35008	1			T1	93		T2	11		T4	48
valid_sources[0x3a]	29641	1			T1	3		T2	15		T4	46
valid_sources[0x3b]	26580	1			T2	13		T4	37		T5	27
valid_sources[0x3c]	27374	1			T1	110		T2	5		T4	40
valid_sources[0x3d]	28619	1			T1	286		T2	17		T3	1
valid_sources[0x3e]	27869	1			T1	71		T2	11		T4	50
valid_sources[0x3f]	24922	1			T1	61		T2	14		T4	48
valid_sources[0x40]	28622	1			T1	3		T2	10		T4	41
valid_sources[0x41]	26556	1			T1	101		T2	14		T4	49
valid_sources[0x42]	29914	1			T1	4		T2	10		T4	56
valid_sources[0x43]	27917	1			T2	16		T4	39		T5	26
valid_sources[0x44]	29409	1			T1	321		T2	17		T4	43
valid_sources[0x45]	29248	1			T1	1		T2	9		T4	48
valid_sources[0x46]	25767	1			T1	4		T2	15		T4	40
valid_sources[0x47]	25794	1			T2	14		T4	46		T5	31
valid_sources[0x48]	32175	1			T2	11		T3	1		T4	59
valid_sources[0x49]	32405	1			T2	14		T4	54		T5	23
valid_sources[0x4a]	26036	1			T1	11		T2	9		T4	45
valid_sources[0x4b]	27967	1			T1	527		T2	9		T4	41
valid_sources[0x4c]	28073	1			T1	4		T2	14		T4	38
valid_sources[0x4d]	27341	1			T1	46		T2	6		T4	40
valid_sources[0x4e]	26155	1			T2	11		T4	46		T5	17
valid_sources[0x4f]	30529	1			T1	24		T2	16		T4	44
valid_sources[0x50]	25228	1			T1	128		T2	17		T4	33
valid_sources[0x51]	27845	1			T1	33		T2	10		T4	45
valid_sources[0x52]	29896	1			T1	69		T2	12		T4	36
valid_sources[0x53]	26823	1			T1	1		T2	12		T4	39
valid_sources[0x54]	27605	1			T1	140		T2	7		T4	31
valid_sources[0x55]	28425	1			T1	718		T2	13		T4	50
valid_sources[0x56]	26704	1			T1	676		T2	12		T4	50
valid_sources[0x57]	27513	1			T1	77		T2	9		T4	46
valid_sources[0x58]	27936	1			T1	59		T2	10		T4	43
valid_sources[0x59]	28792	1			T1	86		T2	16		T3	1
valid_sources[0x5a]	25827	1			T1	13		T2	14		T4	54
valid_sources[0x5b]	30070	1			T1	27		T2	15		T4	35
valid_sources[0x5c]	25500	1			T1	164		T2	9		T3	4
valid_sources[0x5d]	28386	1			T1	36		T2	11		T4	43
valid_sources[0x5e]	28126	1			T1	40		T2	8		T4	57
valid_sources[0x5f]	28547	1			T1	8		T2	7		T4	43
valid_sources[0x60]	30743	1			T1	132		T2	11		T4	57
valid_sources[0x61]	29049	1			T1	1		T2	8		T4	44
valid_sources[0x62]	27437	1			T1	32		T2	16		T4	41
valid_sources[0x63]	25931	1			T1	108		T2	9		T4	29
valid_sources[0x64]	26842	1			T2	13		T4	51		T5	2
valid_sources[0x65]	25607	1			T1	2		T2	17		T4	36
valid_sources[0x66]	25140	1			T2	7		T3	1		T4	46
valid_sources[0x67]	27211	1			T1	1		T2	12		T4	33
valid_sources[0x68]	26341	1			T2	9		T4	38		T5	21
valid_sources[0x69]	25491	1			T2	14		T4	43		T5	39
valid_sources[0x6a]	25842	1			T1	4		T2	11		T4	53
valid_sources[0x6b]	27591	1			T2	11		T4	37		T5	26
valid_sources[0x6c]	27816	1			T1	2		T2	15		T4	69
valid_sources[0x6d]	27123	1			T1	1		T2	8		T4	37
valid_sources[0x6e]	26763	1			T1	26		T2	7		T4	38
valid_sources[0x6f]	29390	1			T2	14		T4	52		T5	11
valid_sources[0x70]	27017	1			T1	1		T2	10		T4	45
valid_sources[0x71]	26653	1			T1	150		T2	8		T4	42
valid_sources[0x72]	24853	1			T1	10		T2	12		T4	31
valid_sources[0x73]	25946	1			T1	13		T2	6		T4	33
valid_sources[0x74]	33045	1			T2	11		T3	1		T4	22
valid_sources[0x75]	26235	1			T1	281		T2	16		T4	42
valid_sources[0x76]	26831	1			T2	13		T4	39		T5	30
valid_sources[0x77]	29223	1			T1	62		T2	16		T4	43
valid_sources[0x78]	29401	1			T1	261		T2	14		T4	34
valid_sources[0x79]	26689	1			T1	108		T2	10		T4	50
valid_sources[0x7a]	32856	1			T1	160		T2	12		T4	54
valid_sources[0x7b]	27960	1			T1	4		T2	11		T4	50
valid_sources[0x7c]	25223	1			T1	230		T2	10		T4	47
valid_sources[0x7d]	30270	1			T1	90		T2	21		T4	50
valid_sources[0x7e]	28750	1			T1	100		T2	10		T4	47
valid_sources[0x7f]	29748	1			T1	34		T2	11		T4	61
valid_sources[0x80]	27889	1			T1	1		T2	19		T4	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

964539

1

T1

1771

T2

1020

T3

3

values[0x0]

all_enables

biggest_size

1499941

1

T1

3749

T2

440

T4

3100

values[0x1]

all_enables

biggest_size

1478199

1

T1

3395

T2

450

T3

1