Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3262698

1

T1

13983

T2

1044

T3

14

full_word

3941935

1

T1

8915

T2

1910

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7204223	1			T1	22898		T2	2954		T3	18
auto[TlIntgErrCmd]	137	1			T98	12		T101	2		T102	5
auto[TlIntgErrData]	147	1			T98	7		T101	5		T102	4
auto[TlIntgErrBoth]	126	1			T98	11		T101	3		T102	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3908059

1

T1

13856

T2

2062

T3

14

auto[1]

3296574

1

T1

9042

T2

892

T3

4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2943139	1			T1	12085		T2	1042		T3	11
auto[TlIntgErrNone]	partial	auto[1]	319186	1			T1	1898		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	964720	1			T1	1771		T2	1020		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	2977178	1			T1	7144		T2	890		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	67	1			T98	5		T101	1		T102	5
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T98	7		T101	1		T115	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T181	1		T182	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T183	1		T184	1		T181	1
auto[TlIntgErrData]	partial	auto[0]	69	1			T98	4		T101	2		T102	3
auto[TlIntgErrData]	partial	auto[1]	64	1			T98	1		T101	3		T102	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T185	1		T171	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T98	2		T184	1		T186	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T98	9		T115	1		T177	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T98	2		T101	1		T102	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T101	1		T181	1		T187	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T101	1		T185	2		T171	3