Group : spi_device_env_pkg::busy_blocks_command_cg
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Group : spi_device_env_pkg::busy_blocks_command_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
spi_device_env_pkg.en4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.ex4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.upload_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wrdi_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wren_block_cmd_cg 100.00 1 100 1 64 64




Group Instance : spi_device_env_pkg.en4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.en4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.en4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.ex4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.upload_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.upload_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.upload_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wrdi_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wren_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wren_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wren_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 24 1 T24 1 T48 1 T164 2
allowed 1436 1 T1 4 T4 8 T8 13


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 39 1 T164 1 T94 1 T188 1
allowed 1423 1 T1 1 T4 5 T8 4


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 221 1 T53 3 T43 2 T48 2
allowed 4710 1 T1 4 T4 14 T8 28


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 45 1 T48 3 T164 1 T94 1
allowed 1447 1 T4 6 T8 10 T11 12


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 31 1 T43 1 T47 1 T94 1
allowed 1423 1 T1 4 T4 2 T8 13

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