Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401430123	2747560	0	0
DepthKnown_A	401430123	401291571	0	0
RvalidKnown_A	401430123	401291571	0	0
WreadyKnown_A	401430123	401291571	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	2747560	0	0
T1	101147	3326	0	0
T2	64513	832	0	0
T3	988	0	0	0
T4	384827	9979	0	0
T5	240569	832	0	0
T6	40915	1663	0	0
T7	778546	0	0	0
T8	966055	17464	0	0
T9	6991	832	0	0
T10	917093	0	0	0
T11	0	14970	0	0
T12	0	832	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401430123	2959156	0	0
DepthKnown_A	401430123	401291571	0	0
RvalidKnown_A	401430123	401291571	0	0
WreadyKnown_A	401430123	401291571	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	2959156	0	0
T1	101147	1664	0	0
T2	64513	3688	0	0
T3	988	0	0	0
T4	384827	5824	0	0
T5	240569	3848	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	10816	0	0
T9	6991	832	0	0
T10	917093	0	0	0
T11	0	9984	0	0
T12	0	3746	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401430123	184882	0	0
DepthKnown_A	401430123	401291571	0	0
RvalidKnown_A	401430123	401291571	0	0
WreadyKnown_A	401430123	401291571	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	184882	0	0
T1	101147	1102	0	0
T2	64513	0	0	0
T3	988	0	0	0
T4	384827	129	0	0
T5	240569	0	0	0
T6	40915	0	0	0
T7	778546	0	0	0
T8	966055	366	0	0
T9	6991	0	0	0
T10	917093	921	0	0
T11	0	358	0	0
T15	0	2985	0	0
T24	0	129	0	0
T27	0	130	0	0
T30	0	747	0	0
T31	0	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401430123	415472	0	0
DepthKnown_A	401430123	401291571	0	0
RvalidKnown_A	401430123	401291571	0	0
WreadyKnown_A	401430123	401291571	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	415472	0	0
T1	101147	1102	0	0
T2	64513	0	0	0
T3	988	0	0	0
T4	384827	129	0	0
T5	240569	0	0	0
T6	40915	0	0	0
T7	778546	0	0	0
T8	966055	366	0	0
T9	6991	0	0	0
T10	917093	921	0	0
T11	0	358	0	0
T15	0	13673	0	0
T24	0	129	0	0
T27	0	130	0	0
T30	0	3275	0	0
T31	0	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401430123	5672844	0	0
DepthKnown_A	401430123	401291571	0	0
RvalidKnown_A	401430123	401291571	0	0
WreadyKnown_A	401430123	401291571	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	5672844	0	0
T1	101147	20230	0	0
T2	64513	2122	0	0
T3	988	18	0	0
T4	384827	5896	0	0
T5	240569	6211	0	0
T6	40915	1090	0	0
T7	778546	803	0	0
T8	966055	6223	0	0
T9	6991	50	0	0
T10	917093	16293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401430123	12560374	0	0
DepthKnown_A	401430123	401291571	0	0
RvalidKnown_A	401430123	401291571	0	0
WreadyKnown_A	401430123	401291571	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	12560374	0	0
T1	101147	20132	0	0
T2	64513	9191	0	0
T3	988	18	0	0
T4	384827	5892	0	0
T5	240569	26945	0	0
T6	40915	4551	0	0
T7	778546	803	0	0
T8	966055	6188	0	0
T9	6991	50	0	0
T10	917093	16223	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401430123	401291571	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0