Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	677230267	536732317	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	677230267	3524164	0	0
GntImpliesValid_A	677230267	3524164	0	0
GrantKnown_A	677230267	536732317	0	0
IdxKnown_A	677230267	536732317	0	0
IndexIsCorrect_A	677230267	3524164	0	0
LockArbDecision_A	677230267	0	0	0
NoReadyValidNoGrant_A	677230267	0	0	0
ReadyAndValidImplyGrant_A	677230267	3524164	0	0
ReqAndReadyImplyGrant_A	677230267	3524164	0	0
ReqImpliesValid_A	677230267	3524164	0	0
ReqStaysHighUntilGranted0_M	677230267	0	0	0
RoundRobin_A	677230267	2	0	976
ValidKnown_A	677230267	536732317	0	0
gen_data_port_assertion.DataFlow_A	677230267	3524164	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	536732317	0	0
T1	771181	429936	0	0
T2	118241	91311	0	0
T3	1196	1030	0	0
T4	1337669	860116	0	0
T5	353657	296601	0	0
T6	59595	50171	0	0
T7	975142	874286	0	0
T8	1868239	1413474	0	0
T9	6991	6899	0	0
T10	1178163	1043939	0	0
T11	875416	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	3524164	0	0
T1	771181	10641	0	0
T2	118241	832	0	0
T3	1196	3	0	0
T4	1337669	9232	0	0
T5	353657	832	0	0
T6	59595	832	0	0
T7	975142	0	0	0
T8	1868239	16058	0	0
T9	6991	832	0	0
T10	1178163	8631	0	0
T11	875416	12074	0	0
T15	0	20928	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T43	0	2423	0	0
T53	0	4972	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	3524164	0	0
T1	771181	10641	0	0
T2	118241	832	0	0
T3	1196	3	0	0
T4	1337669	9232	0	0
T5	353657	832	0	0
T6	59595	832	0	0
T7	975142	0	0	0
T8	1868239	16058	0	0
T9	6991	832	0	0
T10	1178163	8631	0	0
T11	875416	12074	0	0
T15	0	20928	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T43	0	2423	0	0
T53	0	4972	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	536732317	0	0
T1	771181	429936	0	0
T2	118241	91311	0	0
T3	1196	1030	0	0
T4	1337669	860116	0	0
T5	353657	296601	0	0
T6	59595	50171	0	0
T7	975142	874286	0	0
T8	1868239	1413474	0	0
T9	6991	6899	0	0
T10	1178163	1043939	0	0
T11	875416	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	536732317	0	0
T1	771181	429936	0	0
T2	118241	91311	0	0
T3	1196	1030	0	0
T4	1337669	860116	0	0
T5	353657	296601	0	0
T6	59595	50171	0	0
T7	975142	874286	0	0
T8	1868239	1413474	0	0
T9	6991	6899	0	0
T10	1178163	1043939	0	0
T11	875416	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	3524164	0	0
T1	771181	10641	0	0
T2	118241	832	0	0
T3	1196	3	0	0
T4	1337669	9232	0	0
T5	353657	832	0	0
T6	59595	832	0	0
T7	975142	0	0	0
T8	1868239	16058	0	0
T9	6991	832	0	0
T10	1178163	8631	0	0
T11	875416	12074	0	0
T15	0	20928	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T43	0	2423	0	0
T53	0	4972	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	3524164	0	0
T1	771181	10641	0	0
T2	118241	832	0	0
T3	1196	3	0	0
T4	1337669	9232	0	0
T5	353657	832	0	0
T6	59595	832	0	0
T7	975142	0	0	0
T8	1868239	16058	0	0
T9	6991	832	0	0
T10	1178163	8631	0	0
T11	875416	12074	0	0
T15	0	20928	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T43	0	2423	0	0
T53	0	4972	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	3524164	0	0
T1	771181	10641	0	0
T2	118241	832	0	0
T3	1196	3	0	0
T4	1337669	9232	0	0
T5	353657	832	0	0
T6	59595	832	0	0
T7	975142	0	0	0
T8	1868239	16058	0	0
T9	6991	832	0	0
T10	1178163	8631	0	0
T11	875416	12074	0	0
T15	0	20928	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T43	0	2423	0	0
T53	0	4972	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	3524164	0	0
T1	771181	10641	0	0
T2	118241	832	0	0
T3	1196	3	0	0
T4	1337669	9232	0	0
T5	353657	832	0	0
T6	59595	832	0	0
T7	975142	0	0	0
T8	1868239	16058	0	0
T9	6991	832	0	0
T10	1178163	8631	0	0
T11	875416	12074	0	0
T15	0	20928	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T43	0	2423	0	0
T53	0	4972	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	2	0	976
T54	244336	1	0	1
T55	0	1	0	0
T56	393843	0	0	1
T57	450720	0	0	1
T58	28246	0	0	1
T59	63627	0	0	1
T60	557950	0	0	1
T61	5187	0	0	1
T62	65127	0	0	1
T63	49951	0	0	1
T64	191003	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	536732317	0	0
T1	771181	429936	0	0
T2	118241	91311	0	0
T3	1196	1030	0	0
T4	1337669	860116	0	0
T5	353657	296601	0	0
T6	59595	50171	0	0
T7	975142	874286	0	0
T8	1868239	1413474	0	0
T9	6991	6899	0	0
T10	1178163	1043939	0	0
T11	875416	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677230267	3524164	0	0
T1	771181	10641	0	0
T2	118241	832	0	0
T3	1196	3	0	0
T4	1337669	9232	0	0
T5	353657	832	0	0
T6	59595	832	0	0
T7	975142	0	0	0
T8	1868239	16058	0	0
T9	6991	832	0	0
T10	1178163	8631	0	0
T11	875416	12074	0	0
T15	0	20928	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T43	0	2423	0	0
T53	0	4972	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	139121571	27489836	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	139121571	614878	0	0
GntImpliesValid_A	139121571	614878	0	0
GrantKnown_A	139121571	27489836	0	0
IdxKnown_A	139121571	27489836	0	0
IndexIsCorrect_A	139121571	614878	0	0
LockArbDecision_A	139121571	0	0	0
NoReadyValidNoGrant_A	139121571	0	0	0
ReadyAndValidImplyGrant_A	139121571	614878	0	0
ReqAndReadyImplyGrant_A	139121571	614878	0	0
ReqImpliesValid_A	139121571	614878	0	0
ReqStaysHighUntilGranted0_M	139121571	0	0	0
RoundRobin_A	139121571	0	0	0
ValidKnown_A	139121571	27489836	0	0
gen_data_port_assertion.DataFlow_A	139121571	614878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	27489836	0	0
T1	335017	150312	0	0
T2	26864	0	0	0
T3	104	104	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	95816	0	0
T8	451092	24920	0	0
T10	130535	126896	0	0
T11	437708	0	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	614878	0	0
T1	335017	5882	0	0
T2	26864	0	0	0
T3	104	2	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	614	0	0
T10	130535	5741	0	0
T11	437708	0	0	0
T15	0	9130	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T53	0	4970	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	614878	0	0
T1	335017	5882	0	0
T2	26864	0	0	0
T3	104	2	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	614	0	0
T10	130535	5741	0	0
T11	437708	0	0	0
T15	0	9130	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T53	0	4970	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	27489836	0	0
T1	335017	150312	0	0
T2	26864	0	0	0
T3	104	104	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	95816	0	0
T8	451092	24920	0	0
T10	130535	126896	0	0
T11	437708	0	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	27489836	0	0
T1	335017	150312	0	0
T2	26864	0	0	0
T3	104	104	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	95816	0	0
T8	451092	24920	0	0
T10	130535	126896	0	0
T11	437708	0	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	614878	0	0
T1	335017	5882	0	0
T2	26864	0	0	0
T3	104	2	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	614	0	0
T10	130535	5741	0	0
T11	437708	0	0	0
T15	0	9130	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T53	0	4970	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	614878	0	0
T1	335017	5882	0	0
T2	26864	0	0	0
T3	104	2	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	614	0	0
T10	130535	5741	0	0
T11	437708	0	0	0
T15	0	9130	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T53	0	4970	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	614878	0	0
T1	335017	5882	0	0
T2	26864	0	0	0
T3	104	2	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	614	0	0
T10	130535	5741	0	0
T11	437708	0	0	0
T15	0	9130	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T53	0	4970	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	614878	0	0
T1	335017	5882	0	0
T2	26864	0	0	0
T3	104	2	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	614	0	0
T10	130535	5741	0	0
T11	437708	0	0	0
T15	0	9130	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T53	0	4970	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	27489836	0	0
T1	335017	150312	0	0
T2	26864	0	0	0
T3	104	104	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	95816	0	0
T8	451092	24920	0	0
T10	130535	126896	0	0
T11	437708	0	0	0
T15	0	217095	0	0
T29	0	112200	0	0
T30	0	93568	0	0
T31	0	46656	0	0
T33	0	88	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	614878	0	0
T1	335017	5882	0	0
T2	26864	0	0	0
T3	104	2	0	0
T4	476421	0	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	614	0	0
T10	130535	5741	0	0
T11	437708	0	0	0
T15	0	9130	0	0
T30	0	4447	0	0
T31	0	2132	0	0
T33	0	2	0	0
T42	0	126	0	0
T53	0	4970	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	139121571	110347681	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	139121571	751175	0	0
GntImpliesValid_A	139121571	751175	0	0
GrantKnown_A	139121571	110347681	0	0
IdxKnown_A	139121571	110347681	0	0
IndexIsCorrect_A	139121571	751175	0	0
LockArbDecision_A	139121571	0	0	0
NoReadyValidNoGrant_A	139121571	0	0	0
ReadyAndValidImplyGrant_A	139121571	751175	0	0
ReqAndReadyImplyGrant_A	139121571	751175	0	0
ReqImpliesValid_A	139121571	751175	0	0
ReqStaysHighUntilGranted0_M	139121571	0	0	0
RoundRobin_A	139121571	0	0	0
ValidKnown_A	139121571	110347681	0	0
gen_data_port_assertion.DataFlow_A	139121571	751175	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	110347681	0	0
T1	335017	178483	0	0
T2	26864	26864	0	0
T3	104	0	0	0
T4	476421	475295	0	0
T5	56544	56096	0	0
T6	9340	9340	0	0
T7	98298	0	0	0
T8	451092	422556	0	0
T10	130535	0	0	0
T11	437708	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	751175	0	0
T1	335017	265	0	0
T2	26864	0	0	0
T3	104	0	0	0
T4	476421	3267	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	3978	0	0
T10	130535	0	0	0
T11	437708	1714	0	0
T15	0	11798	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T43	0	2423	0	0
T53	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	751175	0	0
T1	335017	265	0	0
T2	26864	0	0	0
T3	104	0	0	0
T4	476421	3267	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	3978	0	0
T10	130535	0	0	0
T11	437708	1714	0	0
T15	0	11798	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T43	0	2423	0	0
T53	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	110347681	0	0
T1	335017	178483	0	0
T2	26864	26864	0	0
T3	104	0	0	0
T4	476421	475295	0	0
T5	56544	56096	0	0
T6	9340	9340	0	0
T7	98298	0	0	0
T8	451092	422556	0	0
T10	130535	0	0	0
T11	437708	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	110347681	0	0
T1	335017	178483	0	0
T2	26864	26864	0	0
T3	104	0	0	0
T4	476421	475295	0	0
T5	56544	56096	0	0
T6	9340	9340	0	0
T7	98298	0	0	0
T8	451092	422556	0	0
T10	130535	0	0	0
T11	437708	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	751175	0	0
T1	335017	265	0	0
T2	26864	0	0	0
T3	104	0	0	0
T4	476421	3267	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	3978	0	0
T10	130535	0	0	0
T11	437708	1714	0	0
T15	0	11798	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T43	0	2423	0	0
T53	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	751175	0	0
T1	335017	265	0	0
T2	26864	0	0	0
T3	104	0	0	0
T4	476421	3267	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	3978	0	0
T10	130535	0	0	0
T11	437708	1714	0	0
T15	0	11798	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T43	0	2423	0	0
T53	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	751175	0	0
T1	335017	265	0	0
T2	26864	0	0	0
T3	104	0	0	0
T4	476421	3267	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	3978	0	0
T10	130535	0	0	0
T11	437708	1714	0	0
T15	0	11798	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T43	0	2423	0	0
T53	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	751175	0	0
T1	335017	265	0	0
T2	26864	0	0	0
T3	104	0	0	0
T4	476421	3267	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	3978	0	0
T10	130535	0	0	0
T11	437708	1714	0	0
T15	0	11798	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T43	0	2423	0	0
T53	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	110347681	0	0
T1	335017	178483	0	0
T2	26864	26864	0	0
T3	104	0	0	0
T4	476421	475295	0	0
T5	56544	56096	0	0
T6	9340	9340	0	0
T7	98298	0	0	0
T8	451092	422556	0	0
T10	130535	0	0	0
T11	437708	435175	0	0
T12	0	96294	0	0
T13	0	75624	0	0
T14	0	54053	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139121571	751175	0	0
T1	335017	265	0	0
T2	26864	0	0	0
T3	104	0	0	0
T4	476421	3267	0	0
T5	56544	0	0	0
T6	9340	0	0	0
T7	98298	0	0	0
T8	451092	3978	0	0
T10	130535	0	0	0
T11	437708	1714	0	0
T15	0	11798	0	0
T16	0	6843	0	0
T24	0	1532	0	0
T27	0	755	0	0
T43	0	2423	0	0
T53	0	2	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398987125	398894800	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	398987125	2158111	0	0
GntImpliesValid_A	398987125	2158111	0	0
GrantKnown_A	398987125	398894800	0	0
IdxKnown_A	398987125	398894800	0	0
IndexIsCorrect_A	398987125	2158111	0	0
LockArbDecision_A	398987125	0	0	0
NoReadyValidNoGrant_A	398987125	0	0	0
ReadyAndValidImplyGrant_A	398987125	2158111	0	0
ReqAndReadyImplyGrant_A	398987125	2158111	0	0
ReqImpliesValid_A	398987125	2158111	0	0
ReqStaysHighUntilGranted0_M	398987125	0	0	0
RoundRobin_A	398987125	2	0	976
ValidKnown_A	398987125	398894800	0	0
gen_data_port_assertion.DataFlow_A	398987125	2158111	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	398894800	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2158111	0	0
T1	101147	4494	0	0
T2	64513	832	0	0
T3	988	1	0	0
T4	384827	5965	0	0
T5	240569	832	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	11466	0	0
T9	6991	832	0	0
T10	917093	2890	0	0
T11	0	10360	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2158111	0	0
T1	101147	4494	0	0
T2	64513	832	0	0
T3	988	1	0	0
T4	384827	5965	0	0
T5	240569	832	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	11466	0	0
T9	6991	832	0	0
T10	917093	2890	0	0
T11	0	10360	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	398894800	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	398894800	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2158111	0	0
T1	101147	4494	0	0
T2	64513	832	0	0
T3	988	1	0	0
T4	384827	5965	0	0
T5	240569	832	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	11466	0	0
T9	6991	832	0	0
T10	917093	2890	0	0
T11	0	10360	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2158111	0	0
T1	101147	4494	0	0
T2	64513	832	0	0
T3	988	1	0	0
T4	384827	5965	0	0
T5	240569	832	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	11466	0	0
T9	6991	832	0	0
T10	917093	2890	0	0
T11	0	10360	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2158111	0	0
T1	101147	4494	0	0
T2	64513	832	0	0
T3	988	1	0	0
T4	384827	5965	0	0
T5	240569	832	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	11466	0	0
T9	6991	832	0	0
T10	917093	2890	0	0
T11	0	10360	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2158111	0	0
T1	101147	4494	0	0
T2	64513	832	0	0
T3	988	1	0	0
T4	384827	5965	0	0
T5	240569	832	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	11466	0	0
T9	6991	832	0	0
T10	917093	2890	0	0
T11	0	10360	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2	0	976
T54	244336	1	0	1
T55	0	1	0	0
T56	393843	0	0	1
T57	450720	0	0	1
T58	28246	0	0	1
T59	63627	0	0	1
T60	557950	0	0	1
T61	5187	0	0	1
T62	65127	0	0	1
T63	49951	0	0	1
T64	191003	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	398894800	0	0
T1	101147	101141	0	0
T2	64513	64447	0	0
T3	988	926	0	0
T4	384827	384821	0	0
T5	240569	240505	0	0
T6	40915	40831	0	0
T7	778546	778470	0	0
T8	966055	965998	0	0
T9	6991	6899	0	0
T10	917093	917043	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398987125	2158111	0	0
T1	101147	4494	0	0
T2	64513	832	0	0
T3	988	1	0	0
T4	384827	5965	0	0
T5	240569	832	0	0
T6	40915	832	0	0
T7	778546	0	0	0
T8	966055	11466	0	0
T9	6991	832	0	0
T10	917093	2890	0	0
T11	0	10360	0	0