Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2816384	1			T1	136		T2	4073		T4	2956
all_values[1]	2816384	1			T1	136		T2	4073		T4	2956
all_values[2]	2816384	1			T1	136		T2	4073		T4	2956
all_values[3]	2816384	1			T1	136		T2	4073		T4	2956
all_values[4]	2816384	1			T1	136		T2	4073		T4	2956
all_values[5]	2816384	1			T1	136		T2	4073		T4	2956
all_values[6]	2816384	1			T1	136		T2	4073		T4	2956
all_values[7]	2816384	1			T1	136		T2	4073		T4	2956

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21892046

1

T1

1088

T2

32584

T4

23648

auto[1]

639026

1

T14

79

T18

45

T19

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22504333

1

T1

1088

T2

32584

T4

23648

auto[1]

26739

1

T5

272

T14

282

T26

102

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2655566	1			T1	136		T2	4073		T4	2956
all_values[0]	auto[0]	auto[1]	12078	1			T5	111		T14	94		T26	52
all_values[0]	auto[1]	auto[0]	147995	1			T14	7		T18	4		T20	8
all_values[0]	auto[1]	auto[1]	745	1			T14	8		T18	2		T19	4
all_values[1]	auto[0]	auto[0]	2799882	1			T1	136		T2	4073		T4	2956
all_values[1]	auto[0]	auto[1]	8313	1			T5	103		T14	98		T26	38
all_values[1]	auto[1]	auto[0]	7799	1			T14	7		T18	5		T19	1
all_values[1]	auto[1]	auto[1]	390	1			T14	1		T18	3		T19	4
all_values[2]	auto[0]	auto[0]	2736734	1			T1	136		T2	4073		T4	2956
all_values[2]	auto[0]	auto[1]	3096	1			T5	58		T14	31		T26	12
all_values[2]	auto[1]	auto[0]	76159	1			T14	4		T18	7		T19	1
all_values[2]	auto[1]	auto[1]	395	1			T14	5		T18	2		T19	2
all_values[3]	auto[0]	auto[0]	2758980	1			T1	136		T2	4073		T4	2956
all_values[3]	auto[0]	auto[1]	166	1			T14	3		T18	2		T19	1
all_values[3]	auto[1]	auto[0]	57050	1			T14	8		T18	4		T19	1
all_values[3]	auto[1]	auto[1]	188	1			T14	3		T19	4		T20	5
all_values[4]	auto[0]	auto[0]	2746197	1			T1	136		T2	4073		T4	2956
all_values[4]	auto[0]	auto[1]	175	1			T14	7		T18	1		T19	2
all_values[4]	auto[1]	auto[0]	69829	1			T14	4		T18	5		T19	3
all_values[4]	auto[1]	auto[1]	183	1			T14	4		T18	3		T19	3
all_values[5]	auto[0]	auto[0]	2713550	1			T1	136		T2	4073		T4	2956
all_values[5]	auto[0]	auto[1]	168	1			T14	6		T18	1		T19	1
all_values[5]	auto[1]	auto[0]	102504	1			T14	5		T18	3		T19	5
all_values[5]	auto[1]	auto[1]	162	1			T14	4		T19	1		T20	9
all_values[6]	auto[0]	auto[0]	2712944	1			T1	136		T2	4073		T4	2956
all_values[6]	auto[0]	auto[1]	187	1			T14	3		T18	6		T19	3
all_values[6]	auto[1]	auto[0]	103103	1			T14	6		T18	1		T19	2
all_values[6]	auto[1]	auto[1]	150	1			T14	3		T19	3		T20	2
all_values[7]	auto[0]	auto[0]	2743836	1			T1	136		T2	4073		T4	2956
all_values[7]	auto[0]	auto[1]	174	1			T14	8		T19	4		T20	6
all_values[7]	auto[1]	auto[0]	72205	1			T14	6		T18	3		T20	6
all_values[7]	auto[1]	auto[1]	169	1			T14	4		T18	3		T19	2