Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34213	1			T2	297		T5	132		T7	4
auto[SpiFlashAddrCfg]	7433	1			T2	55		T5	37		T7	2
auto[SpiFlashAddr3b]	8978	1			T2	46		T5	35		T14	17
auto[SpiFlashAddr4b]	7655	1			T2	40		T5	37		T7	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31966

1

T2

233

T5

130

T7

10

auto[1]

26313

1

T2

205

T5

111

T14

57

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31613

1

T2

270

T5

123

T7

4

auto[1]

26666

1

T2

168

T5

118

T7

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38879	1			T2	332		T5	158		T7	8
values[1]	1128	1			T2	9		T5	5		T15	4
values[2]	1381	1			T2	4		T5	5		T14	3
values[3]	1404	1			T2	15		T5	3		T14	2
values[4]	1474	1			T2	13		T5	6		T14	2
values[5]	1494	1			T2	2		T5	11		T14	3
values[6]	1412	1			T2	5		T5	9		T14	4
values[7]	1442	1			T2	9		T5	4		T14	7
values[8]	9665	1			T2	49		T5	40		T7	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28008

1

T5

241

T7

10

T13

2

auto[1]

30271

1

T2

438

T16

100

T17

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54971

1

T2

420

T5

223

T7

10

write

3308

1

T2

18

T5

18

T14

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18927

1

T2

109

T5

100

T7

2

valids[0x1]

39352

1

T2

329

T5

141

T7

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1658	1			T2	19		T5	8		T14	5
internal_process_ops[0x5a]	1545	1			T2	9		T5	7		T14	2
internal_process_ops[0x05]	20342	1			T2	189		T5	66		T7	2
internal_process_ops[0x35]	1554	1			T2	8		T5	3		T14	1
internal_process_ops[0x15]	1554	1			T2	11		T5	6		T14	5
internal_process_ops[0x03]	1001	1			T2	4		T5	9		T14	5
internal_process_ops[0x0b]	1013	1			T2	6		T5	3		T7	4
internal_process_ops[0x3b]	965	1			T2	3		T5	9		T14	5
internal_process_ops[0x6b]	1094	1			T2	5		T5	5		T14	3
internal_process_ops[0xbb]	1039	1			T2	1		T5	8		T14	3
internal_process_ops[0xeb]	919	1			T2	2		T5	8		T14	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56635

1

T2

425

T5

234

T7

10

auto[1]

1644

1

T2

13

T5

7

T14

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55888

1

T2

418

T5

230

T7

10

auto[1]

2391

1

T2

20

T5

11

T14

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8950

1

T5

85

T7

4

T13

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6375

1

T5

40

T14

21

T15

108

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1798

1

T5

11

T7

2

T14

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1659

1

T5

22

T14

11

T15

31

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2227

1

T5

8

T14

11

T15

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2001

1

T5

22

T14

6

T15

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1911

1

T5

18

T7

4

T14

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1610

1

T5

17

T14

15

T15

22

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

92

1

T5

2

T29

2

T21

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T5

2

T21

3

T23

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

84

1

T5

1

T15

1

T21

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

111

1

T5

2

T15

1

T25

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

91

1

T5

2

T14

1

T15

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

76

1

T5

1

T14

1

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

87

1

T29

1

T20

3

T21

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T5

1

T15

1

T42

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

123

1

T29

1

T58

1

T21

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T15

4

T29

4

T21

7

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

80

1

T5

4

T15

1

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T5

1

T15

1

T42

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T5

1

T14

1

T15

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

75

1

T21

5

T22

1

T23

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T5

1

T15

4

T21

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T14

4

T15

3

T27

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10070

1

T2

153

T16

27

T26

206

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7957

1

T2

138

T16

14

T26

194

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1607

1

T2

28

T16

9

T17

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1566

1

T2

23

T16

4

T26

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2027

1

T2

25

T16

9

T26

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1896

1

T2

20

T16

9

T26

33

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1699

1

T2

17

T16

4

T17

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1618

1

T2

16

T16

13

T26

19

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

127

1

T44

1

T45

4

T39

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

124

1

T2

4

T16

4

T26

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

125

1

T2

1

T26

3

T44

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T2

1

T20

2

T164

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

109

1

T16

3

T79

1

T23

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

128

1

T2

1

T26

1

T44

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T26

4

T44

5

T39

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T2

3

T26

1

T44

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T2

1

T45

1

T46

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

109

1

T45

1

T39

3

T20

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T26

1

T39

1

T20

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

125

1

T26

2

T44

8

T46

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

121

1

T2

3

T79

1

T165

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

111

1

T2

1

T16

3

T26

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

112

1

T26

1

T44

3

T39

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T2

3

T16

1

T26

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3419	1			T5	40		T7	2		T13	2
auto[0]	values[0]	valids[0x1]	14509	1			T5	118		T7	6		T14	43
auto[0]	values[1]	valids[0x1]	557	1			T5	5		T15	4		T29	5
auto[0]	values[2]	valids[0x0]	504	1			T5	3		T15	2		T29	2
auto[0]	values[2]	valids[0x1]	236	1			T5	2		T14	3		T15	7
auto[0]	values[3]	valids[0x0]	430	1			T5	3		T14	1		T15	3
auto[0]	values[3]	valids[0x1]	260	1			T14	1		T15	4		T29	1
auto[0]	values[4]	valids[0x0]	496	1			T5	5		T14	1		T15	16
auto[0]	values[4]	valids[0x1]	279	1			T5	1		T14	1		T15	3
auto[0]	values[5]	valids[0x0]	504	1			T5	6		T14	3		T15	8
auto[0]	values[5]	valids[0x1]	282	1			T5	5		T15	6		T29	8
auto[0]	values[6]	valids[0x0]	497	1			T5	7		T14	1		T15	4
auto[0]	values[6]	valids[0x1]	275	1			T5	2		T14	3		T15	6
auto[0]	values[7]	valids[0x0]	484	1			T5	4		T14	6		T15	3
auto[0]	values[7]	valids[0x1]	261	1			T14	1		T15	2		T21	6
auto[0]	values[8]	valids[0x0]	3207	1			T5	32		T14	27		T15	49
auto[0]	values[8]	valids[0x1]	1808	1			T5	8		T7	2		T14	7
auto[1]	values[0]	valids[0x0]	4234	1			T2	60		T16	20		T26	74
auto[1]	values[0]	valids[0x1]	16717	1			T2	272		T16	35		T26	369
auto[1]	values[1]	valids[0x1]	571	1			T2	9		T16	1		T26	7
auto[1]	values[2]	valids[0x0]	364	1			T2	3		T16	4		T26	1
auto[1]	values[2]	valids[0x1]	277	1			T2	1		T26	3		T44	4
auto[1]	values[3]	valids[0x0]	410	1			T2	7		T16	4		T26	8
auto[1]	values[3]	valids[0x1]	304	1			T2	8		T16	1		T26	4
auto[1]	values[4]	valids[0x0]	402	1			T2	8		T26	1		T44	6
auto[1]	values[4]	valids[0x1]	297	1			T2	5		T17	2		T26	9
auto[1]	values[5]	valids[0x0]	428	1			T2	2		T26	2		T44	4
auto[1]	values[5]	valids[0x1]	280	1			T16	1		T26	1		T44	6
auto[1]	values[6]	valids[0x0]	399	1			T2	2		T26	3		T44	5
auto[1]	values[6]	valids[0x1]	241	1			T2	3		T16	3		T26	3
auto[1]	values[7]	valids[0x0]	405	1			T2	6		T16	1		T26	4
auto[1]	values[7]	valids[0x1]	292	1			T2	3		T16	2		T26	4
auto[1]	values[8]	valids[0x0]	2744	1			T2	21		T16	7		T17	3
auto[1]	values[8]	valids[0x1]	1906	1			T2	28		T16	21		T26	26