Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3221883

1

T2

8916

T4

1

T5

5694

auto[1]

27713

1

T2

179

T5

61

T14

23

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

910085

1

T2

108

T4

1

T5

67

auto[1]

2339511

1

T2

8987

T5

5688

T7

256

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	644629	1			T2	288		T4	1		T5	3726
auto[524288:1048575]	363085	1			T2	181		T5	513		T14	4
auto[1048576:1572863]	401222	1			T2	3907		T5	19		T13	567
auto[1572864:2097151]	309476	1			T2	736		T5	4		T14	259
auto[2097152:2621439]	367317	1			T2	1		T5	51		T14	265
auto[2621440:3145727]	371906	1			T2	13		T5	669		T13	547
auto[3145728:3670015]	411157	1			T2	1331		T5	772		T14	3
auto[3670016:4194303]	380804	1			T2	2638		T5	1		T13	575

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2375630

1

T2

9071

T4

1

T5

5755

auto[1]

873966

1

T2

24

T13

1753

T15

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2762228

1

T2

5371

T4

1

T5

5749

auto[1]

487368

1

T2

3724

T5

6

T14

1456

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	203580	1			T2	4		T4	1		T5	13
auto[0]	auto[0]	auto[0:524287]	auto[1]	378606	1			T2	259		T5	3704		T7	256
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	109987	1			T2	7		T5	1		T14	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	184490	1			T2	30		T5	512		T15	2038
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	118893	1			T2	3		T5	4		T13	567
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	217984	1			T2	770		T5	2		T14	3020
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	68351	1			T2	8		T5	1		T14	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	178464	1			T2	648		T5	3		T14	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	92346	1			T2	1		T5	13		T14	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	222565	1			T5	4		T14	256		T15	4407
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	83028	1			T2	2		T5	13		T13	547
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	227965	1			T2	1		T5	645		T15	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	131812	1			T2	15		T5	4		T14	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	216017	1			T2	897		T5	768		T15	263
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	86825	1			T2	13		T5	1		T13	575
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	218651	1			T2	2619		T14	1		T15	5560
auto[0]	auto[1]	auto[0:524287]	auto[0]	1730	1			T2	1		T5	3		T15	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	56595	1			T2	1		T15	2		T29	515
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2222	1			T2	4		T14	2		T15	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	63982	1			T2	134		T15	1		T26	715
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1014	1			T2	10		T14	2		T16	14
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	60077	1			T2	3083		T14	1		T26	380
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	656	1			T2	3		T15	1		T26	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	58014	1			T2	1		T26	259		T29	1057
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2273	1			T5	2		T14	1		T15	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46459	1			T14	1		T15	512		T26	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	895	1			T2	3		T5	1		T14	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	57000	1			T16	1		T29	512		T39	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	670	1			T2	13		T16	15		T26	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58617	1			T2	386		T16	256		T26	259
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2020	1			T14	1		T16	2		T26	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	70095	1			T14	1437		T26	1939		T39	4348
auto[1]	auto[0]	auto[0:524287]	auto[0]	490	1			T5	2		T15	2		T16	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	2797	1			T5	4		T15	3		T44	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	249	1			T2	1		T15	1		T26	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1634	1			T2	1		T15	13		T26	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	415	1			T2	2		T5	2		T14	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2252	1			T2	9		T5	11		T14	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	382	1			T2	5		T15	4		T16	9
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3208	1			T2	58		T15	19		T26	33
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	361	1			T5	4		T29	3		T39	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2580	1			T5	28		T29	19		T39	28
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	321	1			T2	2		T5	3		T15	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2052	1			T2	5		T5	7		T15	41
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	338	1			T2	1		T15	1		T16	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2819	1			T2	4		T15	40		T29	13
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	475	1			T2	2		T14	1		T16	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2291	1			T2	4		T14	4		T26	25
auto[1]	auto[1]	auto[0:524287]	auto[0]	129	1			T2	1		T15	1		T23	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	702	1			T2	22		T15	18		T23	28
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	82	1			T2	1		T15	1		T44	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	439	1			T2	3		T15	56		T44	10
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	85	1			T2	3		T14	1		T45	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	502	1			T2	27		T14	3		T45	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	99	1			T2	1		T26	3		T20	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	302	1			T2	12		T26	3		T20	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	76	1			T14	1		T26	3		T20	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	657	1			T14	5		T26	124		T21	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	101	1			T39	1		T79	2		T96	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	544	1			T39	3		T79	25		T165	73
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	109	1			T2	2		T26	3		T29	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	775	1			T2	13		T26	83		T29	23
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	71	1			T39	1		T164	1		T165	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	376	1			T39	10		T164	3		T165	37

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1872468	1			T2	5271		T4	1		T5	5688
auto[0]	auto[0]	auto[1]	867096	1			T2	6		T13	1753		T15	5
auto[0]	auto[1]	auto[0]	476159	1			T2	3633		T5	6		T14	1446
auto[0]	auto[1]	auto[1]	6160	1			T2	6		T26	2		T29	1
auto[1]	auto[0]	auto[0]	22101	1			T2	85		T5	61		T14	13
auto[1]	auto[0]	auto[1]	563	1			T2	9		T15	1		T16	4
auto[1]	auto[1]	auto[0]	4902	1			T2	82		T14	10		T15	76
auto[1]	auto[1]	auto[1]	147	1			T2	3		T26	4		T29	2