Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2816384	1			T1	136		T2	4073		T4	2956
all_pins[1]	2816384	1			T1	136		T2	4073		T4	2956
all_pins[2]	2816384	1			T1	136		T2	4073		T4	2956
all_pins[3]	2816384	1			T1	136		T2	4073		T4	2956
all_pins[4]	2816384	1			T1	136		T2	4073		T4	2956
all_pins[5]	2816384	1			T1	136		T2	4073		T4	2956
all_pins[6]	2816384	1			T1	136		T2	4073		T4	2956
all_pins[7]	2816384	1			T1	136		T2	4073		T4	2956

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22423963	1			T1	1088		T2	32584		T4	23648
values[0x1]	107109	1			T14	32		T18	13		T19	23
transitions[0x0=>0x1]	105078	1			T14	23		T18	11		T19	19
transitions[0x1=>0x0]	105090	1			T14	23		T18	11		T19	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2815571	1			T1	136		T2	4073		T4	2956
all_pins[0]	values[0x1]	813	1			T14	8		T18	2		T19	4
all_pins[0]	transitions[0x0=>0x1]	688	1			T14	8		T18	2		T19	3
all_pins[0]	transitions[0x1=>0x0]	304	1			T14	1		T18	3		T19	3
all_pins[1]	values[0x0]	2815955	1			T1	136		T2	4073		T4	2956
all_pins[1]	values[0x1]	429	1			T14	1		T18	3		T19	4
all_pins[1]	transitions[0x0=>0x1]	294	1			T14	1		T18	1		T19	4
all_pins[1]	transitions[0x1=>0x0]	286	1			T14	5		T19	2		T20	4
all_pins[2]	values[0x0]	2815963	1			T1	136		T2	4073		T4	2956
all_pins[2]	values[0x1]	421	1			T14	5		T18	2		T19	2
all_pins[2]	transitions[0x0=>0x1]	376	1			T14	3		T18	2		T19	2
all_pins[2]	transitions[0x1=>0x0]	143	1			T14	1		T19	4		T20	5
all_pins[3]	values[0x0]	2816196	1			T1	136		T2	4073		T4	2956
all_pins[3]	values[0x1]	188	1			T14	3		T19	4		T20	5
all_pins[3]	transitions[0x0=>0x1]	148	1			T14	3		T19	2		T20	5
all_pins[3]	transitions[0x1=>0x0]	143	1			T14	4		T18	3		T19	1
all_pins[4]	values[0x0]	2816201	1			T1	136		T2	4073		T4	2956
all_pins[4]	values[0x1]	183	1			T14	4		T18	3		T19	3
all_pins[4]	transitions[0x0=>0x1]	144	1			T14	3		T18	3		T19	3
all_pins[4]	transitions[0x1=>0x0]	2013	1			T14	3		T19	1		T20	7
all_pins[5]	values[0x0]	2814332	1			T1	136		T2	4073		T4	2956
all_pins[5]	values[0x1]	2052	1			T14	4		T19	1		T20	9
all_pins[5]	transitions[0x0=>0x1]	490	1			T14	3		T19	1		T20	9
all_pins[5]	transitions[0x1=>0x0]	101292	1			T14	2		T19	3		T20	2
all_pins[6]	values[0x0]	2713530	1			T1	136		T2	4073		T4	2956
all_pins[6]	values[0x1]	102854	1			T14	3		T19	3		T20	2
all_pins[6]	transitions[0x0=>0x1]	102821	1			T14	2		T19	3		T20	1
all_pins[6]	transitions[0x1=>0x0]	136	1			T14	3		T18	3		T19	2
all_pins[7]	values[0x0]	2816215	1			T1	136		T2	4073		T4	2956
all_pins[7]	values[0x1]	169	1			T14	4		T18	3		T19	2
all_pins[7]	transitions[0x0=>0x1]	117	1			T18	3		T19	1		T20	4
all_pins[7]	transitions[0x1=>0x0]	773	1			T14	4		T18	2		T19	3