Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15617

1

T5

130

T7

10

T13

2

auto[1]

12391

1

T5

111

T14

57

T15

198

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3387	1			T5	21		T14	78		T15	165
values[1]	3570	1			T5	31		T14	25		T15	97
values[2]	3659	1			T5	25		T13	2		T15	80
values[3]	3206	1			T15	60		T27	6		T98	18
values[4]	3812	1			T5	21		T7	10		T14	20
values[5]	3399	1			T5	82		T29	71		T108	10
values[6]	3207	1			T5	33		T15	20		T29	23
values[7]	3768	1			T5	28		T15	71		T29	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3706	1			T5	63		T7	10		T13	2
values[1]	3597	1			T15	64		T29	20		T21	82
values[2]	2854	1			T5	53		T14	20		T15	51
values[3]	3316	1			T5	21		T14	34		T15	97
values[4]	3375	1			T5	56		T15	91		T29	56
values[5]	3486	1			T5	28		T14	24		T15	95
values[6]	3943	1			T5	20		T14	45		T15	75
values[7]	3731	1			T15	20		T106	12		T53	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	242	1			T202	11		T198	14		T240	4
auto[0]	values[0]	values[1]	225	1			T15	52		T21	18		T207	15
auto[0]	values[0]	values[2]	248	1			T14	10		T15	12		T180	12
auto[0]	values[0]	values[3]	169	1			T5	13		T14	14		T18	10
auto[0]	values[0]	values[4]	186	1			T29	46		T58	14		T21	13
auto[0]	values[0]	values[5]	222	1			T14	11		T15	62		T202	14
auto[0]	values[0]	values[6]	386	1			T21	16		T180	8		T142	14
auto[0]	values[0]	values[7]	205	1			T201	11		T226	11		T204	17
auto[0]	values[1]	values[0]	286	1			T241	2		T232	11		T158	15
auto[0]	values[1]	values[1]	210	1			T21	33		T23	18		T180	8
auto[0]	values[1]	values[2]	211	1			T185	11		T204	13		T242	50
auto[0]	values[1]	values[3]	179	1			T15	23		T207	17		T201	10
auto[0]	values[1]	values[4]	220	1			T5	12		T243	12		T96	11
auto[0]	values[1]	values[5]	205	1			T58	7		T207	17		T180	9
auto[0]	values[1]	values[6]	187	1			T14	17		T219	9		T193	11
auto[0]	values[1]	values[7]	346	1			T106	12		T21	137		T195	10
auto[0]	values[2]	values[0]	221	1			T13	2		T244	4		T21	7
auto[0]	values[2]	values[1]	269	1			T188	12		T237	11		T185	13
auto[0]	values[2]	values[2]	244	1			T15	18		T21	21		T195	7
auto[0]	values[2]	values[3]	251	1			T29	15		T245	6		T187	15
auto[0]	values[2]	values[4]	194	1			T5	4		T21	13		T231	11
auto[0]	values[2]	values[5]	246	1			T246	8		T247	10		T221	10
auto[0]	values[2]	values[6]	219	1			T15	19		T21	9		T192	10
auto[0]	values[2]	values[7]	196	1			T21	12		T211	41		T225	14
auto[0]	values[3]	values[0]	186	1			T21	11		T92	28		T188	11
auto[0]	values[3]	values[1]	289	1			T23	17		T96	15		T207	19
auto[0]	values[3]	values[2]	204	1			T22	4		T23	16		T226	29
auto[0]	values[3]	values[3]	226	1			T22	18		T23	18		T195	15
auto[0]	values[3]	values[4]	228	1			T15	14		T190	19		T180	18
auto[0]	values[3]	values[5]	163	1			T15	13		T217	6		T109	6
auto[0]	values[3]	values[6]	285	1			T15	14		T21	106		T248	13
auto[0]	values[3]	values[7]	174	1			T21	8		T96	10		T249	6
auto[0]	values[4]	values[0]	326	1			T5	12		T7	10		T29	16
auto[0]	values[4]	values[1]	214	1			T29	9		T190	10		T234	15
auto[0]	values[4]	values[2]	234	1			T207	11		T142	12		T250	14
auto[0]	values[4]	values[3]	383	1			T207	20		T251	14		T193	11
auto[0]	values[4]	values[4]	339	1			T198	14		T252	4		T188	139
auto[0]	values[4]	values[5]	169	1			T190	11		T201	8		T239	15
auto[0]	values[4]	values[6]	284	1			T14	14		T29	14		T22	13
auto[0]	values[4]	values[7]	254	1			T53	2		T22	8		T195	14
auto[0]	values[5]	values[0]	209	1			T5	36		T21	19		T31	12
auto[0]	values[5]	values[1]	328	1			T253	7		T200	4		T254	4
auto[0]	values[5]	values[2]	181	1			T5	9		T96	10		T195	15
auto[0]	values[5]	values[3]	171	1			T21	25		T22	12		T198	10
auto[0]	values[5]	values[4]	167	1			T108	10		T190	12		T215	12
auto[0]	values[5]	values[5]	203	1			T23	11		T209	6		T234	12
auto[0]	values[5]	values[6]	467	1			T5	13		T29	49		T21	13
auto[0]	values[5]	values[7]	238	1			T21	11		T219	33		T48	15
auto[0]	values[6]	values[0]	82	1			T29	5		T96	10		T181	14
auto[0]	values[6]	values[1]	356	1			T190	8		T255	24		T193	17
auto[0]	values[6]	values[2]	185	1			T5	23		T202	9		T218	12
auto[0]	values[6]	values[3]	229	1			T256	6		T190	8		T231	9
auto[0]	values[6]	values[4]	367	1			T21	29		T195	8		T190	14
auto[0]	values[6]	values[5]	151	1			T198	14		T180	15		T184	8
auto[0]	values[6]	values[6]	231	1			T21	14		T23	17		T239	15
auto[0]	values[6]	values[7]	232	1			T15	16		T23	16		T257	4
auto[0]	values[7]	values[0]	416	1			T29	13		T20	18		T58	10
auto[0]	values[7]	values[1]	142	1			T231	12		T258	4		T226	11
auto[0]	values[7]	values[2]	205	1			T20	6		T197	18		T198	9
auto[0]	values[7]	values[3]	176	1			T29	9		T259	4		T218	19
auto[0]	values[7]	values[4]	321	1			T15	52		T207	13		T260	6
auto[0]	values[7]	values[5]	393	1			T5	8		T107	2		T21	23
auto[0]	values[7]	values[6]	169	1			T191	18		T261	12		T253	15
auto[0]	values[7]	values[7]	473	1			T21	48		T22	14		T234	9
auto[1]	values[0]	values[0]	141	1			T202	64		T198	6		T158	8
auto[1]	values[0]	values[1]	278	1			T15	12		T21	8		T207	7
auto[1]	values[0]	values[2]	106	1			T14	10		T15	14		T41	8
auto[1]	values[0]	values[3]	212	1			T5	8		T14	20		T18	10
auto[1]	values[0]	values[4]	125	1			T29	10		T58	6		T21	7
auto[1]	values[0]	values[5]	206	1			T14	13		T15	13		T202	6
auto[1]	values[0]	values[6]	244	1			T21	4		T180	12		T142	6
auto[1]	values[0]	values[7]	192	1			T201	9		T226	9		T204	30
auto[1]	values[1]	values[0]	323	1			T232	9		T158	138		T212	10
auto[1]	values[1]	values[1]	157	1			T21	23		T23	9		T220	8
auto[1]	values[1]	values[2]	128	1			T185	21		T204	7		T242	8
auto[1]	values[1]	values[3]	203	1			T15	74		T207	3		T201	10
auto[1]	values[1]	values[4]	163	1			T5	19		T96	9		T190	10
auto[1]	values[1]	values[5]	222	1			T58	13		T207	7		T180	11
auto[1]	values[1]	values[6]	282	1			T14	8		T219	11		T193	9
auto[1]	values[1]	values[7]	248	1			T21	22		T195	10		T198	28
auto[1]	values[2]	values[0]	210	1			T21	13		T253	18		T195	12
auto[1]	values[2]	values[1]	247	1			T188	33		T237	11		T185	7
auto[1]	values[2]	values[2]	290	1			T15	7		T21	43		T195	13
auto[1]	values[2]	values[3]	178	1			T29	7		T187	10		T237	5
auto[1]	values[2]	values[4]	153	1			T5	21		T21	7		T262	18
auto[1]	values[2]	values[5]	241	1			T246	12		T247	10		T221	10
auto[1]	values[2]	values[6]	219	1			T15	36		T21	11		T158	11
auto[1]	values[2]	values[7]	281	1			T21	45		T158	7		T185	11
auto[1]	values[3]	values[0]	205	1			T98	18		T21	29		T188	9
auto[1]	values[3]	values[1]	188	1			T23	12		T96	5		T207	2
auto[1]	values[3]	values[2]	146	1			T42	14		T22	16		T23	6
auto[1]	values[3]	values[3]	261	1			T27	6		T22	9		T23	6
auto[1]	values[3]	values[4]	203	1			T15	6		T190	32		T180	2
auto[1]	values[3]	values[5]	138	1			T15	7		T198	11		T210	12
auto[1]	values[3]	values[6]	163	1			T15	6		T21	11		T248	7
auto[1]	values[3]	values[7]	147	1			T21	38		T96	10		T219	29
auto[1]	values[4]	values[0]	175	1			T5	9		T29	7		T207	4
auto[1]	values[4]	values[1]	130	1			T29	11		T190	41		T234	5
auto[1]	values[4]	values[2]	130	1			T207	10		T142	8		T193	7
auto[1]	values[4]	values[3]	301	1			T207	4		T193	9		T237	9
auto[1]	values[4]	values[4]	158	1			T198	9		T263	20		T188	7
auto[1]	values[4]	values[5]	292	1			T190	26		T201	12		T239	8
auto[1]	values[4]	values[6]	247	1			T14	6		T25	12		T29	6
auto[1]	values[4]	values[7]	176	1			T22	13		T195	6		T207	13
auto[1]	values[5]	values[0]	235	1			T5	6		T21	11		T31	9
auto[1]	values[5]	values[1]	254	1			T253	13		T215	7		T264	20
auto[1]	values[5]	values[2]	143	1			T5	11		T96	10		T195	8
auto[1]	values[5]	values[3]	88	1			T21	12		T22	8		T198	12
auto[1]	values[5]	values[4]	153	1			T190	45		T215	8		T265	46
auto[1]	values[5]	values[5]	247	1			T23	9		T189	6		T234	8
auto[1]	values[5]	values[6]	171	1			T5	7		T29	22		T21	7
auto[1]	values[5]	values[7]	144	1			T21	21		T219	5		T48	6
auto[1]	values[6]	values[0]	124	1			T29	18		T96	10		T181	6
auto[1]	values[6]	values[1]	192	1			T190	12		T193	3		T226	11
auto[1]	values[6]	values[2]	91	1			T5	10		T202	11		T218	8
auto[1]	values[6]	values[3]	236	1			T190	22		T231	11		T188	10
auto[1]	values[6]	values[4]	211	1			T21	58		T195	12		T190	6
auto[1]	values[6]	values[5]	137	1			T198	6		T180	5		T188	7
auto[1]	values[6]	values[6]	258	1			T21	16		T23	8		T239	8
auto[1]	values[6]	values[7]	125	1			T15	4		T23	5		T226	8
auto[1]	values[7]	values[0]	325	1			T29	7		T20	8		T58	10
auto[1]	values[7]	values[1]	118	1			T231	19		T226	9		T204	8
auto[1]	values[7]	values[2]	108	1			T20	14		T198	19		T231	5
auto[1]	values[7]	values[3]	53	1			T29	11		T218	5		T266	16
auto[1]	values[7]	values[4]	187	1			T15	19		T207	11		T226	11
auto[1]	values[7]	values[5]	251	1			T5	20		T21	28		T188	88
auto[1]	values[7]	values[6]	131	1			T253	5		T207	9		T267	15
auto[1]	values[7]	values[7]	300	1			T21	26		T22	6		T234	11