Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	344	1			T5	3		T14	1		T29	3
auto[ReadAddrCrossIntoMailbox]	248	1			T5	3		T15	1		T29	1
auto[ReadAddrCrossOutOfMailbox]	291	1			T5	3		T14	4		T15	1
auto[ReadAddrCrossAllMailbox]	191	1			T5	1		T14	2		T15	2
auto[ReadAddrOutsideMailbox]	3308	1			T5	32		T7	4		T14	17

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2182

1

T5

28

T7

2

T14

7

auto[1]

2200

1

T5

14

T7

2

T14

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	739	1			T5	9		T14	5		T15	12
read_ops[0x0b]	740	1			T5	3		T7	4		T14	2
read_ops[0x3b]	687	1			T5	9		T14	5		T15	6
read_ops[0x6b]	785	1			T5	5		T14	3		T15	12
read_ops[0xbb]	761	1			T5	8		T14	3		T15	8
read_ops[0xeb]	670	1			T5	8		T14	6		T15	12

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T5	1		T29	1		T244	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T244	1		T21	2		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T29	1		T21	2		T23	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T190	2		T231	1		T234	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T14	1		T58	1		T21	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T23	2		T202	1		T207	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T21	1		T195	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T21	2		T158	1		T196	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	251	1			T5	5		T14	1		T15	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T5	3		T14	3		T15	11
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T5	1		T21	1		T195	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T21	1		T253	1		T231	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T5	2		T15	1		T207	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T195	1		T190	1		T223	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T198	1		T254	1		T246	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T21	2		T23	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T20	1		T198	1		T190	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T15	1		T22	1		T198	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T7	2		T14	1		T15	8
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T7	2		T14	1		T15	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T23	1		T248	1		T196	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T5	1		T21	1		T22	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T21	1		T195	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T21	1		T207	1		T198	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T21	1		T188	1		T246	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T14	1		T198	1		T219	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T21	1		T268	1		T239	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T188	2		T267	1		T205	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T5	4		T14	1		T15	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T5	4		T14	3		T15	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T22	1		T96	1		T198	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T29	1		T22	1		T188	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T21	3		T22	2		T198	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T20	1		T22	1		T207	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T5	1		T21	1		T202	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T5	1		T15	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T5	1		T190	2		T201	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T20	1		T22	1		T180	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T5	1		T14	1		T15	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T5	1		T14	2		T15	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T21	1		T198	1		T201	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T14	1		T190	1		T248	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T5	1		T21	2		T22	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T21	2		T207	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T21	2		T198	1		T231	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T29	1		T21	2		T198	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T21	1		T22	1		T190	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T14	1		T15	1		T190	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T5	4		T15	4		T29	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T5	3		T14	1		T15	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T29	1		T21	1		T207	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T21	1		T193	2		T226	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T96	1		T205	1		T239	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T23	1		T195	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T5	1		T202	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T14	2		T195	1		T188	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T21	1		T207	1		T190	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T14	1		T264	1		T269	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T5	6		T14	2		T15	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T5	1		T14	1		T15	7