Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3805	1			T5	28		T15	55		T27	6
values[1]	2933	1			T5	25		T14	20		T15	52
values[2]	3123	1			T5	74		T14	59		T15	114
values[3]	3600	1			T5	31		T15	46		T29	56
values[4]	3683	1			T5	83		T7	10		T14	20
values[5]	3405	1			T15	40		T29	46		T98	18
values[6]	3724	1			T13	2		T15	25		T29	46
values[7]	3735	1			T14	24		T15	161		T29	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4020	1			T5	21		T15	95		T29	22
values[1]	3201	1			T7	10		T13	2		T14	20
values[2]	3201	1			T5	82		T15	26		T107	2
values[3]	3124	1			T15	32		T25	12		T29	43
values[4]	3533	1			T5	25		T15	40		T27	6
values[5]	3666	1			T14	59		T15	55		T29	88
values[6]	3333	1			T14	20		T29	20		T58	20
values[7]	3930	1			T5	113		T14	24		T15	161

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27272

1

T5

234

T7

10

T13

2

auto[1]

736

1

T5

7

T14

5

T15

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	568	1			T29	22		T53	2		T21	40
auto[0]	values[0]	values[1]	332	1			T220	6		T190	20		T270	4
auto[0]	values[0]	values[2]	496	1			T231	20		T226	20		T264	201
auto[0]	values[0]	values[3]	378	1			T218	20		T271	22		T93	8
auto[0]	values[0]	values[4]	440	1			T15	18		T27	4		T22	41
auto[0]	values[0]	values[5]	646	1			T15	35		T29	20		T23	23
auto[0]	values[0]	values[6]	459	1			T58	20		T96	18		T272	4
auto[0]	values[0]	values[7]	393	1			T5	28		T252	4		T273	122
auto[0]	values[1]	values[0]	420	1			T15	20		T106	12		T244	4
auto[0]	values[1]	values[1]	507	1			T21	40		T207	20		T262	14
auto[0]	values[1]	values[2]	217	1			T107	2		T21	30		T253	33
auto[0]	values[1]	values[3]	433	1			T15	31		T250	14		T219	23
auto[0]	values[1]	values[4]	321	1			T5	25		T108	10		T21	18
auto[0]	values[1]	values[5]	297	1			T21	28		T258	4		T215	20
auto[0]	values[1]	values[6]	328	1			T14	20		T29	20		T183	53
auto[0]	values[1]	values[7]	342	1			T195	26		T201	118		T158	22
auto[0]	values[2]	values[0]	370	1			T15	75		T190	16		T218	23
auto[0]	values[2]	values[1]	252	1			T15	38		T18	20		T190	19
auto[0]	values[2]	values[2]	451	1			T5	19		T42	4		T21	78
auto[0]	values[2]	values[3]	338	1			T25	8		T21	20		T23	47
auto[0]	values[2]	values[4]	575	1			T58	20		T21	98		T211	41
auto[0]	values[2]	values[5]	377	1			T14	57		T20	19		T249	6
auto[0]	values[2]	values[6]	267	1			T21	30		T200	4		T180	20
auto[0]	values[2]	values[7]	399	1			T5	53		T20	26		T142	20
auto[0]	values[3]	values[0]	421	1			T261	12		T96	19		T202	20
auto[0]	values[3]	values[1]	458	1			T29	55		T21	63		T274	8
auto[0]	values[3]	values[2]	532	1			T15	25		T191	18		T198	22
auto[0]	values[3]	values[3]	346	1			T21	115		T188	46		T232	19
auto[0]	values[3]	values[4]	300	1			T201	19		T188	31		T226	23
auto[0]	values[3]	values[5]	284	1			T58	20		T23	25		T195	19
auto[0]	values[3]	values[6]	450	1			T275	10		T142	18		T276	8
auto[0]	values[3]	values[7]	718	1			T5	29		T15	17		T22	27
auto[0]	values[4]	values[0]	471	1			T5	20		T31	21		T238	8
auto[0]	values[4]	values[1]	352	1			T7	10		T14	17		T21	20
auto[0]	values[4]	values[2]	447	1			T5	60		T202	20		T195	20
auto[0]	values[4]	values[3]	463	1			T21	17		T207	20		T237	28
auto[0]	values[4]	values[4]	385	1			T253	20		T198	24		T277	14
auto[0]	values[4]	values[5]	430	1			T29	45		T41	8		T21	19
auto[0]	values[4]	values[6]	537	1			T23	26		T248	20		T231	26
auto[0]	values[4]	values[7]	474	1			T23	22		T207	22		T234	19
auto[0]	values[5]	values[0]	692	1			T223	8		T234	21		T219	24
auto[0]	values[5]	values[1]	367	1			T15	20		T253	19		T255	24
auto[0]	values[5]	values[2]	284	1			T23	20		T91	10		T193	20
auto[0]	values[5]	values[3]	408	1			T29	20		T96	20		T190	30
auto[0]	values[5]	values[4]	375	1			T98	18		T22	20		T207	20
auto[0]	values[5]	values[5]	483	1			T15	19		T29	22		T217	6
auto[0]	values[5]	values[6]	352	1			T21	68		T190	20		T251	14
auto[0]	values[5]	values[7]	343	1			T180	20		T184	8		T188	24
auto[0]	values[6]	values[0]	328	1			T22	20		T194	19		T214	22
auto[0]	values[6]	values[1]	470	1			T13	2		T15	25		T29	43
auto[0]	values[6]	values[2]	487	1			T21	163		T198	21		T248	20
auto[0]	values[6]	values[3]	299	1			T195	20		T207	24		T190	51
auto[0]	values[6]	values[4]	628	1			T231	34		T260	6		T241	2
auto[0]	values[6]	values[5]	422	1			T245	6		T22	20		T231	21
auto[0]	values[6]	values[6]	507	1			T21	20		T259	4		T187	20
auto[0]	values[6]	values[7]	501	1			T109	6		T198	20		T188	44
auto[0]	values[7]	values[0]	650	1			T207	21		T198	40		T203	10
auto[0]	values[7]	values[1]	384	1			T21	21		T256	6		T190	36
auto[0]	values[7]	values[2]	199	1			T207	21		T190	56		T231	31
auto[0]	values[7]	values[3]	375	1			T29	20		T21	36		T195	18
auto[0]	values[7]	values[4]	423	1			T15	20		T21	20		T23	21
auto[0]	values[7]	values[5]	615	1			T21	55		T22	21		T202	74
auto[0]	values[7]	values[6]	327	1			T195	19		T193	18		T237	30
auto[0]	values[7]	values[7]	679	1			T14	24		T15	140		T243	12
auto[1]	values[0]	values[0]	10	1			T190	1		T246	3		T214	1
auto[1]	values[0]	values[1]	9	1			T220	2		T188	1		T185	1
auto[1]	values[0]	values[2]	6	1			T264	3		T144	2		T278	1
auto[1]	values[0]	values[3]	7	1			T279	1		T280	5		T281	1
auto[1]	values[0]	values[4]	19	1			T15	2		T27	2		T23	2
auto[1]	values[0]	values[5]	16	1			T23	1		T189	2		T188	1
auto[1]	values[0]	values[6]	20	1			T96	2		T231	3		T204	3
auto[1]	values[0]	values[7]	6	1			T219	2		T215	4		-	-
auto[1]	values[1]	values[0]	17	1			T188	2		T196	2		T215	3
auto[1]	values[1]	values[1]	9	1			T262	4		T198	1		T242	3
auto[1]	values[1]	values[2]	2	1			T187	2		-	-		-	-
auto[1]	values[1]	values[3]	16	1			T15	1		T219	2		T193	2
auto[1]	values[1]	values[4]	8	1			T21	2		T214	1		T282	1
auto[1]	values[1]	values[5]	8	1			T283	2		T216	1		T284	1
auto[1]	values[1]	values[6]	3	1			T222	1		T285	2		-	-
auto[1]	values[1]	values[7]	5	1			T286	1		T279	2		T287	1
auto[1]	values[2]	values[0]	11	1			T190	4		T218	1		T196	2
auto[1]	values[2]	values[1]	4	1			T15	1		T190	1		T158	2
auto[1]	values[2]	values[2]	22	1			T5	1		T42	10		T21	2
auto[1]	values[2]	values[3]	11	1			T25	4		T264	1		T288	4
auto[1]	values[2]	values[4]	8	1			T21	1		T140	1		T289	1
auto[1]	values[2]	values[5]	18	1			T14	2		T20	1		T234	4
auto[1]	values[2]	values[6]	12	1			T268	1		T264	4		T212	2
auto[1]	values[2]	values[7]	8	1			T5	1		T196	1		T204	1
auto[1]	values[3]	values[0]	15	1			T96	1		T196	1		T215	3
auto[1]	values[3]	values[1]	8	1			T29	1		T21	3		T290	3
auto[1]	values[3]	values[2]	8	1			T15	1		T198	1		T142	1
auto[1]	values[3]	values[3]	10	1			T21	2		T188	5		T232	1
auto[1]	values[3]	values[4]	13	1			T201	1		T188	2		T216	1
auto[1]	values[3]	values[5]	6	1			T195	1		T247	1		T281	1
auto[1]	values[3]	values[6]	16	1			T142	2		T196	3		T265	2
auto[1]	values[3]	values[7]	15	1			T5	2		T15	3		T188	1
auto[1]	values[4]	values[0]	15	1			T5	1		T204	3		T48	1
auto[1]	values[4]	values[1]	16	1			T14	3		T180	1		T268	3
auto[1]	values[4]	values[2]	17	1			T5	2		T195	3		T193	3
auto[1]	values[4]	values[3]	16	1			T21	6		T237	1		T205	3
auto[1]	values[4]	values[4]	19	1			T198	4		T277	4		T291	2
auto[1]	values[4]	values[5]	9	1			T21	1		T96	3		T292	2
auto[1]	values[4]	values[6]	17	1			T23	3		T188	2		T237	1
auto[1]	values[4]	values[7]	15	1			T234	1		T221	3		T293	1
auto[1]	values[5]	values[0]	16	1			T234	1		T219	1		T48	1
auto[1]	values[5]	values[1]	15	1			T253	1		T180	1		T219	2
auto[1]	values[5]	values[2]	15	1			T23	1		T158	3		T294	4
auto[1]	values[5]	values[3]	8	1			T29	3		T232	2		T269	1
auto[1]	values[5]	values[4]	7	1			T231	2		T234	2		T237	1
auto[1]	values[5]	values[5]	13	1			T15	1		T29	1		T237	1
auto[1]	values[5]	values[6]	16	1			T21	4		T49	7		T281	3
auto[1]	values[5]	values[7]	11	1			T295	4		T186	3		T296	2
auto[1]	values[6]	values[0]	4	1			T194	1		T214	1		T212	1
auto[1]	values[6]	values[1]	6	1			T29	3		T207	1		T279	1
auto[1]	values[6]	values[2]	11	1			T21	2		T198	2		T204	3
auto[1]	values[6]	values[3]	7	1			T195	2		T268	2		T291	2
auto[1]	values[6]	values[4]	7	1			T231	1		T297	1		T298	3
auto[1]	values[6]	values[5]	20	1			T187	3		T299	2		T215	1
auto[1]	values[6]	values[6]	12	1			T268	4		T292	2		T300	1
auto[1]	values[6]	values[7]	15	1			T188	1		T301	5		T302	1
auto[1]	values[7]	values[0]	12	1			T226	1		T237	2		T215	1
auto[1]	values[7]	values[1]	12	1			T21	1		T190	1		T180	2
auto[1]	values[7]	values[2]	7	1			T207	3		T190	1		T246	2
auto[1]	values[7]	values[3]	9	1			T21	1		T195	2		T289	1
auto[1]	values[7]	values[4]	5	1			T292	1		T144	2		T303	1
auto[1]	values[7]	values[5]	22	1			T21	2		T22	2		T202	1
auto[1]	values[7]	values[6]	10	1			T195	1		T193	2		T237	2
auto[1]	values[7]	values[7]	6	1			T15	1		T304	1		T284	2