Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1648

1

T1

1

T4

1

T5

6

auto[1]

1673

1

T4

2

T5

9

T9

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1878

1

T1

1

T4

3

T5

15

auto[1]

1443

1

T9

8

T11

5

T14

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2569

1

T4

2

T5

11

T9

8

auto[1]

752

1

T1

1

T4

1

T5

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	665	1			T4	1		T5	5		T9	2
valid[1]	727	1			T4	2		T5	4		T9	3
valid[2]	648	1			T5	4		T11	2		T14	6
valid[3]	637	1			T5	2		T9	2		T11	3
valid[4]	644	1			T1	1		T9	1		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	105	1			T5	3		T19	3		T87	1
auto[0]	auto[0]	valid[0]	auto[1]	140	1			T84	1		T87	1		T88	2
auto[0]	auto[0]	valid[1]	auto[0]	113	1			T5	1		T11	2		T14	1
auto[0]	auto[0]	valid[1]	auto[1]	146	1			T11	1		T87	1		T88	1
auto[0]	auto[0]	valid[2]	auto[0]	114	1			T5	2		T11	1		T14	1
auto[0]	auto[0]	valid[2]	auto[1]	123	1			T14	1		T18	2		T85	1
auto[0]	auto[0]	valid[3]	auto[0]	113	1			T14	1		T19	2		T87	1
auto[0]	auto[0]	valid[3]	auto[1]	148	1			T9	1		T14	1		T87	2
auto[0]	auto[0]	valid[4]	auto[0]	98	1			T11	1		T26	1		T29	1
auto[0]	auto[0]	valid[4]	auto[1]	153	1			T87	1		T54	2		T329	4
auto[0]	auto[1]	valid[0]	auto[0]	117	1			T5	2		T14	2		T26	1
auto[0]	auto[1]	valid[0]	auto[1]	157	1			T9	2		T14	1		T85	1
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T4	2		T85	1		T45	2
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T9	3		T11	1		T14	1
auto[0]	auto[1]	valid[2]	auto[0]	123	1			T5	2		T14	2		T29	1
auto[0]	auto[1]	valid[2]	auto[1]	145	1			T85	1		T87	1		T330	6
auto[0]	auto[1]	valid[3]	auto[0]	99	1			T5	1		T14	1		T18	1
auto[0]	auto[1]	valid[3]	auto[1]	122	1			T9	1		T11	3		T18	3
auto[0]	auto[1]	valid[4]	auto[0]	119	1			T14	1		T19	1		T45	2
auto[0]	auto[1]	valid[4]	auto[1]	132	1			T9	1		T87	1		T51	1
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T4	1		T11	1		T85	1
auto[1]	auto[0]	valid[1]	auto[0]	88	1			T29	1		T85	1		T45	1
auto[1]	auto[0]	valid[2]	auto[0]	67	1			T14	1		T19	1		T87	1
auto[1]	auto[0]	valid[3]	auto[0]	90	1			T14	2		T18	1		T19	1
auto[1]	auto[0]	valid[4]	auto[0]	68	1			T1	1		T11	1		T14	2
auto[1]	auto[1]	valid[0]	auto[0]	64	1			T86	1		T45	2		T39	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T5	3		T11	1		T29	1
auto[1]	auto[1]	valid[2]	auto[0]	76	1			T11	1		T14	1		T18	1
auto[1]	auto[1]	valid[3]	auto[0]	65	1			T5	1		T85	2		T86	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T46	1		T326	1		T21	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal