Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48360

1

T1

26

T4

200

T5

326

auto[1]

14140

1

T1

5

T9

121

T11

92

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44970

1

T1

19

T4

133

T5

224

auto[1]

17530

1

T1

12

T4

67

T5

102

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32154	1			T1	19		T4	98		T5	174
others[1]	5315	1			T1	2		T4	15		T5	30
others[2]	5263	1			T1	1		T4	13		T5	24
others[3]	6004	1			T1	2		T4	27		T5	33
interest[1]	3398	1			T1	2		T4	12		T5	20
interest[4]	21125	1			T1	9		T4	67		T5	110
interest[64]	10366	1			T1	5		T4	35		T5	45

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15643	1			T1	8		T4	69		T5	119
auto[0]	auto[0]	others[1]	2641	1			T1	2		T4	11		T5	21
auto[0]	auto[0]	others[2]	2664	1			T4	7		T5	15		T11	16
auto[0]	auto[0]	others[3]	2985	1			T1	1		T4	13		T5	22
auto[0]	auto[0]	interest[1]	1711	1			T4	10		T5	14		T11	4
auto[0]	auto[0]	interest[4]	10147	1			T1	2		T4	46		T5	80
auto[0]	auto[0]	interest[64]	5186	1			T1	3		T4	23		T5	33
auto[0]	auto[1]	others[0]	7462	1			T1	3		T9	62		T11	49
auto[0]	auto[1]	others[1]	1173	1			T9	15		T11	4		T14	1
auto[0]	auto[1]	others[2]	1168	1			T1	1		T9	12		T11	6
auto[0]	auto[1]	others[3]	1352	1			T9	5		T11	9		T14	7
auto[0]	auto[1]	interest[1]	722	1			T1	1		T9	4		T11	5
auto[0]	auto[1]	interest[4]	5031	1			T1	2		T9	47		T11	31
auto[0]	auto[1]	interest[64]	2263	1			T9	23		T11	19		T14	7
auto[1]	auto[0]	others[0]	9049	1			T1	8		T4	29		T5	55
auto[1]	auto[0]	others[1]	1501	1			T4	4		T5	9		T11	9
auto[1]	auto[0]	others[2]	1431	1			T4	6		T5	9		T11	13
auto[1]	auto[0]	others[3]	1667	1			T1	1		T4	14		T5	11
auto[1]	auto[0]	interest[1]	965	1			T1	1		T4	2		T5	6
auto[1]	auto[0]	interest[4]	5947	1			T1	5		T4	21		T5	30
auto[1]	auto[0]	interest[64]	2917	1			T1	2		T4	12		T5	12

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal