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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.29 95.43 99.21


Total test records in report: 1149
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T148 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2152696264 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:02 PM PDT 24 150016856 ps
T126 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4043530808 Aug 01 05:35:52 PM PDT 24 Aug 01 05:36:30 PM PDT 24 7865653497 ps
T1035 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.286412373 Aug 01 05:36:08 PM PDT 24 Aug 01 05:36:09 PM PDT 24 11963681 ps
T118 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3177330574 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:04 PM PDT 24 186806976 ps
T110 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2728367088 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:02 PM PDT 24 139377434 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1607859625 Aug 01 05:35:51 PM PDT 24 Aug 01 05:35:52 PM PDT 24 12547975 ps
T129 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.927503593 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:15 PM PDT 24 5257449451 ps
T119 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1264895166 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:12 PM PDT 24 28176869 ps
T1037 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1911264651 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:10 PM PDT 24 43580550 ps
T1038 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.982106831 Aug 01 05:36:16 PM PDT 24 Aug 01 05:36:17 PM PDT 24 11734031 ps
T1039 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2388582033 Aug 01 05:36:06 PM PDT 24 Aug 01 05:36:08 PM PDT 24 58902455 ps
T1040 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3647409927 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:10 PM PDT 24 57439974 ps
T1041 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3123565895 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:13 PM PDT 24 33099801 ps
T1042 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2951919433 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:03 PM PDT 24 258811080 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.909558350 Aug 01 05:35:54 PM PDT 24 Aug 01 05:36:00 PM PDT 24 242793322 ps
T104 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3521815144 Aug 01 05:36:03 PM PDT 24 Aug 01 05:36:11 PM PDT 24 589902825 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1500171896 Aug 01 05:35:52 PM PDT 24 Aug 01 05:35:54 PM PDT 24 37157892 ps
T128 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3431131051 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:03 PM PDT 24 198965584 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4134512486 Aug 01 05:35:58 PM PDT 24 Aug 01 05:35:59 PM PDT 24 28808025 ps
T1044 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3059714074 Aug 01 05:35:50 PM PDT 24 Aug 01 05:35:52 PM PDT 24 76937195 ps
T1045 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1196663927 Aug 01 05:36:07 PM PDT 24 Aug 01 05:36:11 PM PDT 24 113669666 ps
T155 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1199583724 Aug 01 05:35:52 PM PDT 24 Aug 01 05:36:02 PM PDT 24 1732513995 ps
T1046 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2064553626 Aug 01 05:35:58 PM PDT 24 Aug 01 05:35:59 PM PDT 24 44322828 ps
T1047 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.31897076 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:10 PM PDT 24 49604422 ps
T113 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3221923048 Aug 01 05:35:49 PM PDT 24 Aug 01 05:35:54 PM PDT 24 186245451 ps
T156 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3344076753 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:04 PM PDT 24 138296235 ps
T1048 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1590492750 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:11 PM PDT 24 26500404 ps
T1049 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3984534171 Aug 01 05:36:15 PM PDT 24 Aug 01 05:36:16 PM PDT 24 35133620 ps
T170 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3751745808 Aug 01 05:36:05 PM PDT 24 Aug 01 05:36:20 PM PDT 24 673898637 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3908847662 Aug 01 05:36:06 PM PDT 24 Aug 01 05:36:07 PM PDT 24 132350119 ps
T1051 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2042439627 Aug 01 05:35:59 PM PDT 24 Aug 01 05:36:00 PM PDT 24 25157572 ps
T1052 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3769952475 Aug 01 05:36:12 PM PDT 24 Aug 01 05:36:14 PM PDT 24 55446829 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1536023523 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:01 PM PDT 24 139643207 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.417714173 Aug 01 05:36:04 PM PDT 24 Aug 01 05:36:05 PM PDT 24 13640784 ps
T173 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2902095999 Aug 01 05:36:08 PM PDT 24 Aug 01 05:36:28 PM PDT 24 1217895261 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1741454993 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:03 PM PDT 24 418328216 ps
T1056 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3629686983 Aug 01 05:36:12 PM PDT 24 Aug 01 05:36:15 PM PDT 24 1138400142 ps
T130 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1685011888 Aug 01 05:36:03 PM PDT 24 Aug 01 05:36:06 PM PDT 24 1010463025 ps
T112 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2162994381 Aug 01 05:35:59 PM PDT 24 Aug 01 05:36:04 PM PDT 24 188537113 ps
T114 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.342353310 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:15 PM PDT 24 104656693 ps
T174 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.538972905 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:15 PM PDT 24 1174520156 ps
T1057 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4258115069 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:11 PM PDT 24 38345837 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4244682336 Aug 01 05:35:48 PM PDT 24 Aug 01 05:35:50 PM PDT 24 15734164 ps
T1059 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1483530922 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:11 PM PDT 24 125672303 ps
T1060 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4142062074 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:11 PM PDT 24 12555052 ps
T131 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3502946089 Aug 01 05:35:54 PM PDT 24 Aug 01 05:36:06 PM PDT 24 3579185112 ps
T171 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3901464942 Aug 01 05:36:15 PM PDT 24 Aug 01 05:36:27 PM PDT 24 1385589657 ps
T1061 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1462138350 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:12 PM PDT 24 17712718 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.844864534 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:58 PM PDT 24 612511788 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.746542710 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:59 PM PDT 24 1090473299 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3314333998 Aug 01 05:35:52 PM PDT 24 Aug 01 05:35:55 PM PDT 24 159701224 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2233785561 Aug 01 05:35:51 PM PDT 24 Aug 01 05:35:51 PM PDT 24 13506373 ps
T1065 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2111866474 Aug 01 05:36:06 PM PDT 24 Aug 01 05:36:10 PM PDT 24 698615226 ps
T167 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3308965485 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:20 PM PDT 24 1255540458 ps
T1066 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3976363677 Aug 01 05:36:13 PM PDT 24 Aug 01 05:36:14 PM PDT 24 14466232 ps
T1067 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3565743037 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:58 PM PDT 24 106762514 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.697972735 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:03 PM PDT 24 181420850 ps
T1069 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.203740511 Aug 01 05:36:07 PM PDT 24 Aug 01 05:36:07 PM PDT 24 11666676 ps
T132 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2695870663 Aug 01 05:35:53 PM PDT 24 Aug 01 05:36:17 PM PDT 24 2059025285 ps
T168 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1455011085 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:07 PM PDT 24 109786676 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2314304408 Aug 01 05:36:03 PM PDT 24 Aug 01 05:36:04 PM PDT 24 13229441 ps
T1071 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2256375631 Aug 01 05:35:50 PM PDT 24 Aug 01 05:36:10 PM PDT 24 1099561001 ps
T1072 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1971798578 Aug 01 05:36:08 PM PDT 24 Aug 01 05:36:11 PM PDT 24 155037896 ps
T1073 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1639470407 Aug 01 05:35:57 PM PDT 24 Aug 01 05:36:05 PM PDT 24 1466093797 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2150433252 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:05 PM PDT 24 370861260 ps
T1075 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3316999515 Aug 01 05:36:03 PM PDT 24 Aug 01 05:36:09 PM PDT 24 440933729 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.731845410 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:13 PM PDT 24 129782538 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4129571942 Aug 01 05:36:07 PM PDT 24 Aug 01 05:36:08 PM PDT 24 93229800 ps
T1078 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2807409610 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:04 PM PDT 24 158294294 ps
T175 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3096974348 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:13 PM PDT 24 399347456 ps
T1079 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2869642531 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:12 PM PDT 24 14979651 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1258888271 Aug 01 05:36:03 PM PDT 24 Aug 01 05:36:05 PM PDT 24 40108776 ps
T1081 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1704312968 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:13 PM PDT 24 60986938 ps
T176 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1057331948 Aug 01 05:35:53 PM PDT 24 Aug 01 05:36:18 PM PDT 24 1048562611 ps
T1082 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2228974404 Aug 01 05:36:03 PM PDT 24 Aug 01 05:36:07 PM PDT 24 158259673 ps
T1083 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.867912511 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:01 PM PDT 24 68343831 ps
T1084 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.336233934 Aug 01 05:36:06 PM PDT 24 Aug 01 05:36:08 PM PDT 24 45103698 ps
T169 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4266544964 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:08 PM PDT 24 276595658 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3031606975 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:57 PM PDT 24 629957941 ps
T177 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3759108500 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:10 PM PDT 24 1244303555 ps
T1086 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1231594853 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:10 PM PDT 24 15372568 ps
T1087 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.646974745 Aug 01 05:36:16 PM PDT 24 Aug 01 05:36:18 PM PDT 24 102242467 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3583484571 Aug 01 05:35:59 PM PDT 24 Aug 01 05:36:06 PM PDT 24 685857460 ps
T1089 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1244237324 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:13 PM PDT 24 33111194 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1099110613 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:55 PM PDT 24 58030841 ps
T1091 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.157066910 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:05 PM PDT 24 98301750 ps
T1092 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.331048340 Aug 01 05:35:59 PM PDT 24 Aug 01 05:36:02 PM PDT 24 197414938 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.773792242 Aug 01 05:35:59 PM PDT 24 Aug 01 05:36:03 PM PDT 24 636978397 ps
T1094 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1601576747 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:04 PM PDT 24 23385147 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.719904567 Aug 01 05:36:15 PM PDT 24 Aug 01 05:36:18 PM PDT 24 114895786 ps
T1096 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3419814501 Aug 01 05:36:01 PM PDT 24 Aug 01 05:36:05 PM PDT 24 55121813 ps
T1097 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1031380805 Aug 01 05:36:15 PM PDT 24 Aug 01 05:36:16 PM PDT 24 43920485 ps
T1098 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4276721993 Aug 01 05:36:18 PM PDT 24 Aug 01 05:36:24 PM PDT 24 1690334052 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1652770352 Aug 01 05:35:47 PM PDT 24 Aug 01 05:36:10 PM PDT 24 4585200193 ps
T1100 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1901447555 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:15 PM PDT 24 236264528 ps
T1101 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1143922092 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:13 PM PDT 24 488019682 ps
T81 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.879220950 Aug 01 05:35:47 PM PDT 24 Aug 01 05:35:48 PM PDT 24 80473480 ps
T1102 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1117623971 Aug 01 05:36:15 PM PDT 24 Aug 01 05:36:16 PM PDT 24 15423296 ps
T1103 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1069365043 Aug 01 05:35:57 PM PDT 24 Aug 01 05:36:01 PM PDT 24 559386894 ps
T1104 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.729710827 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:03 PM PDT 24 162669289 ps
T1105 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3271851773 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:03 PM PDT 24 160526064 ps
T1106 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1165330035 Aug 01 05:35:50 PM PDT 24 Aug 01 05:36:28 PM PDT 24 5204061522 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1066004000 Aug 01 05:36:12 PM PDT 24 Aug 01 05:36:13 PM PDT 24 45953140 ps
T1108 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3122982119 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:24 PM PDT 24 1102751972 ps
T1109 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1828016167 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:56 PM PDT 24 373073012 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3783139752 Aug 01 05:35:59 PM PDT 24 Aug 01 05:36:02 PM PDT 24 455575817 ps
T1111 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3330385654 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:12 PM PDT 24 57639593 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2333455378 Aug 01 05:35:49 PM PDT 24 Aug 01 05:35:50 PM PDT 24 18289355 ps
T1113 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2127659813 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:13 PM PDT 24 75032403 ps
T1114 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1244249381 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:56 PM PDT 24 135416963 ps
T1115 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.888999758 Aug 01 05:36:07 PM PDT 24 Aug 01 05:36:08 PM PDT 24 44521427 ps
T1116 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3057355208 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:12 PM PDT 24 12177134 ps
T1117 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1203070346 Aug 01 05:36:09 PM PDT 24 Aug 01 05:36:09 PM PDT 24 18335672 ps
T1118 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4085345255 Aug 01 05:35:59 PM PDT 24 Aug 01 05:36:00 PM PDT 24 26783109 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2623803467 Aug 01 05:35:52 PM PDT 24 Aug 01 05:35:53 PM PDT 24 34787092 ps
T1120 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3703272586 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:12 PM PDT 24 15205758 ps
T1121 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1568417336 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:55 PM PDT 24 110337859 ps
T82 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2276121668 Aug 01 05:35:52 PM PDT 24 Aug 01 05:35:53 PM PDT 24 142392470 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2220994068 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:56 PM PDT 24 132056069 ps
T1123 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1392789700 Aug 01 05:36:12 PM PDT 24 Aug 01 05:36:13 PM PDT 24 53140089 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3990913707 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:04 PM PDT 24 61072324 ps
T1125 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1109723606 Aug 01 05:36:06 PM PDT 24 Aug 01 05:36:08 PM PDT 24 48478521 ps
T172 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.540502145 Aug 01 05:35:53 PM PDT 24 Aug 01 05:36:09 PM PDT 24 700477057 ps
T1126 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1915127388 Aug 01 05:36:16 PM PDT 24 Aug 01 05:36:17 PM PDT 24 34152745 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2132087521 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:54 PM PDT 24 26423141 ps
T1128 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2938973045 Aug 01 05:36:16 PM PDT 24 Aug 01 05:36:17 PM PDT 24 25585341 ps
T1129 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3516935151 Aug 01 05:35:51 PM PDT 24 Aug 01 05:35:54 PM PDT 24 86143852 ps
T1130 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2652976558 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:12 PM PDT 24 24968379 ps
T1131 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4205120661 Aug 01 05:36:12 PM PDT 24 Aug 01 05:36:13 PM PDT 24 12969578 ps
T1132 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4086286698 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:06 PM PDT 24 131250550 ps
T1133 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3650125974 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:03 PM PDT 24 552877339 ps
T1134 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2925159 Aug 01 05:36:08 PM PDT 24 Aug 01 05:36:09 PM PDT 24 14622255 ps
T1135 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3284685061 Aug 01 05:36:06 PM PDT 24 Aug 01 05:36:09 PM PDT 24 126908084 ps
T166 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3683804599 Aug 01 05:36:04 PM PDT 24 Aug 01 05:36:09 PM PDT 24 234067580 ps
T1136 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4118178360 Aug 01 05:35:51 PM PDT 24 Aug 01 05:35:55 PM PDT 24 485769375 ps
T1137 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3382997516 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:04 PM PDT 24 181229989 ps
T1138 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1584208217 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:12 PM PDT 24 109569640 ps
T1139 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1585496772 Aug 01 05:36:11 PM PDT 24 Aug 01 05:36:14 PM PDT 24 151211077 ps
T83 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.326651029 Aug 01 05:35:51 PM PDT 24 Aug 01 05:35:52 PM PDT 24 18749255 ps
T1140 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.816636068 Aug 01 05:35:51 PM PDT 24 Aug 01 05:35:59 PM PDT 24 634242017 ps
T1141 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3104621420 Aug 01 05:35:52 PM PDT 24 Aug 01 05:35:54 PM PDT 24 68779002 ps
T1142 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.580420383 Aug 01 05:36:12 PM PDT 24 Aug 01 05:36:13 PM PDT 24 13787980 ps
T1143 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2131645275 Aug 01 05:35:53 PM PDT 24 Aug 01 05:35:54 PM PDT 24 11858089 ps
T1144 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3215601075 Aug 01 05:36:08 PM PDT 24 Aug 01 05:36:11 PM PDT 24 52570793 ps
T1145 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2925693525 Aug 01 05:36:00 PM PDT 24 Aug 01 05:36:04 PM PDT 24 193146997 ps
T1146 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4223547302 Aug 01 05:36:10 PM PDT 24 Aug 01 05:36:19 PM PDT 24 734238553 ps
T1147 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.531280622 Aug 01 05:36:12 PM PDT 24 Aug 01 05:36:13 PM PDT 24 23777693 ps
T1148 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3566050083 Aug 01 05:35:52 PM PDT 24 Aug 01 05:35:54 PM PDT 24 172893254 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2990888289 Aug 01 05:36:02 PM PDT 24 Aug 01 05:36:10 PM PDT 24 110375839 ps

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.687497743
Short name T5
Test name
Test status
Simulation time 8279507890 ps
CPU time 92.67 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:18:54 PM PDT 24
Peak memory 266248 kb
Host smart-20d9d00d-8c7c-4fd8-8e58-eb5e1b07e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687497743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.687497743
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3678336394
Short name T14
Test name
Test status
Simulation time 4573054359 ps
CPU time 78.45 seconds
Started Aug 01 05:18:41 PM PDT 24
Finished Aug 01 05:20:00 PM PDT 24
Peak memory 249928 kb
Host smart-fab71e00-d7c2-47ac-b956-5350fca5d04a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678336394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3678336394
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2344388151
Short name T21
Test name
Test status
Simulation time 48694942181 ps
CPU time 300.33 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:24:21 PM PDT 24
Peak memory 307232 kb
Host smart-26edc535-788b-4150-bd94-f0f2e3becfc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344388151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2344388151
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.950136800
Short name T99
Test name
Test status
Simulation time 685137857 ps
CPU time 14.91 seconds
Started Aug 01 05:36:05 PM PDT 24
Finished Aug 01 05:36:20 PM PDT 24
Peak memory 215476 kb
Host smart-39c5d4e5-1673-41b2-9187-b6fde74315c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950136800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.950136800
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3344435300
Short name T23
Test name
Test status
Simulation time 93619474578 ps
CPU time 476.24 seconds
Started Aug 01 05:18:38 PM PDT 24
Finished Aug 01 05:26:34 PM PDT 24
Peak memory 265288 kb
Host smart-e037cac4-a313-41b3-832c-6180fc608d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344435300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3344435300
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3948117020
Short name T64
Test name
Test status
Simulation time 15982000 ps
CPU time 0.77 seconds
Started Aug 01 05:15:18 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 216592 kb
Host smart-8a7b133c-8e13-41ac-92a4-2eecda22fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948117020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3948117020
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.213781820
Short name T31
Test name
Test status
Simulation time 104314803931 ps
CPU time 183 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:18:45 PM PDT 24
Peak memory 256180 kb
Host smart-666538ec-6850-4b82-a234-618b8bd59383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213781820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.213781820
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.919713271
Short name T2
Test name
Test status
Simulation time 30001675253 ps
CPU time 218.95 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:22:59 PM PDT 24
Peak memory 249916 kb
Host smart-4dee194f-46f6-4ce1-830e-7d983a996bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919713271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.919713271
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1812749656
Short name T264
Test name
Test status
Simulation time 153731783756 ps
CPU time 722.35 seconds
Started Aug 01 05:16:12 PM PDT 24
Finished Aug 01 05:28:14 PM PDT 24
Peak memory 299108 kb
Host smart-b2698e15-4da1-44d8-ba42-9a9b3479f190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812749656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1812749656
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.297843733
Short name T105
Test name
Test status
Simulation time 270300146 ps
CPU time 4.54 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:16 PM PDT 24
Peak memory 215684 kb
Host smart-cb738d39-5663-4b59-a24c-86f55b7d2049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297843733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.297843733
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4149139404
Short name T61
Test name
Test status
Simulation time 41544676 ps
CPU time 0.75 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:35 PM PDT 24
Peak memory 206056 kb
Host smart-49621dfb-0d7a-4559-bcf4-875fddcb3ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149139404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4149139404
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.459055774
Short name T17
Test name
Test status
Simulation time 2852321778 ps
CPU time 26.58 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:17:11 PM PDT 24
Peak memory 241628 kb
Host smart-2e32fcbb-73f3-4995-ae86-1501189f64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459055774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.459055774
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4121635288
Short name T188
Test name
Test status
Simulation time 6581648948 ps
CPU time 142.87 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:21:10 PM PDT 24
Peak memory 274460 kb
Host smart-27b65af9-eb5c-4890-b044-05a1f446195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121635288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4121635288
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2534110914
Short name T29
Test name
Test status
Simulation time 60337570584 ps
CPU time 516.3 seconds
Started Aug 01 05:18:20 PM PDT 24
Finished Aug 01 05:26:57 PM PDT 24
Peak memory 258164 kb
Host smart-cdf6f67c-b2bd-4fab-a1fc-9436632ca1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534110914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2534110914
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.625036249
Short name T158
Test name
Test status
Simulation time 13165830375 ps
CPU time 193.43 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:20:04 PM PDT 24
Peak memory 283764 kb
Host smart-b0508dc0-3fb6-4a00-a40d-5a4bc35819d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625036249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.625036249
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.228868397
Short name T120
Test name
Test status
Simulation time 368858097 ps
CPU time 2.6 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 215568 kb
Host smart-26df5b04-3e81-4ec2-9848-1e9fa6d5650c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228868397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.228868397
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4210389751
Short name T226
Test name
Test status
Simulation time 22460792048 ps
CPU time 274.3 seconds
Started Aug 01 05:17:52 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 265700 kb
Host smart-876fd877-c202-4a34-bbeb-d52da1dba272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210389751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4210389751
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1367311097
Short name T214
Test name
Test status
Simulation time 140459470774 ps
CPU time 319.26 seconds
Started Aug 01 05:17:26 PM PDT 24
Finished Aug 01 05:22:45 PM PDT 24
Peak memory 260184 kb
Host smart-55134df2-99e5-4cb8-855a-437bccdd83f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367311097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1367311097
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.733507683
Short name T32
Test name
Test status
Simulation time 12918756313 ps
CPU time 150.93 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:18:32 PM PDT 24
Peak memory 274240 kb
Host smart-df06058a-3c32-43a0-9527-d8723e8c6970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733507683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.733507683
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3267891627
Short name T509
Test name
Test status
Simulation time 24605979 ps
CPU time 1.03 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:17 PM PDT 24
Peak memory 217104 kb
Host smart-d141b5eb-971d-45c1-a187-cd71efa4f810
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267891627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3267891627
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1812665171
Short name T215
Test name
Test status
Simulation time 67763917686 ps
CPU time 466.2 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:24:30 PM PDT 24
Peak memory 262860 kb
Host smart-fcc158ff-36e6-4cb0-89af-c75e97fa9c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812665171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1812665171
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1146736137
Short name T330
Test name
Test status
Simulation time 6801108225 ps
CPU time 6.81 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:07 PM PDT 24
Peak memory 217072 kb
Host smart-4c469054-7667-45ef-acc6-606964ef604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146736137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1146736137
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2104470385
Short name T68
Test name
Test status
Simulation time 37441418 ps
CPU time 0.97 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 235600 kb
Host smart-ef9c7cc6-831b-490b-8bc6-c2d53d72627b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104470385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2104470385
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2954476581
Short name T198
Test name
Test status
Simulation time 140544967916 ps
CPU time 690.39 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:28:15 PM PDT 24
Peak memory 263816 kb
Host smart-c2e4e0a0-4916-4438-a040-2949173178c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954476581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2954476581
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2994565950
Short name T269
Test name
Test status
Simulation time 37994228374 ps
CPU time 380.97 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:23:56 PM PDT 24
Peak memory 256912 kb
Host smart-058bfebd-96e8-4e7b-b57a-7944127f0859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994565950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2994565950
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1549052995
Short name T304
Test name
Test status
Simulation time 21767197329 ps
CPU time 96.56 seconds
Started Aug 01 05:18:34 PM PDT 24
Finished Aug 01 05:20:11 PM PDT 24
Peak memory 249768 kb
Host smart-2a13d4d5-e91b-4d2d-8e77-6c7436cd2159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549052995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1549052995
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3308965485
Short name T167
Test name
Test status
Simulation time 1255540458 ps
CPU time 18.52 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:20 PM PDT 24
Peak memory 223612 kb
Host smart-03ef788c-f028-4c45-a8df-117a41e5f200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308965485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3308965485
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.316147023
Short name T231
Test name
Test status
Simulation time 6500864742 ps
CPU time 107.85 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:17:28 PM PDT 24
Peak memory 251028 kb
Host smart-59a3a9e4-fbe5-48f3-b37b-3ac22cb528ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316147023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.316147023
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1190943997
Short name T280
Test name
Test status
Simulation time 218236935843 ps
CPU time 411.38 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:23:44 PM PDT 24
Peak memory 265276 kb
Host smart-889cdfd3-c905-491d-bfaf-0884abfe61b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190943997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1190943997
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.844864534
Short name T116
Test name
Test status
Simulation time 612511788 ps
CPU time 4.49 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:58 PM PDT 24
Peak memory 215736 kb
Host smart-694bb08d-f31d-4f54-91b2-d01832a66ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844864534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.844864534
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4158044384
Short name T433
Test name
Test status
Simulation time 13130240752 ps
CPU time 113.9 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:17:56 PM PDT 24
Peak memory 249872 kb
Host smart-cd18fc6a-d907-439a-91bf-ebc6c5a95593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158044384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4158044384
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1146664963
Short name T319
Test name
Test status
Simulation time 20174294727 ps
CPU time 31.35 seconds
Started Aug 01 05:16:42 PM PDT 24
Finished Aug 01 05:17:14 PM PDT 24
Peak memory 217008 kb
Host smart-2b825408-b0fb-448b-9ca0-525a70f251af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146664963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1146664963
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.737655332
Short name T246
Test name
Test status
Simulation time 23127926047 ps
CPU time 97.12 seconds
Started Aug 01 05:18:35 PM PDT 24
Finished Aug 01 05:20:13 PM PDT 24
Peak memory 267916 kb
Host smart-47572e45-2b28-42f7-bb7d-e097f8178e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737655332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.737655332
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2140013994
Short name T865
Test name
Test status
Simulation time 781627786300 ps
CPU time 444.86 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:26:26 PM PDT 24
Peak memory 257640 kb
Host smart-a4cd80c0-0c72-4cc6-a659-f2d368fe7475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140013994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2140013994
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.130178232
Short name T833
Test name
Test status
Simulation time 1963522966 ps
CPU time 33.04 seconds
Started Aug 01 05:15:44 PM PDT 24
Finished Aug 01 05:16:17 PM PDT 24
Peak memory 241532 kb
Host smart-6cd195b9-c8a6-4708-a0be-345e178261b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130178232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.130178232
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_upload.393802120
Short name T211
Test name
Test status
Simulation time 43429102036 ps
CPU time 30.76 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 235072 kb
Host smart-1cc4373c-9bb4-452f-9ffb-33afc0699014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393802120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.393802120
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3693010282
Short name T144
Test name
Test status
Simulation time 223459335310 ps
CPU time 610.66 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:27:00 PM PDT 24
Peak memory 266268 kb
Host smart-1701d9e2-bc5c-48c6-98a7-c50aadf165a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693010282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3693010282
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3483393860
Short name T15
Test name
Test status
Simulation time 18003953142 ps
CPU time 101.1 seconds
Started Aug 01 05:15:46 PM PDT 24
Finished Aug 01 05:17:27 PM PDT 24
Peak memory 264496 kb
Host smart-1bd948e0-b6d3-4836-93b7-807f975360d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483393860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3483393860
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1057331948
Short name T176
Test name
Test status
Simulation time 1048562611 ps
CPU time 24.89 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:36:18 PM PDT 24
Peak memory 215956 kb
Host smart-29c125ec-fbce-47ea-ab6c-cdf9a3cca701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057331948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1057331948
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3677286900
Short name T298
Test name
Test status
Simulation time 45878112463 ps
CPU time 363.01 seconds
Started Aug 01 05:16:19 PM PDT 24
Finished Aug 01 05:22:22 PM PDT 24
Peak memory 258132 kb
Host smart-75a3c8f1-9b64-4649-b24c-8fb562c14479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677286900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3677286900
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1485262534
Short name T9
Test name
Test status
Simulation time 687384476 ps
CPU time 2 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:16:18 PM PDT 24
Peak memory 216584 kb
Host smart-90cdd85f-ef0f-4f98-aba1-827028f7fe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485262534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1485262534
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2419739439
Short name T212
Test name
Test status
Simulation time 66962221310 ps
CPU time 629.48 seconds
Started Aug 01 05:16:40 PM PDT 24
Finished Aug 01 05:27:10 PM PDT 24
Peak memory 267624 kb
Host smart-54431859-d8bc-49d7-a4e2-492b541b012c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419739439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2419739439
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1391968693
Short name T295
Test name
Test status
Simulation time 17140915781 ps
CPU time 15.86 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:17:00 PM PDT 24
Peak memory 249896 kb
Host smart-7374a10e-d4bd-4e75-a9a8-8408d645b0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391968693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1391968693
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2788566834
Short name T305
Test name
Test status
Simulation time 10508726492 ps
CPU time 30.06 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:17:22 PM PDT 24
Peak memory 249848 kb
Host smart-98c2b5f5-56f7-4354-8539-bf9340f02d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788566834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2788566834
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.533636214
Short name T218
Test name
Test status
Simulation time 2498039628 ps
CPU time 26.39 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:29 PM PDT 24
Peak memory 241636 kb
Host smart-baf756f6-3cee-4bf6-a668-d34e3c27b2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533636214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.533636214
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.14455500
Short name T285
Test name
Test status
Simulation time 12424846247 ps
CPU time 15.73 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:50 PM PDT 24
Peak memory 233436 kb
Host smart-56e0acd8-9058-4b43-8900-90d06ef252f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14455500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.14455500
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3816076904
Short name T286
Test name
Test status
Simulation time 33285829948 ps
CPU time 105.9 seconds
Started Aug 01 05:18:07 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 241688 kb
Host smart-0440a9fd-98fd-4017-b48e-758c52d050f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816076904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3816076904
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4004935551
Short name T308
Test name
Test status
Simulation time 2063230027 ps
CPU time 32.84 seconds
Started Aug 01 05:18:29 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 233448 kb
Host smart-badf4b4e-7c06-4aed-99e1-9a1ea2aceb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004935551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4004935551
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4108287576
Short name T187
Test name
Test status
Simulation time 154604300534 ps
CPU time 281.43 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:23:18 PM PDT 24
Peak memory 249800 kb
Host smart-4aed3306-90b9-46f6-b6d3-2a3d6f548c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108287576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4108287576
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_intercept.872462599
Short name T244
Test name
Test status
Simulation time 1341124940 ps
CPU time 4.55 seconds
Started Aug 01 05:16:22 PM PDT 24
Finished Aug 01 05:16:26 PM PDT 24
Peak memory 233428 kb
Host smart-fd91e55d-5463-45ab-8a00-aa55094141a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872462599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.872462599
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3221923048
Short name T113
Test name
Test status
Simulation time 186245451 ps
CPU time 4.39 seconds
Started Aug 01 05:35:49 PM PDT 24
Finished Aug 01 05:35:54 PM PDT 24
Peak memory 215764 kb
Host smart-c7ec1b72-dbf0-4ae4-af50-825c63c72ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221923048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
221923048
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2276121668
Short name T82
Test name
Test status
Simulation time 142392470 ps
CPU time 1.41 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:35:53 PM PDT 24
Peak memory 207308 kb
Host smart-7b5a259c-5f81-420a-805a-6cf5c9389121
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276121668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2276121668
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3531564011
Short name T95
Test name
Test status
Simulation time 27200928313 ps
CPU time 155.08 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:19:39 PM PDT 24
Peak memory 251984 kb
Host smart-737bab91-9596-4e35-96dd-5e8c4ae78815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531564011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3531564011
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3029522920
Short name T121
Test name
Test status
Simulation time 882587193 ps
CPU time 14.66 seconds
Started Aug 01 05:35:50 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 207284 kb
Host smart-b23e848a-6033-4ac0-8245-ad335bcbb58d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029522920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3029522920
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4043530808
Short name T126
Test name
Test status
Simulation time 7865653497 ps
CPU time 38.33 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:36:30 PM PDT 24
Peak memory 215668 kb
Host smart-4e9fc99d-3ab3-4793-85c8-0856fcd44574
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043530808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4043530808
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.326651029
Short name T83
Test name
Test status
Simulation time 18749255 ps
CPU time 1.15 seconds
Started Aug 01 05:35:51 PM PDT 24
Finished Aug 01 05:35:52 PM PDT 24
Peak memory 216488 kb
Host smart-3a7202fe-4ca9-43e3-9c04-da0e61235f7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326651029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.326651029
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4118178360
Short name T1136
Test name
Test status
Simulation time 485769375 ps
CPU time 3.81 seconds
Started Aug 01 05:35:51 PM PDT 24
Finished Aug 01 05:35:55 PM PDT 24
Peak memory 217560 kb
Host smart-59e5d436-4551-43e8-9573-87b49e67bb94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118178360 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4118178360
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2560854716
Short name T146
Test name
Test status
Simulation time 468128305 ps
CPU time 1.38 seconds
Started Aug 01 05:35:50 PM PDT 24
Finished Aug 01 05:35:51 PM PDT 24
Peak memory 207260 kb
Host smart-f9952a6d-1ef1-4b7e-b714-423bb4845e6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560854716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
560854716
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2131645275
Short name T1143
Test name
Test status
Simulation time 11858089 ps
CPU time 0.76 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:54 PM PDT 24
Peak memory 203996 kb
Host smart-e4878133-c19a-42fc-bcc1-c215e1b92517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131645275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
131645275
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.821679935
Short name T125
Test name
Test status
Simulation time 125965403 ps
CPU time 2.14 seconds
Started Aug 01 05:35:49 PM PDT 24
Finished Aug 01 05:35:51 PM PDT 24
Peak memory 215496 kb
Host smart-dadaa7b7-a97d-4062-8990-fabd856b81bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821679935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.821679935
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.227170344
Short name T1029
Test name
Test status
Simulation time 28433568 ps
CPU time 0.67 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:35:53 PM PDT 24
Peak memory 204188 kb
Host smart-640c3eb9-5949-4b26-8ffb-356efe7ca81b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227170344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.227170344
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3314333998
Short name T1063
Test name
Test status
Simulation time 159701224 ps
CPU time 2.84 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:35:55 PM PDT 24
Peak memory 215572 kb
Host smart-d16fe9e3-efbc-4470-ae3a-fda3a06cda95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314333998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3314333998
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1199583724
Short name T155
Test name
Test status
Simulation time 1732513995 ps
CPU time 9.41 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:36:02 PM PDT 24
Peak memory 215544 kb
Host smart-cb85ecd1-632b-4353-8e41-a9389db32e30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199583724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1199583724
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2695870663
Short name T132
Test name
Test status
Simulation time 2059025285 ps
CPU time 22.89 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:36:17 PM PDT 24
Peak memory 207296 kb
Host smart-29085d35-28d7-42a8-970a-a47e3e8fe42a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695870663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2695870663
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3516935151
Short name T1129
Test name
Test status
Simulation time 86143852 ps
CPU time 3.07 seconds
Started Aug 01 05:35:51 PM PDT 24
Finished Aug 01 05:35:54 PM PDT 24
Peak memory 217804 kb
Host smart-49bee906-00e2-4966-ae9b-aaa460addc7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516935151 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3516935151
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1099110613
Short name T1090
Test name
Test status
Simulation time 58030841 ps
CPU time 1.43 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:55 PM PDT 24
Peak memory 215560 kb
Host smart-ac98ec0d-bf2f-41f5-a6aa-ede40fce476b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099110613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
099110613
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2333455378
Short name T1112
Test name
Test status
Simulation time 18289355 ps
CPU time 0.74 seconds
Started Aug 01 05:35:49 PM PDT 24
Finished Aug 01 05:35:50 PM PDT 24
Peak memory 203980 kb
Host smart-75662591-57f1-4d94-9a5b-4d8f264b31b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333455378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
333455378
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1500171896
Short name T127
Test name
Test status
Simulation time 37157892 ps
CPU time 1.6 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:35:54 PM PDT 24
Peak memory 215524 kb
Host smart-0feacea5-ca7d-46c1-bed8-3c69bfeb96da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500171896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1500171896
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2623803467
Short name T1119
Test name
Test status
Simulation time 34787092 ps
CPU time 0.66 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:35:53 PM PDT 24
Peak memory 203880 kb
Host smart-3a2e4130-6ba7-409a-9387-bd0e21a0078a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623803467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2623803467
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1828016167
Short name T1109
Test name
Test status
Simulation time 373073012 ps
CPU time 2.64 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:56 PM PDT 24
Peak memory 215496 kb
Host smart-673bbd38-4f36-410e-b6c8-169a8d8aa63c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828016167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1828016167
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.746542710
Short name T1062
Test name
Test status
Simulation time 1090473299 ps
CPU time 5.53 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:59 PM PDT 24
Peak memory 216700 kb
Host smart-3f0d028e-a64d-443e-82f4-64222577fad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746542710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.746542710
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.816636068
Short name T1140
Test name
Test status
Simulation time 634242017 ps
CPU time 8.12 seconds
Started Aug 01 05:35:51 PM PDT 24
Finished Aug 01 05:35:59 PM PDT 24
Peak memory 215552 kb
Host smart-592c98f1-8995-4f03-8ce2-70c83e7e69f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816636068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.816636068
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2902757134
Short name T102
Test name
Test status
Simulation time 58191558 ps
CPU time 3.81 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 217644 kb
Host smart-769e83ed-cc8f-4cc4-a95a-abaa6a8fce9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902757134 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2902757134
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3908847662
Short name T1050
Test name
Test status
Simulation time 132350119 ps
CPU time 0.72 seconds
Started Aug 01 05:36:06 PM PDT 24
Finished Aug 01 05:36:07 PM PDT 24
Peak memory 204300 kb
Host smart-03f2b78b-22ab-49b8-86b4-72758f782c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908847662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3908847662
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1196663927
Short name T1045
Test name
Test status
Simulation time 113669666 ps
CPU time 3.68 seconds
Started Aug 01 05:36:07 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 215496 kb
Host smart-35e04cfd-567d-4b5e-8a0f-a533a05513ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196663927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1196663927
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3316999515
Short name T1075
Test name
Test status
Simulation time 440933729 ps
CPU time 6.16 seconds
Started Aug 01 05:36:03 PM PDT 24
Finished Aug 01 05:36:09 PM PDT 24
Peak memory 215744 kb
Host smart-34901392-d61e-4435-97a1-b94e1c6c944e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316999515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3316999515
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3751745808
Short name T170
Test name
Test status
Simulation time 673898637 ps
CPU time 14.68 seconds
Started Aug 01 05:36:05 PM PDT 24
Finished Aug 01 05:36:20 PM PDT 24
Peak memory 216908 kb
Host smart-6038fa55-c50d-4476-8111-6569efcd6ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751745808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3751745808
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2925693525
Short name T1145
Test name
Test status
Simulation time 193146997 ps
CPU time 3.39 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 217336 kb
Host smart-7eec82ba-4b6e-4980-8c48-21b7350bf0ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925693525 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2925693525
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.697972735
Short name T1068
Test name
Test status
Simulation time 181420850 ps
CPU time 1.33 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 207356 kb
Host smart-f834a2e8-92df-4961-81ce-405df93c925c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697972735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.697972735
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.417714173
Short name T1054
Test name
Test status
Simulation time 13640784 ps
CPU time 0.68 seconds
Started Aug 01 05:36:04 PM PDT 24
Finished Aug 01 05:36:05 PM PDT 24
Peak memory 203940 kb
Host smart-3f3d838c-fca1-43c8-a335-d4cd5fdb6602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417714173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.417714173
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3344076753
Short name T156
Test name
Test status
Simulation time 138296235 ps
CPU time 3.15 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 215476 kb
Host smart-9843a0ec-4ecd-4191-bd11-6d33251248a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344076753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3344076753
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2162994381
Short name T112
Test name
Test status
Simulation time 188537113 ps
CPU time 4.64 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 215728 kb
Host smart-04779f0b-6ae9-46a7-a3fb-a193f32dedef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162994381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2162994381
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3759108500
Short name T177
Test name
Test status
Simulation time 1244303555 ps
CPU time 8.13 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 223596 kb
Host smart-e6827b16-f033-4229-84c8-170261a05145
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759108500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3759108500
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3177330574
Short name T118
Test name
Test status
Simulation time 186806976 ps
CPU time 2.9 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 216928 kb
Host smart-4e5f7714-ab4e-4dca-9453-a0d897817976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177330574 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3177330574
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2152696264
Short name T148
Test name
Test status
Simulation time 150016856 ps
CPU time 1.29 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:02 PM PDT 24
Peak memory 215500 kb
Host smart-887be65f-d30e-49c0-8f8f-76a0e5cfc365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152696264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2152696264
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4129571942
Short name T1077
Test name
Test status
Simulation time 93229800 ps
CPU time 0.72 seconds
Started Aug 01 05:36:07 PM PDT 24
Finished Aug 01 05:36:08 PM PDT 24
Peak memory 204304 kb
Host smart-2a3aaf43-4c7f-4fb2-938d-5a322a69d881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129571942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4129571942
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2228974404
Short name T1082
Test name
Test status
Simulation time 158259673 ps
CPU time 3.98 seconds
Started Aug 01 05:36:03 PM PDT 24
Finished Aug 01 05:36:07 PM PDT 24
Peak memory 215520 kb
Host smart-b04305fe-8197-424c-a9d2-d6b5f5e2c92f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228974404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2228974404
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1069365043
Short name T1103
Test name
Test status
Simulation time 559386894 ps
CPU time 3.42 seconds
Started Aug 01 05:35:57 PM PDT 24
Finished Aug 01 05:36:01 PM PDT 24
Peak memory 215760 kb
Host smart-1b512f74-2cea-44cb-baf0-a4d80ad8e06d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069365043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1069365043
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1639470407
Short name T1073
Test name
Test status
Simulation time 1466093797 ps
CPU time 7.5 seconds
Started Aug 01 05:35:57 PM PDT 24
Finished Aug 01 05:36:05 PM PDT 24
Peak memory 215504 kb
Host smart-5cb01180-ad90-45f0-b0b5-60798e87be5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639470407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1639470407
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1391939806
Short name T117
Test name
Test status
Simulation time 308112198 ps
CPU time 3.88 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:06 PM PDT 24
Peak memory 217756 kb
Host smart-9171567c-bee7-42c0-a8b1-91e49e727b69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391939806 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1391939806
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1685011888
Short name T130
Test name
Test status
Simulation time 1010463025 ps
CPU time 3.06 seconds
Started Aug 01 05:36:03 PM PDT 24
Finished Aug 01 05:36:06 PM PDT 24
Peak memory 215560 kb
Host smart-a059af92-5014-42ef-9b91-0a4287b78319
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685011888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1685011888
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.92213888
Short name T1028
Test name
Test status
Simulation time 14253176 ps
CPU time 0.71 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:00 PM PDT 24
Peak memory 203880 kb
Host smart-ad4fe54e-01d9-42d1-afd4-6f03ff8838d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92213888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.92213888
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2777647111
Short name T145
Test name
Test status
Simulation time 31223712 ps
CPU time 1.83 seconds
Started Aug 01 05:35:58 PM PDT 24
Finished Aug 01 05:36:00 PM PDT 24
Peak memory 215476 kb
Host smart-4d2709a0-da20-4b00-aa79-e1680187bd7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777647111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2777647111
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3284685061
Short name T1135
Test name
Test status
Simulation time 126908084 ps
CPU time 2.4 seconds
Started Aug 01 05:36:06 PM PDT 24
Finished Aug 01 05:36:09 PM PDT 24
Peak memory 215732 kb
Host smart-0c1b0c8d-33f9-4502-b18a-315af097978c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284685061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3284685061
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1455011085
Short name T168
Test name
Test status
Simulation time 109786676 ps
CPU time 7.11 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:07 PM PDT 24
Peak memory 216976 kb
Host smart-eb40839c-2fd4-47e1-9f97-9bc72843667c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455011085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1455011085
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2524065669
Short name T115
Test name
Test status
Simulation time 194987420 ps
CPU time 3.66 seconds
Started Aug 01 05:36:07 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 217424 kb
Host smart-d2ee8ee4-679e-4831-b655-f45abb25b88d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524065669 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2524065669
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.719904567
Short name T1095
Test name
Test status
Simulation time 114895786 ps
CPU time 2.76 seconds
Started Aug 01 05:36:15 PM PDT 24
Finished Aug 01 05:36:18 PM PDT 24
Peak memory 215444 kb
Host smart-3f6baa12-0d0f-4e91-a107-f05d86944d41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719904567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.719904567
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2869642531
Short name T1079
Test name
Test status
Simulation time 14979651 ps
CPU time 0.7 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 204028 kb
Host smart-5c62bfdb-ab9c-4766-bed1-c68bdcb782fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869642531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2869642531
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.731845410
Short name T1076
Test name
Test status
Simulation time 129782538 ps
CPU time 2.86 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 215920 kb
Host smart-1de2c8df-4349-4de8-b10d-2bb93c400fee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731845410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.731845410
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3683804599
Short name T166
Test name
Test status
Simulation time 234067580 ps
CPU time 4.94 seconds
Started Aug 01 05:36:04 PM PDT 24
Finished Aug 01 05:36:09 PM PDT 24
Peak memory 215776 kb
Host smart-7a30ec74-c1e1-4b87-a7d1-80bd7fa07ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683804599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3683804599
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.538972905
Short name T174
Test name
Test status
Simulation time 1174520156 ps
CPU time 14.81 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 216004 kb
Host smart-d7d23fd9-b838-4af1-95e8-1f7b1fab73fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538972905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.538972905
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2127659813
Short name T1113
Test name
Test status
Simulation time 75032403 ps
CPU time 1.79 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 215672 kb
Host smart-ccf3d337-2129-47ac-b98e-5694f734cc0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127659813 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2127659813
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1584208217
Short name T1138
Test name
Test status
Simulation time 109569640 ps
CPU time 1.89 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 215540 kb
Host smart-3d54f505-be41-4ea7-a744-bf30d380ab23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584208217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1584208217
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1066004000
Short name T1107
Test name
Test status
Simulation time 45953140 ps
CPU time 0.69 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 203932 kb
Host smart-4b455eb0-3aff-4f54-afc5-21919f6a5dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066004000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1066004000
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1590492750
Short name T1048
Test name
Test status
Simulation time 26500404 ps
CPU time 1.67 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 215560 kb
Host smart-775240ae-3202-4b2c-832f-5130a1bd111e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590492750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1590492750
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3215601075
Short name T1144
Test name
Test status
Simulation time 52570793 ps
CPU time 1.92 seconds
Started Aug 01 05:36:08 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 215748 kb
Host smart-c929e93a-fd58-4813-89dd-91721cac9f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215601075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3215601075
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3122982119
Short name T1108
Test name
Test status
Simulation time 1102751972 ps
CPU time 14.62 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:24 PM PDT 24
Peak memory 223700 kb
Host smart-e8a32bcd-72d6-4581-80e5-33e2a2ac11ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122982119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3122982119
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1143922092
Short name T1101
Test name
Test status
Simulation time 488019682 ps
CPU time 3.51 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 217184 kb
Host smart-1b6bc9ea-97ec-42ac-8b2b-3df2d45562e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143922092 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1143922092
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.646974745
Short name T1087
Test name
Test status
Simulation time 102242467 ps
CPU time 2.52 seconds
Started Aug 01 05:36:16 PM PDT 24
Finished Aug 01 05:36:18 PM PDT 24
Peak memory 215496 kb
Host smart-aa2df740-72f7-45e7-886e-3cd3b8a78854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646974745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.646974745
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3703272586
Short name T1120
Test name
Test status
Simulation time 15205758 ps
CPU time 0.73 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 204292 kb
Host smart-91423aee-14bf-4a58-9726-ed7229f6d558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703272586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3703272586
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1971798578
Short name T1072
Test name
Test status
Simulation time 155037896 ps
CPU time 2.69 seconds
Started Aug 01 05:36:08 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 215384 kb
Host smart-a3caeaf4-5a48-447f-8f4d-6d944e23b77f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971798578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1971798578
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2111866474
Short name T1065
Test name
Test status
Simulation time 698615226 ps
CPU time 3.1 seconds
Started Aug 01 05:36:06 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 215664 kb
Host smart-0cdbb90c-09be-4abb-9d22-4400a132c427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111866474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2111866474
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4223547302
Short name T1146
Test name
Test status
Simulation time 734238553 ps
CPU time 8.52 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:19 PM PDT 24
Peak memory 216128 kb
Host smart-9624a5ac-2040-4220-af85-b7836341bf32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223547302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4223547302
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3769952475
Short name T1052
Test name
Test status
Simulation time 55446829 ps
CPU time 1.88 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:14 PM PDT 24
Peak memory 216480 kb
Host smart-69cec70a-8769-433f-a2c3-dabbef9946db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769952475 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3769952475
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1764593775
Short name T124
Test name
Test status
Simulation time 2011728786 ps
CPU time 2.54 seconds
Started Aug 01 05:36:13 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 215524 kb
Host smart-ba846178-ac3a-4fb2-b2e8-38ea4917fe91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764593775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1764593775
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.580420383
Short name T1142
Test name
Test status
Simulation time 13787980 ps
CPU time 0.73 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 204244 kb
Host smart-bea1d3b4-d6de-4bcb-a5e4-b6e52308e8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580420383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.580420383
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1109723606
Short name T1125
Test name
Test status
Simulation time 48478521 ps
CPU time 1.69 seconds
Started Aug 01 05:36:06 PM PDT 24
Finished Aug 01 05:36:08 PM PDT 24
Peak memory 215420 kb
Host smart-7ac31647-22f9-4843-b638-a496b6460cec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109723606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1109723606
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1901447555
Short name T1100
Test name
Test status
Simulation time 236264528 ps
CPU time 3.11 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 215788 kb
Host smart-a67da3c3-e861-40f7-ad56-808ea5bdfbf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901447555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1901447555
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2902095999
Short name T173
Test name
Test status
Simulation time 1217895261 ps
CPU time 19.55 seconds
Started Aug 01 05:36:08 PM PDT 24
Finished Aug 01 05:36:28 PM PDT 24
Peak memory 215400 kb
Host smart-4151ad53-20ed-4664-bc56-d2400f82d900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902095999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2902095999
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1264895166
Short name T119
Test name
Test status
Simulation time 28176869 ps
CPU time 1.88 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 215676 kb
Host smart-69062809-0e89-42a5-90b2-54c71222f894
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264895166 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1264895166
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4258115069
Short name T1057
Test name
Test status
Simulation time 38345837 ps
CPU time 2.46 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 215544 kb
Host smart-ebebc42b-185a-494b-ac97-aa1c133c2117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258115069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4258115069
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3228967463
Short name T1027
Test name
Test status
Simulation time 19264757 ps
CPU time 0.75 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 204252 kb
Host smart-8cad3f4d-4690-4614-81cf-c64be7e9b81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228967463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3228967463
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2388582033
Short name T1039
Test name
Test status
Simulation time 58902455 ps
CPU time 1.72 seconds
Started Aug 01 05:36:06 PM PDT 24
Finished Aug 01 05:36:08 PM PDT 24
Peak memory 215520 kb
Host smart-c7d3ad13-78b9-4089-856b-24c4c5ddb794
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388582033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2388582033
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4276721993
Short name T1098
Test name
Test status
Simulation time 1690334052 ps
CPU time 6.1 seconds
Started Aug 01 05:36:18 PM PDT 24
Finished Aug 01 05:36:24 PM PDT 24
Peak memory 216216 kb
Host smart-6a4cd6cd-ff07-43b0-8018-46ef94550351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276721993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4276721993
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3629686983
Short name T1056
Test name
Test status
Simulation time 1138400142 ps
CPU time 2.47 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 216520 kb
Host smart-eb916b60-e028-41d7-9277-8242a34debfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629686983 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3629686983
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1704312968
Short name T1081
Test name
Test status
Simulation time 60986938 ps
CPU time 1.73 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 215524 kb
Host smart-9b239a46-ff26-4de9-95b5-31c26b6259b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704312968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1704312968
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1915127388
Short name T1126
Test name
Test status
Simulation time 34152745 ps
CPU time 0.76 seconds
Started Aug 01 05:36:16 PM PDT 24
Finished Aug 01 05:36:17 PM PDT 24
Peak memory 203964 kb
Host smart-2c8e0ef6-8d13-45fb-b50a-dab399083aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915127388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1915127388
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1585496772
Short name T1139
Test name
Test status
Simulation time 151211077 ps
CPU time 2.88 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:14 PM PDT 24
Peak memory 216072 kb
Host smart-fac0dfc1-fc48-4907-ab51-22ddab443570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585496772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1585496772
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.342353310
Short name T114
Test name
Test status
Simulation time 104656693 ps
CPU time 3.6 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 216672 kb
Host smart-f6b2c19d-99d9-4e4a-ad48-d6e21f9f96eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342353310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.342353310
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3901464942
Short name T171
Test name
Test status
Simulation time 1385589657 ps
CPU time 12.18 seconds
Started Aug 01 05:36:15 PM PDT 24
Finished Aug 01 05:36:27 PM PDT 24
Peak memory 215456 kb
Host smart-3931e724-9111-4750-8d6f-b661b4990f37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901464942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3901464942
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2256375631
Short name T1071
Test name
Test status
Simulation time 1099561001 ps
CPU time 20.43 seconds
Started Aug 01 05:35:50 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 215480 kb
Host smart-ac9529e1-a072-4361-bf59-a50f5cf201c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256375631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2256375631
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1165330035
Short name T1106
Test name
Test status
Simulation time 5204061522 ps
CPU time 38.34 seconds
Started Aug 01 05:35:50 PM PDT 24
Finished Aug 01 05:36:28 PM PDT 24
Peak memory 207360 kb
Host smart-4ca6b907-bdb9-4a33-99d9-975951725d0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165330035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1165330035
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.879220950
Short name T81
Test name
Test status
Simulation time 80473480 ps
CPU time 1.31 seconds
Started Aug 01 05:35:47 PM PDT 24
Finished Aug 01 05:35:48 PM PDT 24
Peak memory 206536 kb
Host smart-6f074c3b-c88b-4599-875d-1a68e3039aae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879220950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.879220950
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1568417336
Short name T1121
Test name
Test status
Simulation time 110337859 ps
CPU time 1.97 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:55 PM PDT 24
Peak memory 216592 kb
Host smart-df60d5cd-f3a1-4540-ac3f-f8857c11667e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568417336 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1568417336
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3104621420
Short name T1141
Test name
Test status
Simulation time 68779002 ps
CPU time 1.25 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:35:54 PM PDT 24
Peak memory 207376 kb
Host smart-b437883d-0ad2-41a5-8afa-a0d1faec3b14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104621420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
104621420
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4244682336
Short name T1058
Test name
Test status
Simulation time 15734164 ps
CPU time 0.75 seconds
Started Aug 01 05:35:48 PM PDT 24
Finished Aug 01 05:35:50 PM PDT 24
Peak memory 203940 kb
Host smart-57b4446c-de6a-440a-97ba-53508c252d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244682336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
244682336
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3566050083
Short name T1148
Test name
Test status
Simulation time 172893254 ps
CPU time 1.74 seconds
Started Aug 01 05:35:52 PM PDT 24
Finished Aug 01 05:35:54 PM PDT 24
Peak memory 215548 kb
Host smart-60892b0c-5995-4ab8-8f96-929dca415d96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566050083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3566050083
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2233785561
Short name T1064
Test name
Test status
Simulation time 13506373 ps
CPU time 0.67 seconds
Started Aug 01 05:35:51 PM PDT 24
Finished Aug 01 05:35:51 PM PDT 24
Peak memory 204240 kb
Host smart-05a267a3-3f0c-460f-a359-c8426489e9cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233785561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2233785561
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3153582642
Short name T147
Test name
Test status
Simulation time 111436262 ps
CPU time 3.2 seconds
Started Aug 01 05:35:54 PM PDT 24
Finished Aug 01 05:35:57 PM PDT 24
Peak memory 215488 kb
Host smart-67111010-f498-455f-978d-56d55b7683b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153582642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3153582642
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3031606975
Short name T1085
Test name
Test status
Simulation time 629957941 ps
CPU time 3.97 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:57 PM PDT 24
Peak memory 215716 kb
Host smart-2bfebfd8-8054-4c1c-a8db-162cdb0ae7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031606975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
031606975
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2968968387
Short name T101
Test name
Test status
Simulation time 15452264053 ps
CPU time 24.87 seconds
Started Aug 01 05:35:50 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 215716 kb
Host smart-2a81831a-89b8-48cc-8cec-e50f2b2c90ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968968387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2968968387
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1203070346
Short name T1117
Test name
Test status
Simulation time 18335672 ps
CPU time 0.7 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:09 PM PDT 24
Peak memory 203992 kb
Host smart-969d1ef3-a6b8-462b-8a1e-64368d3041e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203070346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1203070346
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.982106831
Short name T1038
Test name
Test status
Simulation time 11734031 ps
CPU time 0.76 seconds
Started Aug 01 05:36:16 PM PDT 24
Finished Aug 01 05:36:17 PM PDT 24
Peak memory 203964 kb
Host smart-cb0f4bf7-ae4c-4ddf-94f7-48db14845445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982106831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.982106831
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1244237324
Short name T1089
Test name
Test status
Simulation time 33111194 ps
CPU time 0.7 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 204320 kb
Host smart-06ac3d1b-eeca-4833-b07a-c8775f8638b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244237324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1244237324
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4205120661
Short name T1131
Test name
Test status
Simulation time 12969578 ps
CPU time 0.69 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 204332 kb
Host smart-9a0d98b9-87f2-4e00-834e-0d5d32c8ed9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205120661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4205120661
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.286412373
Short name T1035
Test name
Test status
Simulation time 11963681 ps
CPU time 0.7 seconds
Started Aug 01 05:36:08 PM PDT 24
Finished Aug 01 05:36:09 PM PDT 24
Peak memory 203960 kb
Host smart-86081032-95c2-4d63-bcf9-10953927e97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286412373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.286412373
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1911264651
Short name T1037
Test name
Test status
Simulation time 43580550 ps
CPU time 0.7 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 203856 kb
Host smart-063032fc-175f-443e-aa94-5f32b3067a6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911264651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1911264651
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.888999758
Short name T1115
Test name
Test status
Simulation time 44521427 ps
CPU time 0.68 seconds
Started Aug 01 05:36:07 PM PDT 24
Finished Aug 01 05:36:08 PM PDT 24
Peak memory 204004 kb
Host smart-e9ebfb60-3cf2-44ae-9c8a-d244fead0ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888999758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.888999758
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1392789700
Short name T1123
Test name
Test status
Simulation time 53140089 ps
CPU time 0.67 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 204268 kb
Host smart-c8895d1e-1914-4bb9-a35e-b6e49e898f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392789700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1392789700
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1462138350
Short name T1061
Test name
Test status
Simulation time 17712718 ps
CPU time 0.75 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 203992 kb
Host smart-81a2ac9d-37bb-4cc8-bd5c-3dd237b82a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462138350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1462138350
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4234131152
Short name T1031
Test name
Test status
Simulation time 17521844 ps
CPU time 0.76 seconds
Started Aug 01 05:36:08 PM PDT 24
Finished Aug 01 05:36:08 PM PDT 24
Peak memory 203908 kb
Host smart-1beaad8f-075d-4668-af4a-aae2064181e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234131152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4234131152
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1652770352
Short name T1099
Test name
Test status
Simulation time 4585200193 ps
CPU time 22.93 seconds
Started Aug 01 05:35:47 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 215516 kb
Host smart-f3b674e0-f8f8-4bed-8280-787fda41f39b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652770352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1652770352
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3502946089
Short name T131
Test name
Test status
Simulation time 3579185112 ps
CPU time 11.81 seconds
Started Aug 01 05:35:54 PM PDT 24
Finished Aug 01 05:36:06 PM PDT 24
Peak memory 215624 kb
Host smart-3ce32872-9443-4191-a363-a152a1a82092
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502946089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3502946089
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4203856676
Short name T1030
Test name
Test status
Simulation time 18797098 ps
CPU time 1.16 seconds
Started Aug 01 05:35:51 PM PDT 24
Finished Aug 01 05:35:52 PM PDT 24
Peak memory 207252 kb
Host smart-c2f1dcfa-a79a-44da-bba3-c234efa81518
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203856676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4203856676
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3565743037
Short name T1067
Test name
Test status
Simulation time 106762514 ps
CPU time 3.76 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:58 PM PDT 24
Peak memory 217984 kb
Host smart-648f41c9-0c25-4355-9ca6-287b46789b48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565743037 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3565743037
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2220994068
Short name T1122
Test name
Test status
Simulation time 132056069 ps
CPU time 2.14 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:56 PM PDT 24
Peak memory 215516 kb
Host smart-2b0f9a10-4a4c-4e68-b79a-43ce0cb012d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220994068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
220994068
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2132087521
Short name T1127
Test name
Test status
Simulation time 26423141 ps
CPU time 0.71 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:54 PM PDT 24
Peak memory 203968 kb
Host smart-95c24aeb-0f98-4669-8754-c8b9f0c47b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132087521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
132087521
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3059714074
Short name T1044
Test name
Test status
Simulation time 76937195 ps
CPU time 1.46 seconds
Started Aug 01 05:35:50 PM PDT 24
Finished Aug 01 05:35:52 PM PDT 24
Peak memory 215388 kb
Host smart-7d21f11b-2c39-4d88-9416-04a6b4ecfdfb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059714074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3059714074
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1607859625
Short name T1036
Test name
Test status
Simulation time 12547975 ps
CPU time 0.65 seconds
Started Aug 01 05:35:51 PM PDT 24
Finished Aug 01 05:35:52 PM PDT 24
Peak memory 203824 kb
Host smart-4ad8c2dd-f5f0-4c58-95c8-4feea343f1cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607859625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1607859625
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1244249381
Short name T1114
Test name
Test status
Simulation time 135416963 ps
CPU time 1.78 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:35:56 PM PDT 24
Peak memory 215640 kb
Host smart-b9a15bc4-be8e-4ba4-909d-3ea2b39556f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244249381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1244249381
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.540502145
Short name T172
Test name
Test status
Simulation time 700477057 ps
CPU time 16.02 seconds
Started Aug 01 05:35:53 PM PDT 24
Finished Aug 01 05:36:09 PM PDT 24
Peak memory 216992 kb
Host smart-16fa8ebc-4282-4c95-aa38-ff306facb93a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540502145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.540502145
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1117623971
Short name T1102
Test name
Test status
Simulation time 15423296 ps
CPU time 0.73 seconds
Started Aug 01 05:36:15 PM PDT 24
Finished Aug 01 05:36:16 PM PDT 24
Peak memory 203968 kb
Host smart-6c331296-8340-4e45-acd9-015829e2d381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117623971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1117623971
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3123565895
Short name T1041
Test name
Test status
Simulation time 33099801 ps
CPU time 0.71 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 204320 kb
Host smart-ccd0be99-d494-484b-bdcc-62b356b3c323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123565895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3123565895
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3976363677
Short name T1066
Test name
Test status
Simulation time 14466232 ps
CPU time 0.77 seconds
Started Aug 01 05:36:13 PM PDT 24
Finished Aug 01 05:36:14 PM PDT 24
Peak memory 204324 kb
Host smart-ecf767e9-3764-42fb-a97a-ece1ccd745ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976363677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3976363677
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3647409927
Short name T1040
Test name
Test status
Simulation time 57439974 ps
CPU time 0.75 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 203964 kb
Host smart-f9de58ac-2692-4fec-b699-48713a8e1c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647409927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3647409927
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3330385654
Short name T1111
Test name
Test status
Simulation time 57639593 ps
CPU time 0.74 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 203952 kb
Host smart-74a73140-3153-4de9-af7e-b79fd25ac1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330385654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3330385654
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.531280622
Short name T1147
Test name
Test status
Simulation time 23777693 ps
CPU time 0.72 seconds
Started Aug 01 05:36:12 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 204320 kb
Host smart-a24e4357-3d01-47cd-8441-46bfd2f6bdf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531280622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.531280622
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.31897076
Short name T1047
Test name
Test status
Simulation time 49604422 ps
CPU time 0.7 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 203932 kb
Host smart-b9ad2bdc-1304-4859-ab0f-560974137f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31897076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.31897076
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2602260778
Short name T1032
Test name
Test status
Simulation time 35943908 ps
CPU time 0.69 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 204300 kb
Host smart-2b61af78-0923-4a1e-a0f7-9bf723d8f87a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602260778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2602260778
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3057355208
Short name T1116
Test name
Test status
Simulation time 12177134 ps
CPU time 0.73 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 204000 kb
Host smart-00447d2d-6dfb-449e-a893-750a0a780c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057355208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3057355208
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.188145858
Short name T1034
Test name
Test status
Simulation time 11744948 ps
CPU time 0.75 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 203984 kb
Host smart-b8df5ae7-a7d0-4106-acbf-683443099796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188145858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.188145858
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2990888289
Short name T1149
Test name
Test status
Simulation time 110375839 ps
CPU time 7.28 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 207280 kb
Host smart-8721b43c-df3c-431b-b1a6-5062ea3f4ef4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990888289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2990888289
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.927503593
Short name T129
Test name
Test status
Simulation time 5257449451 ps
CPU time 12.56 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:15 PM PDT 24
Peak memory 207372 kb
Host smart-b40b5882-fe3d-40f2-9036-ae56cfd18ffa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927503593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.927503593
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.358633212
Short name T80
Test name
Test status
Simulation time 69854208 ps
CPU time 1.19 seconds
Started Aug 01 05:35:58 PM PDT 24
Finished Aug 01 05:36:00 PM PDT 24
Peak memory 207204 kb
Host smart-0449dcb8-d2ca-4a70-8241-66fe498f0167
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358633212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.358633212
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3783139752
Short name T1110
Test name
Test status
Simulation time 455575817 ps
CPU time 2.59 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:02 PM PDT 24
Peak memory 216496 kb
Host smart-39d7ed79-0a6a-4a16-89e9-25fed444d6f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783139752 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3783139752
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1258888271
Short name T1080
Test name
Test status
Simulation time 40108776 ps
CPU time 1.41 seconds
Started Aug 01 05:36:03 PM PDT 24
Finished Aug 01 05:36:05 PM PDT 24
Peak memory 207280 kb
Host smart-e4c4305f-8a30-4064-98e3-909e7d768bac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258888271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
258888271
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4134512486
Short name T1043
Test name
Test status
Simulation time 28808025 ps
CPU time 0.76 seconds
Started Aug 01 05:35:58 PM PDT 24
Finished Aug 01 05:35:59 PM PDT 24
Peak memory 204276 kb
Host smart-ec284f92-ab29-4e8f-979c-32b139bdddcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134512486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
134512486
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3128265260
Short name T123
Test name
Test status
Simulation time 54958607 ps
CPU time 1.79 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:01 PM PDT 24
Peak memory 215508 kb
Host smart-41c400a5-2870-4508-ba65-110a962e5be1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128265260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3128265260
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4085345255
Short name T1118
Test name
Test status
Simulation time 26783109 ps
CPU time 0.65 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:00 PM PDT 24
Peak memory 203908 kb
Host smart-60ef9b45-d32d-4601-a61d-6d49279167c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085345255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4085345255
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2807409610
Short name T1078
Test name
Test status
Simulation time 158294294 ps
CPU time 4.14 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 215444 kb
Host smart-4dc008aa-b6df-4d10-9f06-93005896c57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807409610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2807409610
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.909558350
Short name T111
Test name
Test status
Simulation time 242793322 ps
CPU time 5.61 seconds
Started Aug 01 05:35:54 PM PDT 24
Finished Aug 01 05:36:00 PM PDT 24
Peak memory 215800 kb
Host smart-5e1048b6-32ab-4bd5-aab5-d6bc3163c392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909558350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.909558350
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3583484571
Short name T1088
Test name
Test status
Simulation time 685857460 ps
CPU time 6.66 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:06 PM PDT 24
Peak memory 215712 kb
Host smart-7c85bd03-b218-4202-9a66-f6a6e636b80a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583484571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3583484571
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2925159
Short name T1134
Test name
Test status
Simulation time 14622255 ps
CPU time 0.73 seconds
Started Aug 01 05:36:08 PM PDT 24
Finished Aug 01 05:36:09 PM PDT 24
Peak memory 204320 kb
Host smart-fbc5144d-b0a4-409c-b62e-edfea13b2679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.2925159
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1031380805
Short name T1097
Test name
Test status
Simulation time 43920485 ps
CPU time 0.74 seconds
Started Aug 01 05:36:15 PM PDT 24
Finished Aug 01 05:36:16 PM PDT 24
Peak memory 204272 kb
Host smart-89aa5ec9-26f8-4ce4-84d6-8705d59144e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031380805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1031380805
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2652976558
Short name T1130
Test name
Test status
Simulation time 24968379 ps
CPU time 0.71 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 204288 kb
Host smart-42deb515-4e22-4209-a35e-63a66c92d006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652976558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2652976558
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4142062074
Short name T1060
Test name
Test status
Simulation time 12555052 ps
CPU time 0.7 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 203896 kb
Host smart-f4c1c136-ebd1-4b80-b6df-cd4321e5eed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142062074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4142062074
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2938973045
Short name T1128
Test name
Test status
Simulation time 25585341 ps
CPU time 0.76 seconds
Started Aug 01 05:36:16 PM PDT 24
Finished Aug 01 05:36:17 PM PDT 24
Peak memory 203940 kb
Host smart-2599b908-442b-4acf-80b5-340785b4606b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938973045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2938973045
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3984534171
Short name T1049
Test name
Test status
Simulation time 35133620 ps
CPU time 0.68 seconds
Started Aug 01 05:36:15 PM PDT 24
Finished Aug 01 05:36:16 PM PDT 24
Peak memory 203972 kb
Host smart-59f37c36-7976-4e54-8068-ca23a21288b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984534171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3984534171
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.203740511
Short name T1069
Test name
Test status
Simulation time 11666676 ps
CPU time 0.72 seconds
Started Aug 01 05:36:07 PM PDT 24
Finished Aug 01 05:36:07 PM PDT 24
Peak memory 203956 kb
Host smart-2698cdc9-28fd-4729-92d4-b7dc1bbd1ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203740511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.203740511
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1231594853
Short name T1086
Test name
Test status
Simulation time 15372568 ps
CPU time 0.74 seconds
Started Aug 01 05:36:09 PM PDT 24
Finished Aug 01 05:36:10 PM PDT 24
Peak memory 203984 kb
Host smart-7c4a0a59-8e69-433b-a62f-2c9e7af536e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231594853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1231594853
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.642792181
Short name T1033
Test name
Test status
Simulation time 11536090 ps
CPU time 0.76 seconds
Started Aug 01 05:36:11 PM PDT 24
Finished Aug 01 05:36:12 PM PDT 24
Peak memory 204288 kb
Host smart-7eea96aa-8a8a-4400-8c53-e9fb4b61064d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642792181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.642792181
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1483530922
Short name T1059
Test name
Test status
Simulation time 125672303 ps
CPU time 0.7 seconds
Started Aug 01 05:36:10 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 203988 kb
Host smart-faa20b9f-7845-4e43-bc7e-2e80f079e87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483530922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1483530922
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4086286698
Short name T1132
Test name
Test status
Simulation time 131250550 ps
CPU time 3.8 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:06 PM PDT 24
Peak memory 217932 kb
Host smart-d7bd111d-6667-4a8c-a3fc-2d7b2fe1cc88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086286698 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4086286698
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3271851773
Short name T1105
Test name
Test status
Simulation time 160526064 ps
CPU time 1.37 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 207260 kb
Host smart-dd02f46e-09ce-442d-be3c-917532c7258c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271851773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
271851773
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2314304408
Short name T1070
Test name
Test status
Simulation time 13229441 ps
CPU time 0.72 seconds
Started Aug 01 05:36:03 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 204280 kb
Host smart-e275a4ce-3d84-474a-8393-cf66aabe1a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314304408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
314304408
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3382997516
Short name T1137
Test name
Test status
Simulation time 181229989 ps
CPU time 1.83 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 215492 kb
Host smart-30a00eaf-f68e-4633-a1b7-b7dd45110887
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382997516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3382997516
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2150433252
Short name T1074
Test name
Test status
Simulation time 370861260 ps
CPU time 4.71 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:05 PM PDT 24
Peak memory 215860 kb
Host smart-44f47303-3b95-4b63-9ff2-7024db1cf90f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150433252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
150433252
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3096974348
Short name T175
Test name
Test status
Simulation time 399347456 ps
CPU time 12.75 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:13 PM PDT 24
Peak memory 215752 kb
Host smart-68965405-fac0-482d-b7ce-b630cd631424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096974348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3096974348
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3990913707
Short name T1124
Test name
Test status
Simulation time 61072324 ps
CPU time 1.72 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 215592 kb
Host smart-e63c5cff-a235-4a8e-8b16-03721ba3844c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990913707 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3990913707
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.862286712
Short name T122
Test name
Test status
Simulation time 163635304 ps
CPU time 2.71 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:01 PM PDT 24
Peak memory 215528 kb
Host smart-66b6eb2b-d8dc-45f4-82ba-ca714670b72a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862286712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.862286712
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1536023523
Short name T1053
Test name
Test status
Simulation time 139643207 ps
CPU time 0.79 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:01 PM PDT 24
Peak memory 204056 kb
Host smart-6e97ba99-d1b5-497c-9f2b-252f5fa04522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536023523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
536023523
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3650125974
Short name T1133
Test name
Test status
Simulation time 552877339 ps
CPU time 3.14 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 215536 kb
Host smart-b939d741-d1d6-4d5e-8caa-49e14a3df392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650125974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3650125974
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.46545190
Short name T103
Test name
Test status
Simulation time 698228822 ps
CPU time 4.75 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 216792 kb
Host smart-f10dec85-b8f3-43f0-8ef6-a768ca3a90ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46545190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.46545190
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.157066910
Short name T1091
Test name
Test status
Simulation time 98301750 ps
CPU time 3.82 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:05 PM PDT 24
Peak memory 217652 kb
Host smart-cff9fca0-8a3c-4cd3-a9df-0ea9b2f9f588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157066910 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.157066910
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1601576747
Short name T1094
Test name
Test status
Simulation time 23385147 ps
CPU time 1.36 seconds
Started Aug 01 05:36:02 PM PDT 24
Finished Aug 01 05:36:04 PM PDT 24
Peak memory 207336 kb
Host smart-c0d809c4-e47e-4a83-b87f-e90cbac67602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601576747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
601576747
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.867912511
Short name T1083
Test name
Test status
Simulation time 68343831 ps
CPU time 0.66 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:01 PM PDT 24
Peak memory 204008 kb
Host smart-6a3223d9-f72e-4508-9371-6a1d8bcc9063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867912511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.867912511
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.729710827
Short name T1104
Test name
Test status
Simulation time 162669289 ps
CPU time 2.77 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 215484 kb
Host smart-8f1ad9df-0bfb-4624-a85b-b241dabdb1aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729710827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.729710827
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2728367088
Short name T110
Test name
Test status
Simulation time 139377434 ps
CPU time 2.26 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:02 PM PDT 24
Peak memory 215876 kb
Host smart-2e7678d4-63bf-4eda-a1c9-0730225794ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728367088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
728367088
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4266544964
Short name T169
Test name
Test status
Simulation time 276595658 ps
CPU time 7.47 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:08 PM PDT 24
Peak memory 216032 kb
Host smart-58653f07-b2e6-44b0-8bd7-3ad6f5236516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266544964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4266544964
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.773792242
Short name T1093
Test name
Test status
Simulation time 636978397 ps
CPU time 4.06 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 217256 kb
Host smart-14dee0e5-b6b7-4a86-bfdf-874c7f58743b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773792242 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.773792242
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3431131051
Short name T128
Test name
Test status
Simulation time 198965584 ps
CPU time 2.73 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 215560 kb
Host smart-8ea2da6f-68ed-4d5f-8233-db4112b34e3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431131051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
431131051
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2064553626
Short name T1046
Test name
Test status
Simulation time 44322828 ps
CPU time 0.72 seconds
Started Aug 01 05:35:58 PM PDT 24
Finished Aug 01 05:35:59 PM PDT 24
Peak memory 203876 kb
Host smart-0d7f8896-31f0-48b9-ae0d-acec452677c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064553626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
064553626
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1741454993
Short name T1055
Test name
Test status
Simulation time 418328216 ps
CPU time 2.88 seconds
Started Aug 01 05:36:00 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 215300 kb
Host smart-88f7f5f6-9a16-4a31-902c-3f43543ac963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741454993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1741454993
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3419814501
Short name T1096
Test name
Test status
Simulation time 55121813 ps
CPU time 3.18 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:05 PM PDT 24
Peak memory 215708 kb
Host smart-25cc811a-2562-4e2f-afe7-081d88009e20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419814501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
419814501
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.331048340
Short name T1092
Test name
Test status
Simulation time 197414938 ps
CPU time 3.49 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:02 PM PDT 24
Peak memory 217080 kb
Host smart-90c5cd79-c951-4964-a211-e89cd8c4120d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331048340 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.331048340
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2951919433
Short name T1042
Test name
Test status
Simulation time 258811080 ps
CPU time 1.92 seconds
Started Aug 01 05:36:01 PM PDT 24
Finished Aug 01 05:36:03 PM PDT 24
Peak memory 215592 kb
Host smart-02870994-7bd0-4446-aef4-f7e751238b21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951919433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
951919433
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2042439627
Short name T1051
Test name
Test status
Simulation time 25157572 ps
CPU time 0.74 seconds
Started Aug 01 05:35:59 PM PDT 24
Finished Aug 01 05:36:00 PM PDT 24
Peak memory 203968 kb
Host smart-e7d7ecb0-81de-4cd5-90bf-20b0b25d7f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042439627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
042439627
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.336233934
Short name T1084
Test name
Test status
Simulation time 45103698 ps
CPU time 2.64 seconds
Started Aug 01 05:36:06 PM PDT 24
Finished Aug 01 05:36:08 PM PDT 24
Peak memory 215500 kb
Host smart-881bbf7c-2211-4d51-9dda-214111dbf784
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336233934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.336233934
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3471187840
Short name T100
Test name
Test status
Simulation time 62028377 ps
CPU time 2.01 seconds
Started Aug 01 05:36:05 PM PDT 24
Finished Aug 01 05:36:07 PM PDT 24
Peak memory 215692 kb
Host smart-997c3318-1dd5-4beb-bbb2-6609c8e581df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471187840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
471187840
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3521815144
Short name T104
Test name
Test status
Simulation time 589902825 ps
CPU time 7.44 seconds
Started Aug 01 05:36:03 PM PDT 24
Finished Aug 01 05:36:11 PM PDT 24
Peak memory 215488 kb
Host smart-5be360a7-94cb-4b19-94b4-ff28e838a643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521815144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3521815144
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.820682425
Short name T548
Test name
Test status
Simulation time 14235243 ps
CPU time 0.76 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:42 PM PDT 24
Peak memory 206080 kb
Host smart-9b264014-d2eb-4868-8d5d-d3170196f4f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820682425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.820682425
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3608646453
Short name T241
Test name
Test status
Simulation time 201685387 ps
CPU time 3.12 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:44 PM PDT 24
Peak memory 233260 kb
Host smart-7779bccf-7c57-48c4-b65e-58e07fec7eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608646453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3608646453
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.981942787
Short name T874
Test name
Test status
Simulation time 14226460 ps
CPU time 0.77 seconds
Started Aug 01 05:15:20 PM PDT 24
Finished Aug 01 05:15:21 PM PDT 24
Peak memory 207276 kb
Host smart-bff7428a-d8cd-47b3-a464-034ac24d0a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981942787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.981942787
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4094799205
Short name T70
Test name
Test status
Simulation time 12150893655 ps
CPU time 52.6 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:16:34 PM PDT 24
Peak memory 249960 kb
Host smart-1cc48c02-70e6-440d-b5ab-b057aa5152eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094799205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4094799205
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3704410967
Short name T641
Test name
Test status
Simulation time 14147362433 ps
CPU time 59.25 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:16:41 PM PDT 24
Peak memory 250868 kb
Host smart-1f5669c8-05f0-4189-90c4-1e36ad5f99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704410967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3704410967
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4291779258
Short name T697
Test name
Test status
Simulation time 162237571 ps
CPU time 2.77 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:44 PM PDT 24
Peak memory 225096 kb
Host smart-43f748a2-4ee9-43b7-90ea-1d92ffaaa9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291779258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4291779258
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2681702675
Short name T16
Test name
Test status
Simulation time 38797189285 ps
CPU time 130.42 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:17:54 PM PDT 24
Peak memory 240656 kb
Host smart-242f609a-8f56-407f-92c3-ebe7738ec99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681702675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2681702675
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2817141285
Short name T943
Test name
Test status
Simulation time 6306053139 ps
CPU time 30.34 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:16:27 PM PDT 24
Peak memory 233504 kb
Host smart-15e7a9da-d04e-4c81-809c-b68ea4213dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817141285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2817141285
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3468388553
Short name T703
Test name
Test status
Simulation time 69072924 ps
CPU time 2.64 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 233312 kb
Host smart-1914bb1b-ca3f-4c76-acde-81ac633582fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468388553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3468388553
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2337169035
Short name T948
Test name
Test status
Simulation time 29627164 ps
CPU time 1.1 seconds
Started Aug 01 05:15:18 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 217116 kb
Host smart-3823b0ed-9664-485c-abde-3050cd80e87c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337169035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2337169035
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.193465108
Short name T986
Test name
Test status
Simulation time 571080887 ps
CPU time 6.59 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:48 PM PDT 24
Peak memory 241556 kb
Host smart-88a05e86-7bf3-4106-afbc-1ffc98c60f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193465108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
193465108
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3591649512
Short name T793
Test name
Test status
Simulation time 2050570441 ps
CPU time 4.71 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:15:45 PM PDT 24
Peak memory 233328 kb
Host smart-22458dbf-ad45-405f-ab32-08bf5d159b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591649512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3591649512
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3976635127
Short name T152
Test name
Test status
Simulation time 3222101701 ps
CPU time 6.52 seconds
Started Aug 01 05:15:39 PM PDT 24
Finished Aug 01 05:15:45 PM PDT 24
Peak memory 221000 kb
Host smart-bcb448d8-b6e4-49c8-9ef4-b965a12427bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3976635127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3976635127
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2615126971
Short name T819
Test name
Test status
Simulation time 82863696 ps
CPU time 1.06 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:44 PM PDT 24
Peak memory 215560 kb
Host smart-dcb94051-ee1e-413d-a8ef-1b8c450ede24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615126971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2615126971
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2853019432
Short name T318
Test name
Test status
Simulation time 2030017385 ps
CPU time 27.65 seconds
Started Aug 01 05:15:19 PM PDT 24
Finished Aug 01 05:15:47 PM PDT 24
Peak memory 217164 kb
Host smart-01b8c493-8ee1-4a94-aa7b-dc9977385ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853019432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2853019432
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3609955348
Short name T54
Test name
Test status
Simulation time 612261297 ps
CPU time 2.43 seconds
Started Aug 01 05:15:19 PM PDT 24
Finished Aug 01 05:15:21 PM PDT 24
Peak memory 216920 kb
Host smart-c2fd46d3-578d-4052-989e-ef5ad2820c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609955348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3609955348
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2804464022
Short name T913
Test name
Test status
Simulation time 522894330 ps
CPU time 8.12 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:15:48 PM PDT 24
Peak memory 216880 kb
Host smart-3118a7c0-646d-4125-a9b1-b1d62997f829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804464022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2804464022
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2436912742
Short name T394
Test name
Test status
Simulation time 166175465 ps
CPU time 0.71 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 206472 kb
Host smart-5fc48167-b70f-49ea-b3b7-7a04cdafe073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436912742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2436912742
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3170348027
Short name T897
Test name
Test status
Simulation time 1818149511 ps
CPU time 4.93 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 238572 kb
Host smart-b92f9f3a-2ba9-4ec1-b9c0-5f4c58d4d4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170348027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3170348027
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4255233273
Short name T727
Test name
Test status
Simulation time 15664588 ps
CPU time 0.74 seconds
Started Aug 01 05:15:44 PM PDT 24
Finished Aug 01 05:15:45 PM PDT 24
Peak memory 205720 kb
Host smart-7a483803-91ca-4239-a2a5-df078814442a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255233273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
255233273
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1748417070
Short name T182
Test name
Test status
Simulation time 180511423 ps
CPU time 2.49 seconds
Started Aug 01 05:15:44 PM PDT 24
Finished Aug 01 05:15:47 PM PDT 24
Peak memory 233292 kb
Host smart-ed1f796c-ff54-40c0-9b58-103ce4ea08ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748417070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1748417070
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3181890642
Short name T945
Test name
Test status
Simulation time 223070492 ps
CPU time 0.75 seconds
Started Aug 01 05:15:45 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 206216 kb
Host smart-1809615e-5e68-47e7-9455-722c73e7e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181890642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3181890642
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1605906543
Short name T265
Test name
Test status
Simulation time 66802937096 ps
CPU time 469.82 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:23:32 PM PDT 24
Peak memory 268732 kb
Host smart-ac56e384-01ee-4c10-a1bf-14b17a4be4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605906543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1605906543
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4239637888
Short name T447
Test name
Test status
Simulation time 32006314860 ps
CPU time 171.93 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:18:34 PM PDT 24
Peak memory 250036 kb
Host smart-888036bf-2df3-463b-b654-3a4ea9fca87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239637888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4239637888
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2430995960
Short name T640
Test name
Test status
Simulation time 168092872248 ps
CPU time 96.23 seconds
Started Aug 01 05:15:39 PM PDT 24
Finished Aug 01 05:17:15 PM PDT 24
Peak memory 250568 kb
Host smart-950e111c-d09c-494e-b029-d13bee0d3347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430995960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2430995960
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4103255276
Short name T753
Test name
Test status
Simulation time 26891237547 ps
CPU time 50.77 seconds
Started Aug 01 05:15:45 PM PDT 24
Finished Aug 01 05:16:36 PM PDT 24
Peak memory 254324 kb
Host smart-d37c9b5c-afb8-495a-89c5-39ff926f2c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103255276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4103255276
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2026309494
Short name T252
Test name
Test status
Simulation time 1455763012 ps
CPU time 11.99 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:54 PM PDT 24
Peak memory 233492 kb
Host smart-ad9ea716-2e1f-4df9-bd77-33f90a215b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026309494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2026309494
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3701244041
Short name T476
Test name
Test status
Simulation time 134587283 ps
CPU time 4.28 seconds
Started Aug 01 05:15:55 PM PDT 24
Finished Aug 01 05:16:00 PM PDT 24
Peak memory 233464 kb
Host smart-dcb28f81-3d0a-4f96-b419-51a1153a57dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701244041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3701244041
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4271506446
Short name T515
Test name
Test status
Simulation time 28853459 ps
CPU time 1.06 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 218408 kb
Host smart-ea4345dd-b37a-414f-a2e1-1cdd64827962
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271506446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4271506446
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3456058084
Short name T801
Test name
Test status
Simulation time 30710007 ps
CPU time 2.55 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:45 PM PDT 24
Peak memory 232996 kb
Host smart-31018b1a-7bfd-4234-bccd-7e908f597809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456058084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3456058084
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3311920841
Short name T969
Test name
Test status
Simulation time 8073041804 ps
CPU time 22.45 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:16:02 PM PDT 24
Peak memory 233320 kb
Host smart-1753d373-3016-4d16-b20b-8cdbe7f68c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311920841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3311920841
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.623748397
Short name T921
Test name
Test status
Simulation time 7903884877 ps
CPU time 24.29 seconds
Started Aug 01 05:15:39 PM PDT 24
Finished Aug 01 05:16:03 PM PDT 24
Peak memory 221152 kb
Host smart-fccad8e6-30a6-4ca3-8161-0c4cf331d747
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=623748397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.623748397
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1079600254
Short name T69
Test name
Test status
Simulation time 1036368717 ps
CPU time 1.16 seconds
Started Aug 01 05:15:39 PM PDT 24
Finished Aug 01 05:15:40 PM PDT 24
Peak memory 235472 kb
Host smart-ca274540-5ee3-454e-a55c-fac01fa1f9c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079600254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1079600254
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.370291071
Short name T650
Test name
Test status
Simulation time 61666597376 ps
CPU time 407.93 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 274068 kb
Host smart-1215695f-f581-4c1f-b5c5-eabc258ac0ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370291071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.370291071
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.94356352
Short name T551
Test name
Test status
Simulation time 20929445838 ps
CPU time 21.56 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:16:02 PM PDT 24
Peak memory 216832 kb
Host smart-76e4e935-e8d2-4f25-b423-a77c50dd95f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94356352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.94356352
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2110147016
Short name T507
Test name
Test status
Simulation time 3081096326 ps
CPU time 5.85 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:49 PM PDT 24
Peak memory 216996 kb
Host smart-a07ff25e-ced5-4baa-bd40-4fd959ac013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110147016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2110147016
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3737669893
Short name T631
Test name
Test status
Simulation time 408152612 ps
CPU time 5.71 seconds
Started Aug 01 05:15:44 PM PDT 24
Finished Aug 01 05:15:50 PM PDT 24
Peak memory 216820 kb
Host smart-4742d155-57c6-4a88-b99e-16451b083fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737669893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3737669893
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1534961999
Short name T662
Test name
Test status
Simulation time 26930416 ps
CPU time 0.8 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:44 PM PDT 24
Peak memory 206516 kb
Host smart-a1c91237-9972-4f03-adf5-e8ba72b70181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534961999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1534961999
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1389930104
Short name T982
Test name
Test status
Simulation time 2349857470 ps
CPU time 4.92 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:47 PM PDT 24
Peak memory 225292 kb
Host smart-a2a7f8d5-5967-40db-bfd6-96cd96e8eae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389930104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1389930104
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1692124927
Short name T888
Test name
Test status
Simulation time 14416079 ps
CPU time 0.75 seconds
Started Aug 01 05:16:19 PM PDT 24
Finished Aug 01 05:16:20 PM PDT 24
Peak memory 205740 kb
Host smart-857d2eed-66f9-4c20-a8cd-c3d965a1f9dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692124927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1692124927
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2671147455
Short name T820
Test name
Test status
Simulation time 324852782 ps
CPU time 5.25 seconds
Started Aug 01 05:16:19 PM PDT 24
Finished Aug 01 05:16:25 PM PDT 24
Peak memory 225220 kb
Host smart-910329a5-ce7f-4af0-b3e6-cf83ec70ad2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671147455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2671147455
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.275867664
Short name T900
Test name
Test status
Simulation time 200122831 ps
CPU time 0.76 seconds
Started Aug 01 05:16:10 PM PDT 24
Finished Aug 01 05:16:11 PM PDT 24
Peak memory 206964 kb
Host smart-d8c7dae6-c5d3-4005-b031-5f6c3ca8a92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275867664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.275867664
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3418786771
Short name T297
Test name
Test status
Simulation time 12884426761 ps
CPU time 82.19 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:17:41 PM PDT 24
Peak memory 256608 kb
Host smart-e0637445-ef83-42b0-9278-7dbc30321fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418786771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3418786771
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1251853360
Short name T140
Test name
Test status
Simulation time 2526284801 ps
CPU time 31.42 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 225312 kb
Host smart-2707ee2c-200b-403c-bc25-f80d4bfe7543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251853360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1251853360
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3028755548
Short name T224
Test name
Test status
Simulation time 30898484503 ps
CPU time 71.98 seconds
Started Aug 01 05:16:17 PM PDT 24
Finished Aug 01 05:17:29 PM PDT 24
Peak memory 249896 kb
Host smart-24c1ccc3-ddbc-42a3-934c-68fca6296097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028755548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3028755548
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2840882044
Short name T789
Test name
Test status
Simulation time 774023085 ps
CPU time 14.72 seconds
Started Aug 01 05:16:12 PM PDT 24
Finished Aug 01 05:16:27 PM PDT 24
Peak memory 241692 kb
Host smart-ac832f39-4cf8-417c-ad7b-a4fe905d9230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840882044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2840882044
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1304202886
Short name T854
Test name
Test status
Simulation time 16466794338 ps
CPU time 113.82 seconds
Started Aug 01 05:16:19 PM PDT 24
Finished Aug 01 05:18:14 PM PDT 24
Peak memory 233408 kb
Host smart-d28f6655-4892-412d-9f73-536569c2742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304202886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1304202886
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1299834616
Short name T747
Test name
Test status
Simulation time 745113778 ps
CPU time 4.95 seconds
Started Aug 01 05:16:13 PM PDT 24
Finished Aug 01 05:16:18 PM PDT 24
Peak memory 225292 kb
Host smart-7dd95550-ae30-4eda-b374-c8b39e7be2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299834616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1299834616
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.855471978
Short name T749
Test name
Test status
Simulation time 4983050502 ps
CPU time 21.59 seconds
Started Aug 01 05:16:19 PM PDT 24
Finished Aug 01 05:16:42 PM PDT 24
Peak memory 225256 kb
Host smart-60dd1884-f479-4cdf-b51d-ae5ccd5f81e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855471978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.855471978
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3200176400
Short name T750
Test name
Test status
Simulation time 3361812980 ps
CPU time 10.59 seconds
Started Aug 01 05:16:14 PM PDT 24
Finished Aug 01 05:16:25 PM PDT 24
Peak memory 233428 kb
Host smart-d75775be-249c-46a7-ab70-6af71369ba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200176400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3200176400
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2477893124
Short name T636
Test name
Test status
Simulation time 126053189 ps
CPU time 3.34 seconds
Started Aug 01 05:16:14 PM PDT 24
Finished Aug 01 05:16:17 PM PDT 24
Peak memory 233516 kb
Host smart-d495ed4b-95bc-49c8-a50f-762d09e04865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477893124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2477893124
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4186963351
Short name T386
Test name
Test status
Simulation time 241492819 ps
CPU time 5.75 seconds
Started Aug 01 05:16:14 PM PDT 24
Finished Aug 01 05:16:20 PM PDT 24
Peak memory 222808 kb
Host smart-4201f031-3e39-41ba-837f-6ffddcbacafd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4186963351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4186963351
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2590519965
Short name T439
Test name
Test status
Simulation time 25646405488 ps
CPU time 208.67 seconds
Started Aug 01 05:16:17 PM PDT 24
Finished Aug 01 05:19:45 PM PDT 24
Peak memory 250076 kb
Host smart-520038c5-4c81-4a69-ba62-8bf3f72c4fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590519965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2590519965
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4161792886
Short name T917
Test name
Test status
Simulation time 7651450114 ps
CPU time 19.44 seconds
Started Aug 01 05:16:11 PM PDT 24
Finished Aug 01 05:16:30 PM PDT 24
Peak memory 217016 kb
Host smart-331f79ec-76d2-46b3-ba83-c8bd0aa07976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161792886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4161792886
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.607776115
Short name T822
Test name
Test status
Simulation time 5640787967 ps
CPU time 4.06 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:19 PM PDT 24
Peak memory 216972 kb
Host smart-6fe6faa6-4a72-4609-ba2f-f0d8d6b7dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607776115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.607776115
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.853909749
Short name T564
Test name
Test status
Simulation time 40786639 ps
CPU time 1.24 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:16 PM PDT 24
Peak memory 216892 kb
Host smart-fb0b2897-ba23-4b7a-8229-f1d27a45f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853909749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.853909749
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2684761011
Short name T666
Test name
Test status
Simulation time 93761597 ps
CPU time 0.78 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:16:19 PM PDT 24
Peak memory 206504 kb
Host smart-0a2d34e9-d6e8-47bd-8585-e90fe8a4250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684761011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2684761011
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2322134088
Short name T748
Test name
Test status
Simulation time 43879027 ps
CPU time 0.69 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:16 PM PDT 24
Peak memory 205704 kb
Host smart-d8e613b9-c969-4b9b-b8e9-819c49436125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322134088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2322134088
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2638511377
Short name T867
Test name
Test status
Simulation time 174922921 ps
CPU time 3.09 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:18 PM PDT 24
Peak memory 225364 kb
Host smart-3a5f0731-4215-4259-bd36-e0aefdad1955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638511377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2638511377
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3843942535
Short name T732
Test name
Test status
Simulation time 26527827 ps
CPU time 0.78 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:16:17 PM PDT 24
Peak memory 206992 kb
Host smart-f54b9333-6327-433e-a869-327657645e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843942535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3843942535
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3159828101
Short name T291
Test name
Test status
Simulation time 30814416300 ps
CPU time 168.7 seconds
Started Aug 01 05:16:13 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 252932 kb
Host smart-de3afdea-2516-4fbe-8121-14331ac2d977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159828101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3159828101
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2263434653
Short name T992
Test name
Test status
Simulation time 22037604648 ps
CPU time 91.18 seconds
Started Aug 01 05:16:14 PM PDT 24
Finished Aug 01 05:17:46 PM PDT 24
Peak memory 253012 kb
Host smart-02a255b2-1282-4de2-bf6a-9ffe7beba094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263434653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2263434653
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2848453029
Short name T665
Test name
Test status
Simulation time 292266546 ps
CPU time 4 seconds
Started Aug 01 05:16:17 PM PDT 24
Finished Aug 01 05:16:21 PM PDT 24
Peak memory 225268 kb
Host smart-a92def88-9be5-4a64-bd3d-2f98bb6d2c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848453029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2848453029
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1325194440
Short name T289
Test name
Test status
Simulation time 21842583483 ps
CPU time 152.3 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 258064 kb
Host smart-f9a19d52-4121-488e-bb71-b5b28344aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325194440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1325194440
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.605222418
Short name T93
Test name
Test status
Simulation time 274028420 ps
CPU time 6.24 seconds
Started Aug 01 05:16:19 PM PDT 24
Finished Aug 01 05:16:26 PM PDT 24
Peak memory 233416 kb
Host smart-5e91051c-6a25-40bb-844e-7b220a602f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605222418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.605222418
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2759781463
Short name T424
Test name
Test status
Simulation time 64549250059 ps
CPU time 134.49 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:18:30 PM PDT 24
Peak memory 241340 kb
Host smart-8321d6ca-133b-47f1-82c4-cbf7082e9163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759781463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2759781463
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.156330095
Short name T1003
Test name
Test status
Simulation time 16256230 ps
CPU time 1.05 seconds
Started Aug 01 05:16:17 PM PDT 24
Finished Aug 01 05:16:19 PM PDT 24
Peak memory 217116 kb
Host smart-8446626e-6847-4b7a-a316-428c3502be73
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156330095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.156330095
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2910138459
Short name T602
Test name
Test status
Simulation time 1359409438 ps
CPU time 4.54 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:16:23 PM PDT 24
Peak memory 225260 kb
Host smart-ae3153e5-4f77-49e8-9694-f90a1d52b9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910138459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2910138459
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.327332276
Short name T390
Test name
Test status
Simulation time 28477138 ps
CPU time 2.09 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:16:18 PM PDT 24
Peak memory 223844 kb
Host smart-ce71f892-9002-4eb2-8ade-2a8b7c156359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327332276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.327332276
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1792125071
Short name T882
Test name
Test status
Simulation time 479958975 ps
CPU time 3.98 seconds
Started Aug 01 05:16:17 PM PDT 24
Finished Aug 01 05:16:21 PM PDT 24
Peak memory 223380 kb
Host smart-6c3d52a4-9fa0-4f07-8587-926e954155cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1792125071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1792125071
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3651534183
Short name T717
Test name
Test status
Simulation time 292093411415 ps
CPU time 670.32 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:27:25 PM PDT 24
Peak memory 273212 kb
Host smart-71288dc7-eecf-43b1-a478-e1014411c5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651534183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3651534183
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.213901998
Short name T848
Test name
Test status
Simulation time 57595820852 ps
CPU time 29.42 seconds
Started Aug 01 05:16:22 PM PDT 24
Finished Aug 01 05:16:51 PM PDT 24
Peak memory 217000 kb
Host smart-bffd2dec-48da-4a84-a14d-290288c6d1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213901998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.213901998
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1165333721
Short name T342
Test name
Test status
Simulation time 3502504499 ps
CPU time 7.97 seconds
Started Aug 01 05:16:17 PM PDT 24
Finished Aug 01 05:16:25 PM PDT 24
Peak memory 216928 kb
Host smart-fe68f806-1bf3-4318-a67e-e344622e07ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165333721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1165333721
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3130704003
Short name T533
Test name
Test status
Simulation time 100741402 ps
CPU time 1.62 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:16:18 PM PDT 24
Peak memory 217128 kb
Host smart-f35cddc1-c662-47a6-9a0f-69e4436a15f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130704003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3130704003
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3526071701
Short name T395
Test name
Test status
Simulation time 346611120 ps
CPU time 0.87 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:16:19 PM PDT 24
Peak memory 206588 kb
Host smart-491c14c8-889c-4519-93d1-147c0e962574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526071701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3526071701
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4127200628
Short name T898
Test name
Test status
Simulation time 865712420 ps
CPU time 5.93 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:16:24 PM PDT 24
Peak memory 225360 kb
Host smart-9351099f-c56a-4a92-bd3d-9747d676ab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127200628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4127200628
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1061268377
Short name T939
Test name
Test status
Simulation time 13462913 ps
CPU time 0.68 seconds
Started Aug 01 05:16:23 PM PDT 24
Finished Aug 01 05:16:24 PM PDT 24
Peak memory 205764 kb
Host smart-ef716822-762f-42cc-be70-26312e8fb461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061268377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1061268377
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1715741514
Short name T472
Test name
Test status
Simulation time 2021067168 ps
CPU time 5.51 seconds
Started Aug 01 05:16:22 PM PDT 24
Finished Aug 01 05:16:27 PM PDT 24
Peak memory 233352 kb
Host smart-1794e473-c4d4-4c37-9971-be293715e300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715741514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1715741514
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.156087619
Short name T557
Test name
Test status
Simulation time 22252707 ps
CPU time 0.73 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:16 PM PDT 24
Peak memory 207248 kb
Host smart-02c38a56-ae47-43c0-9b47-c10a1d14bf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156087619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.156087619
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1497931173
Short name T996
Test name
Test status
Simulation time 67502551657 ps
CPU time 230.95 seconds
Started Aug 01 05:16:26 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 251176 kb
Host smart-7803e664-dfcf-4923-aced-cd58fb813c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497931173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1497931173
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.697844651
Short name T1002
Test name
Test status
Simulation time 26590116833 ps
CPU time 262.31 seconds
Started Aug 01 05:16:23 PM PDT 24
Finished Aug 01 05:20:46 PM PDT 24
Peak memory 265588 kb
Host smart-2653dda6-db86-4886-a8ca-804938f85eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697844651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.697844651
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1055798011
Short name T466
Test name
Test status
Simulation time 114977804374 ps
CPU time 230.85 seconds
Started Aug 01 05:16:23 PM PDT 24
Finished Aug 01 05:20:14 PM PDT 24
Peak memory 252472 kb
Host smart-786e492f-b434-4d6f-b1ac-7689ab1b91ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055798011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1055798011
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2035263159
Short name T310
Test name
Test status
Simulation time 816077538 ps
CPU time 10.42 seconds
Started Aug 01 05:16:22 PM PDT 24
Finished Aug 01 05:16:32 PM PDT 24
Peak memory 225264 kb
Host smart-83701d0c-6d50-498c-9a36-651e59f6a754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035263159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2035263159
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.698003011
Short name T425
Test name
Test status
Simulation time 8915651755 ps
CPU time 22.96 seconds
Started Aug 01 05:16:21 PM PDT 24
Finished Aug 01 05:16:44 PM PDT 24
Peak memory 238984 kb
Host smart-59af69c0-a96e-42a9-8459-c9ca6e1d52a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698003011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.698003011
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.758716684
Short name T274
Test name
Test status
Simulation time 1051561709 ps
CPU time 19.29 seconds
Started Aug 01 05:16:21 PM PDT 24
Finished Aug 01 05:16:40 PM PDT 24
Peak memory 241568 kb
Host smart-5e22a5a0-d393-45b6-9bf1-dc813f0ae4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758716684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.758716684
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1755601175
Short name T896
Test name
Test status
Simulation time 57338528 ps
CPU time 1.03 seconds
Started Aug 01 05:16:13 PM PDT 24
Finished Aug 01 05:16:14 PM PDT 24
Peak memory 217104 kb
Host smart-b9e87468-3566-46af-ba53-0fa8bd5e492b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755601175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1755601175
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3747893835
Short name T277
Test name
Test status
Simulation time 1956826165 ps
CPU time 4.96 seconds
Started Aug 01 05:16:20 PM PDT 24
Finished Aug 01 05:16:25 PM PDT 24
Peak memory 225128 kb
Host smart-645df7c8-c0f2-4353-8b31-d7dc31bf6b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747893835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3747893835
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2452054153
Short name T360
Test name
Test status
Simulation time 31400031 ps
CPU time 2.39 seconds
Started Aug 01 05:16:21 PM PDT 24
Finished Aug 01 05:16:24 PM PDT 24
Peak memory 233036 kb
Host smart-e007ae41-ad9b-4c9c-ac77-c7daae7b7a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452054153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2452054153
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3566137692
Short name T880
Test name
Test status
Simulation time 1025980683 ps
CPU time 8.62 seconds
Started Aug 01 05:16:21 PM PDT 24
Finished Aug 01 05:16:30 PM PDT 24
Peak memory 219612 kb
Host smart-4817e5f9-b45b-44b5-9b10-d55893a7969f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3566137692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3566137692
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3870641008
Short name T18
Test name
Test status
Simulation time 17737813738 ps
CPU time 138.92 seconds
Started Aug 01 05:16:24 PM PDT 24
Finished Aug 01 05:18:44 PM PDT 24
Peak memory 223012 kb
Host smart-496782c7-f0c4-49ca-840f-3a3c01426235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870641008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3870641008
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4090482259
Short name T1025
Test name
Test status
Simulation time 3695319215 ps
CPU time 18.91 seconds
Started Aug 01 05:16:13 PM PDT 24
Finished Aug 01 05:16:32 PM PDT 24
Peak memory 216928 kb
Host smart-67af5e8d-8ca7-4d88-a96a-cf5f41730fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090482259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4090482259
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3356176664
Short name T486
Test name
Test status
Simulation time 329760470 ps
CPU time 4.67 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:20 PM PDT 24
Peak memory 216868 kb
Host smart-18a91231-3031-4b89-a57c-174dd2707129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356176664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3356176664
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3813437258
Short name T995
Test name
Test status
Simulation time 260154596 ps
CPU time 0.92 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:17 PM PDT 24
Peak memory 207484 kb
Host smart-1c4f832b-1bb0-45d5-8b3d-866218b5c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813437258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3813437258
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1429970062
Short name T399
Test name
Test status
Simulation time 38701052 ps
CPU time 2.25 seconds
Started Aug 01 05:16:24 PM PDT 24
Finished Aug 01 05:16:27 PM PDT 24
Peak memory 224752 kb
Host smart-8680ff11-7134-42e9-9c03-0e1763442e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429970062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1429970062
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.906653438
Short name T76
Test name
Test status
Simulation time 60348720 ps
CPU time 0.69 seconds
Started Aug 01 05:16:46 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 205104 kb
Host smart-407ce606-cca3-417b-bdfd-e0b4a7b2565a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906653438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.906653438
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.101162299
Short name T89
Test name
Test status
Simulation time 227025703 ps
CPU time 4.25 seconds
Started Aug 01 05:16:41 PM PDT 24
Finished Aug 01 05:16:45 PM PDT 24
Peak memory 225120 kb
Host smart-1172a69e-b58f-460d-87cb-fecfc4761c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101162299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.101162299
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.390392256
Short name T482
Test name
Test status
Simulation time 13174889 ps
CPU time 0.73 seconds
Started Aug 01 05:16:21 PM PDT 24
Finished Aug 01 05:16:22 PM PDT 24
Peak memory 207072 kb
Host smart-765e0251-4f98-4a59-855f-6bff084fd3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390392256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.390392256
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3779774491
Short name T248
Test name
Test status
Simulation time 1146201988 ps
CPU time 15.06 seconds
Started Aug 01 05:16:42 PM PDT 24
Finished Aug 01 05:16:58 PM PDT 24
Peak memory 234444 kb
Host smart-42247591-c540-4151-bad5-2ba7dfcfb48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779774491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3779774491
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1031154053
Short name T164
Test name
Test status
Simulation time 36040192972 ps
CPU time 142.49 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:19:06 PM PDT 24
Peak memory 250804 kb
Host smart-187e5572-6f09-4b21-bb1d-94c8f9fa7227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031154053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1031154053
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3575188619
Short name T239
Test name
Test status
Simulation time 28724840120 ps
CPU time 264.08 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:21:07 PM PDT 24
Peak memory 252900 kb
Host smart-55307b96-149c-4214-b3a8-acefdff7007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575188619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3575188619
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.501378588
Short name T931
Test name
Test status
Simulation time 363392300 ps
CPU time 2.43 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 225196 kb
Host smart-a7e49bf7-ec96-4c06-946b-c769ba0b9161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501378588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.501378588
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1022458071
Short name T876
Test name
Test status
Simulation time 102692181723 ps
CPU time 195.23 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:19:59 PM PDT 24
Peak memory 253500 kb
Host smart-2c55e117-3e9f-4d4d-b935-a4af3fc18dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022458071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1022458071
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.209163636
Short name T976
Test name
Test status
Simulation time 145433370 ps
CPU time 3.74 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:48 PM PDT 24
Peak memory 225108 kb
Host smart-3afe96c1-d0ba-41de-8a96-7cc566eb24db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209163636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.209163636
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3722432426
Short name T967
Test name
Test status
Simulation time 217332521 ps
CPU time 5.9 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:49 PM PDT 24
Peak memory 233312 kb
Host smart-ad534454-b379-4726-8a4e-cd6cdb3c41dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722432426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3722432426
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3597469565
Short name T658
Test name
Test status
Simulation time 29327182 ps
CPU time 0.98 seconds
Started Aug 01 05:16:24 PM PDT 24
Finished Aug 01 05:16:26 PM PDT 24
Peak memory 218064 kb
Host smart-46f2d061-b550-4b22-a7cb-968b15200b6d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597469565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3597469565
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3336823999
Short name T765
Test name
Test status
Simulation time 797470168 ps
CPU time 5.84 seconds
Started Aug 01 05:16:40 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 233444 kb
Host smart-b9821d77-9e79-46ed-8f59-ffc2e5e39245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336823999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3336823999
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.894621783
Short name T438
Test name
Test status
Simulation time 33057480 ps
CPU time 2.29 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 232980 kb
Host smart-32be6f0b-cf3f-4d60-9835-69f28395549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894621783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.894621783
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3299222419
Short name T10
Test name
Test status
Simulation time 1173423065 ps
CPU time 6.22 seconds
Started Aug 01 05:16:41 PM PDT 24
Finished Aug 01 05:16:48 PM PDT 24
Peak memory 222808 kb
Host smart-5f9371f5-2180-4fc4-ae79-579a10bafd31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299222419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3299222419
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3508995862
Short name T534
Test name
Test status
Simulation time 529474464 ps
CPU time 4.01 seconds
Started Aug 01 05:16:42 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 216876 kb
Host smart-9c02b431-ecfc-427a-b875-72469ad56edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508995862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3508995862
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1409467358
Short name T795
Test name
Test status
Simulation time 3325862082 ps
CPU time 8.13 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 217024 kb
Host smart-ab97c7b8-4a98-458b-badb-06320673a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409467358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1409467358
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4032904729
Short name T766
Test name
Test status
Simulation time 1300975041 ps
CPU time 13.16 seconds
Started Aug 01 05:16:45 PM PDT 24
Finished Aug 01 05:16:58 PM PDT 24
Peak memory 216960 kb
Host smart-35117101-9433-4512-8925-9d9d1d9e35d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032904729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4032904729
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.430195171
Short name T506
Test name
Test status
Simulation time 102275919 ps
CPU time 0.85 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:45 PM PDT 24
Peak memory 206640 kb
Host smart-ee456cdf-4c4b-4292-b00a-8c7fc36455c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430195171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.430195171
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.941606099
Short name T844
Test name
Test status
Simulation time 9040153833 ps
CPU time 26.61 seconds
Started Aug 01 05:16:42 PM PDT 24
Finished Aug 01 05:17:08 PM PDT 24
Peak memory 233488 kb
Host smart-d721c69f-919a-46a4-b822-056d596c51e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941606099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.941606099
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.161004440
Short name T825
Test name
Test status
Simulation time 32614726 ps
CPU time 0.72 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:45 PM PDT 24
Peak memory 205760 kb
Host smart-b6a4ff97-76f1-4d31-be01-92acaa1e734a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161004440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.161004440
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4028134598
Short name T562
Test name
Test status
Simulation time 187292294 ps
CPU time 2.88 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:47 PM PDT 24
Peak memory 233348 kb
Host smart-2b75a030-3b4e-4fe3-a41b-ed9b4bcaee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028134598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4028134598
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.459143963
Short name T538
Test name
Test status
Simulation time 27216157 ps
CPU time 0.8 seconds
Started Aug 01 05:16:45 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 205968 kb
Host smart-bf0447b3-448d-4d57-99b7-c16ca53cd8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459143963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.459143963
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4063180568
Short name T668
Test name
Test status
Simulation time 8759009350 ps
CPU time 70.13 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:17:53 PM PDT 24
Peak memory 249940 kb
Host smart-fcb7ac93-3a60-4bb6-9e90-4bf6a9d93a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063180568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4063180568
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1566316518
Short name T652
Test name
Test status
Simulation time 50276002665 ps
CPU time 109.52 seconds
Started Aug 01 05:16:41 PM PDT 24
Finished Aug 01 05:18:31 PM PDT 24
Peak memory 255964 kb
Host smart-1da15c0a-bf12-4042-808c-9e8c6afc9695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566316518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1566316518
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1228383667
Short name T601
Test name
Test status
Simulation time 1078696828 ps
CPU time 7.77 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 240488 kb
Host smart-db22a8ba-5323-4a93-b69a-f40b9d7584fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228383667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1228383667
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3992000465
Short name T205
Test name
Test status
Simulation time 203988870873 ps
CPU time 198.36 seconds
Started Aug 01 05:16:39 PM PDT 24
Finished Aug 01 05:19:58 PM PDT 24
Peak memory 251796 kb
Host smart-e731d541-d611-4055-8e57-cff93819d8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992000465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3992000465
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1305971586
Short name T952
Test name
Test status
Simulation time 386789807 ps
CPU time 5.45 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:49 PM PDT 24
Peak memory 225080 kb
Host smart-e9039555-e653-4810-9ea0-b8949c87ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305971586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1305971586
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.285871099
Short name T918
Test name
Test status
Simulation time 694882945 ps
CPU time 8.59 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 225220 kb
Host smart-2523b06a-e1bc-417f-855e-e84a8f73ecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285871099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.285871099
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3872022562
Short name T1004
Test name
Test status
Simulation time 26557453 ps
CPU time 1.08 seconds
Started Aug 01 05:16:45 PM PDT 24
Finished Aug 01 05:16:46 PM PDT 24
Peak memory 218360 kb
Host smart-f409d38e-a6c9-4e6c-9083-b0f408501da1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872022562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3872022562
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2025213092
Short name T98
Test name
Test status
Simulation time 8341558642 ps
CPU time 14.24 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:59 PM PDT 24
Peak memory 225208 kb
Host smart-64b1687c-3561-4538-85a4-21f53065e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025213092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2025213092
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2196752101
Short name T663
Test name
Test status
Simulation time 12454406252 ps
CPU time 11.1 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:54 PM PDT 24
Peak memory 225196 kb
Host smart-96ba0fb0-84b2-4757-9542-818b75e67bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196752101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2196752101
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2829234857
Short name T516
Test name
Test status
Simulation time 810890032 ps
CPU time 8.85 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:53 PM PDT 24
Peak memory 221288 kb
Host smart-1b0b5b80-baf0-4c7e-831a-8ea014d4a1ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2829234857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2829234857
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2362993452
Short name T327
Test name
Test status
Simulation time 3124165483 ps
CPU time 35.9 seconds
Started Aug 01 05:16:40 PM PDT 24
Finished Aug 01 05:17:16 PM PDT 24
Peak memory 225300 kb
Host smart-4751cfca-6518-485a-b0b5-52009517b428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362993452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2362993452
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3804404590
Short name T702
Test name
Test status
Simulation time 279513384 ps
CPU time 1.02 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:45 PM PDT 24
Peak memory 208320 kb
Host smart-229532f7-347b-4940-b720-e2733478f58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804404590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3804404590
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3304796557
Short name T489
Test name
Test status
Simulation time 65192826 ps
CPU time 1.51 seconds
Started Aug 01 05:16:42 PM PDT 24
Finished Aug 01 05:16:44 PM PDT 24
Peak memory 216880 kb
Host smart-2cb37ea3-e6da-45de-85dd-d64841d58d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304796557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3304796557
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2095432000
Short name T359
Test name
Test status
Simulation time 55138604 ps
CPU time 0.85 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:45 PM PDT 24
Peak memory 206576 kb
Host smart-00c97a5c-9894-44cb-85fd-25a5fef1deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095432000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2095432000
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3573320591
Short name T217
Test name
Test status
Simulation time 7383034393 ps
CPU time 10.91 seconds
Started Aug 01 05:16:46 PM PDT 24
Finished Aug 01 05:16:57 PM PDT 24
Peak memory 249884 kb
Host smart-a26db573-67a9-408f-906f-4b51e0487d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573320591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3573320591
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2726710894
Short name T561
Test name
Test status
Simulation time 60736382 ps
CPU time 0.72 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:16:48 PM PDT 24
Peak memory 205812 kb
Host smart-e8e051e6-02b3-40e2-9370-121fd6905396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726710894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2726710894
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.459275942
Short name T614
Test name
Test status
Simulation time 1842356954 ps
CPU time 8.2 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 233316 kb
Host smart-1b71a65b-4fc5-4564-a527-b94d580b7e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459275942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.459275942
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2758996288
Short name T441
Test name
Test status
Simulation time 14044470 ps
CPU time 0.79 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:45 PM PDT 24
Peak memory 206928 kb
Host smart-ecc3827e-5c33-4467-a645-bf98bb38d420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758996288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2758996288
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4223856560
Short name T904
Test name
Test status
Simulation time 2136888683 ps
CPU time 28.44 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:17:11 PM PDT 24
Peak memory 249812 kb
Host smart-78f89282-1e36-48c4-bdd4-d93668d00a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223856560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4223856560
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3088626806
Short name T815
Test name
Test status
Simulation time 92204099734 ps
CPU time 167.36 seconds
Started Aug 01 05:16:41 PM PDT 24
Finished Aug 01 05:19:29 PM PDT 24
Peak memory 249936 kb
Host smart-2cc85cb8-7337-4135-9c36-a754b28a1823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088626806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3088626806
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2066373089
Short name T577
Test name
Test status
Simulation time 6012939837 ps
CPU time 39.57 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:17:29 PM PDT 24
Peak memory 249852 kb
Host smart-8e756915-1f33-40fa-8509-eb1b59e2d8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066373089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2066373089
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.273813174
Short name T400
Test name
Test status
Simulation time 298903505 ps
CPU time 4.89 seconds
Started Aug 01 05:16:42 PM PDT 24
Finished Aug 01 05:16:47 PM PDT 24
Peak memory 233536 kb
Host smart-7718978a-396e-4f25-a6ea-292dc96eedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273813174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.273813174
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1881276625
Short name T620
Test name
Test status
Simulation time 56235791 ps
CPU time 2.32 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:16:45 PM PDT 24
Peak memory 232980 kb
Host smart-60c17deb-1592-479d-9a3d-11112e1c848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881276625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1881276625
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1258057411
Short name T459
Test name
Test status
Simulation time 232904793 ps
CPU time 1.05 seconds
Started Aug 01 05:16:41 PM PDT 24
Finished Aug 01 05:16:42 PM PDT 24
Peak memory 217068 kb
Host smart-88ce0298-2a69-4c97-a208-9a266044e11a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258057411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1258057411
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3665362794
Short name T903
Test name
Test status
Simulation time 792948833 ps
CPU time 5.23 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:50 PM PDT 24
Peak memory 233468 kb
Host smart-c6e3a8ab-e1eb-47b1-be20-d8ba79dd2eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665362794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3665362794
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1044986116
Short name T396
Test name
Test status
Simulation time 249703301 ps
CPU time 5.2 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:16:50 PM PDT 24
Peak memory 222536 kb
Host smart-5400e671-6ec0-4cbb-84c6-269ffa7946a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1044986116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1044986116
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1522156487
Short name T983
Test name
Test status
Simulation time 73185966028 ps
CPU time 671.91 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:28:03 PM PDT 24
Peak memory 272496 kb
Host smart-d25dec0c-fffc-44fd-a91b-f39539158f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522156487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1522156487
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.34837301
Short name T565
Test name
Test status
Simulation time 4545825990 ps
CPU time 21.45 seconds
Started Aug 01 05:16:43 PM PDT 24
Finished Aug 01 05:17:05 PM PDT 24
Peak memory 216988 kb
Host smart-d01ef155-b33e-419a-b312-98e8e829a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34837301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.34837301
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3774237717
Short name T642
Test name
Test status
Simulation time 33603052873 ps
CPU time 10.99 seconds
Started Aug 01 05:16:45 PM PDT 24
Finished Aug 01 05:16:56 PM PDT 24
Peak memory 216916 kb
Host smart-4e5fad55-ad0b-4213-a15b-6089b28aca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774237717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3774237717
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1004315798
Short name T773
Test name
Test status
Simulation time 19946801 ps
CPU time 0.78 seconds
Started Aug 01 05:16:41 PM PDT 24
Finished Aug 01 05:16:42 PM PDT 24
Peak memory 207100 kb
Host smart-16d1cc40-8b25-4007-bbc9-700daa204f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004315798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1004315798
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3662104582
Short name T329
Test name
Test status
Simulation time 27422592 ps
CPU time 0.8 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:16:48 PM PDT 24
Peak memory 206584 kb
Host smart-1dc019d3-1a0d-4f8d-be3d-e8a23afd45d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662104582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3662104582
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.57206761
Short name T273
Test name
Test status
Simulation time 11747682291 ps
CPU time 15.77 seconds
Started Aug 01 05:16:44 PM PDT 24
Finished Aug 01 05:17:00 PM PDT 24
Peak memory 237816 kb
Host smart-ebca8aa2-4b05-4b51-80f9-0699743d93ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57206761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.57206761
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.128081815
Short name T647
Test name
Test status
Simulation time 37280219 ps
CPU time 0.72 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:16:51 PM PDT 24
Peak memory 205236 kb
Host smart-cdbd052b-5d37-4644-b5b2-ec289c99197e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128081815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.128081815
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1169303958
Short name T347
Test name
Test status
Simulation time 109790976 ps
CPU time 2.02 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:16:49 PM PDT 24
Peak memory 223636 kb
Host smart-28a8be82-96d2-4d6d-92fb-cee01767c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169303958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1169303958
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3755541777
Short name T823
Test name
Test status
Simulation time 20647931 ps
CPU time 0.73 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 206940 kb
Host smart-ace9e98b-282c-48f7-bba8-2cbea374adf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755541777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3755541777
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.655279161
Short name T278
Test name
Test status
Simulation time 178394270860 ps
CPU time 357.19 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:22:46 PM PDT 24
Peak memory 266192 kb
Host smart-1e42679c-4092-4921-ab1b-b0d1a8cd5568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655279161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.655279161
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3587777530
Short name T679
Test name
Test status
Simulation time 4860657417 ps
CPU time 75.94 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:18:03 PM PDT 24
Peak memory 249904 kb
Host smart-b16c72b5-2d08-40f9-bf76-09527116a1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587777530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3587777530
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3823041424
Short name T949
Test name
Test status
Simulation time 10450378187 ps
CPU time 56.99 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:17:49 PM PDT 24
Peak memory 240060 kb
Host smart-e1d37805-9642-442b-8053-2d8de4d5fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823041424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3823041424
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.385911950
Short name T868
Test name
Test status
Simulation time 698344687 ps
CPU time 13.67 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:17:03 PM PDT 24
Peak memory 233428 kb
Host smart-44c202e8-9eb4-4c6f-b43d-763e5c48c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385911950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.385911950
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3986645729
Short name T178
Test name
Test status
Simulation time 14675030814 ps
CPU time 60.96 seconds
Started Aug 01 05:17:12 PM PDT 24
Finished Aug 01 05:18:13 PM PDT 24
Peak memory 255268 kb
Host smart-6491254e-ba78-4370-807b-cbc5aa8d66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986645729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3986645729
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4064842211
Short name T200
Test name
Test status
Simulation time 869513508 ps
CPU time 4.16 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:55 PM PDT 24
Peak memory 224512 kb
Host smart-52aa5189-34cc-4125-b078-c2b3190e4378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064842211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4064842211
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1833133470
Short name T940
Test name
Test status
Simulation time 1056638643 ps
CPU time 10.18 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:17:02 PM PDT 24
Peak memory 233396 kb
Host smart-30390225-9a1c-4f5f-9a4b-d362cb50a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833133470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1833133470
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.43273883
Short name T843
Test name
Test status
Simulation time 120822489 ps
CPU time 1.05 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:16:49 PM PDT 24
Peak memory 217088 kb
Host smart-de3805ec-bc44-4868-9813-dffe6bae14e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43273883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.43273883
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2927457830
Short name T452
Test name
Test status
Simulation time 1704873065 ps
CPU time 12.19 seconds
Started Aug 01 05:16:48 PM PDT 24
Finished Aug 01 05:17:01 PM PDT 24
Peak memory 233468 kb
Host smart-c71376bf-74d3-4845-9c01-f4dc9e004c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927457830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2927457830
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3379817485
Short name T243
Test name
Test status
Simulation time 4521207318 ps
CPU time 14.94 seconds
Started Aug 01 05:16:48 PM PDT 24
Finished Aug 01 05:17:03 PM PDT 24
Peak memory 233496 kb
Host smart-6a2515da-09cb-4d68-9f55-b095a808b4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379817485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3379817485
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2593003199
Short name T379
Test name
Test status
Simulation time 247088473 ps
CPU time 5.36 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:16:55 PM PDT 24
Peak memory 222544 kb
Host smart-99ba51ec-2b16-40e4-8783-fd889b714543
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2593003199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2593003199
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1941917306
Short name T324
Test name
Test status
Simulation time 3905109935 ps
CPU time 18.39 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:17:08 PM PDT 24
Peak memory 217028 kb
Host smart-49a71e2c-f82e-40b2-becc-082d53bfa371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941917306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1941917306
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4129960631
Short name T563
Test name
Test status
Simulation time 491556838 ps
CPU time 4.24 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:16:53 PM PDT 24
Peak memory 216832 kb
Host smart-70dd28af-405a-4d65-b0d6-da3621f1895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129960631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4129960631
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.151519839
Short name T420
Test name
Test status
Simulation time 83927130 ps
CPU time 1.56 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:53 PM PDT 24
Peak memory 216896 kb
Host smart-19be3233-fd2f-4405-92ea-a196546ba38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151519839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.151519839
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4040828673
Short name T371
Test name
Test status
Simulation time 22245376 ps
CPU time 0.69 seconds
Started Aug 01 05:17:05 PM PDT 24
Finished Aug 01 05:17:06 PM PDT 24
Peak memory 206020 kb
Host smart-334a021e-f6fa-4faf-9553-cb4eee98cef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040828673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4040828673
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.422894721
Short name T479
Test name
Test status
Simulation time 2511790343 ps
CPU time 6.96 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:58 PM PDT 24
Peak memory 237584 kb
Host smart-5257f3f5-c7b2-47d6-82d4-8d9836e91a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422894721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.422894721
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2442237572
Short name T937
Test name
Test status
Simulation time 25853643 ps
CPU time 0.71 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 205740 kb
Host smart-8f7f8679-5d7d-463f-a0a6-7781c6106309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442237572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2442237572
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1192054264
Short name T627
Test name
Test status
Simulation time 2379809575 ps
CPU time 10.63 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:17:01 PM PDT 24
Peak memory 225200 kb
Host smart-b54b1605-ab2c-453a-9432-8935ee9311bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192054264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1192054264
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.541729543
Short name T803
Test name
Test status
Simulation time 16426542 ps
CPU time 0.77 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:16:49 PM PDT 24
Peak memory 206992 kb
Host smart-f0b84bb2-6844-4302-809f-3bdaf375f181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541729543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.541729543
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1985775567
Short name T791
Test name
Test status
Simulation time 8328965108 ps
CPU time 76.01 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:18:08 PM PDT 24
Peak memory 251440 kb
Host smart-d922ee2d-edda-49af-88d6-1f3b65042dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985775567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1985775567
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1005363962
Short name T613
Test name
Test status
Simulation time 10251089429 ps
CPU time 9 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:17:00 PM PDT 24
Peak memory 218440 kb
Host smart-7760fc61-7b8a-40a5-89be-75c45ce52b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005363962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1005363962
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.792938543
Short name T935
Test name
Test status
Simulation time 836151737 ps
CPU time 9.05 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:16:56 PM PDT 24
Peak memory 233460 kb
Host smart-b5a17966-15e3-4ef8-bdbd-2ffa464bdcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792938543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.792938543
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3971033627
Short name T875
Test name
Test status
Simulation time 110909285374 ps
CPU time 109.98 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:18:39 PM PDT 24
Peak memory 252300 kb
Host smart-ebd5671c-0687-4c21-823c-40736df64967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971033627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3971033627
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1356409967
Short name T991
Test name
Test status
Simulation time 5098242838 ps
CPU time 9.28 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:17:01 PM PDT 24
Peak memory 225184 kb
Host smart-bf78f911-6704-43f6-85a0-57feeeec34f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356409967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1356409967
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2094929525
Short name T362
Test name
Test status
Simulation time 1534114145 ps
CPU time 6.34 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:58 PM PDT 24
Peak memory 237964 kb
Host smart-f4442696-97c5-4a73-bb96-2fe21fd4186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094929525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2094929525
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1844541082
Short name T513
Test name
Test status
Simulation time 27316922 ps
CPU time 1.15 seconds
Started Aug 01 05:16:53 PM PDT 24
Finished Aug 01 05:16:54 PM PDT 24
Peak memory 217060 kb
Host smart-6e4503c7-3244-48a4-ae14-eada5e886a07
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844541082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1844541082
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2510457388
Short name T998
Test name
Test status
Simulation time 63115134796 ps
CPU time 17.22 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:17:07 PM PDT 24
Peak memory 233308 kb
Host smart-aa0f0c39-6cdb-43e5-81f6-14a84692dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510457388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2510457388
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3430191540
Short name T695
Test name
Test status
Simulation time 3889080378 ps
CPU time 2.68 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:53 PM PDT 24
Peak memory 225220 kb
Host smart-4fa41645-1c6c-426e-91e3-abe8ae7370b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430191540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3430191540
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1426271645
Short name T708
Test name
Test status
Simulation time 72954724 ps
CPU time 3.76 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:16:54 PM PDT 24
Peak memory 223032 kb
Host smart-5f862be6-d738-4b55-b80d-e4bc6ae5f26f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1426271645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1426271645
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1064946160
Short name T11
Test name
Test status
Simulation time 7843728401 ps
CPU time 22.59 seconds
Started Aug 01 05:16:53 PM PDT 24
Finished Aug 01 05:17:16 PM PDT 24
Peak memory 217200 kb
Host smart-d3099ee8-e921-4da4-9f53-f1587211001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064946160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1064946160
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.396662149
Short name T726
Test name
Test status
Simulation time 21799688383 ps
CPU time 14.57 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:17:06 PM PDT 24
Peak memory 217096 kb
Host smart-b02baf2a-9367-452d-986f-98a07fa095cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396662149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.396662149
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3423549554
Short name T936
Test name
Test status
Simulation time 28317731 ps
CPU time 1.06 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 208460 kb
Host smart-0cd76d29-d39c-4d90-b1d6-02482a558804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423549554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3423549554
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3401371722
Short name T768
Test name
Test status
Simulation time 29127549 ps
CPU time 0.93 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:16:48 PM PDT 24
Peak memory 206524 kb
Host smart-fa42456a-b6c0-4fcc-b3bf-231c6acf572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401371722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3401371722
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2676752784
Short name T505
Test name
Test status
Simulation time 9212634328 ps
CPU time 8.8 seconds
Started Aug 01 05:16:59 PM PDT 24
Finished Aug 01 05:17:08 PM PDT 24
Peak memory 233432 kb
Host smart-7b698a5b-63f0-475d-939e-f3486a51cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676752784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2676752784
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1147037028
Short name T408
Test name
Test status
Simulation time 45416918 ps
CPU time 0.67 seconds
Started Aug 01 05:16:47 PM PDT 24
Finished Aug 01 05:16:48 PM PDT 24
Peak memory 206028 kb
Host smart-13f1334a-effc-408c-936f-2faa3eeb5443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147037028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1147037028
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.149634086
Short name T499
Test name
Test status
Simulation time 559375417 ps
CPU time 2.94 seconds
Started Aug 01 05:17:05 PM PDT 24
Finished Aug 01 05:17:09 PM PDT 24
Peak memory 225204 kb
Host smart-3bef71e9-cf18-4591-94e5-85bfc525c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149634086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.149634086
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3311019844
Short name T1023
Test name
Test status
Simulation time 59113658 ps
CPU time 0.75 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 205920 kb
Host smart-8239d87a-ba1c-4bf9-9d4b-5489cfca1fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311019844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3311019844
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2454324433
Short name T284
Test name
Test status
Simulation time 18604847279 ps
CPU time 84.31 seconds
Started Aug 01 05:17:06 PM PDT 24
Finished Aug 01 05:18:31 PM PDT 24
Peak memory 265508 kb
Host smart-734d33aa-29da-456b-aa78-0cf5aee4816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454324433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2454324433
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3112623227
Short name T535
Test name
Test status
Simulation time 622287963 ps
CPU time 15.57 seconds
Started Aug 01 05:17:05 PM PDT 24
Finished Aug 01 05:17:21 PM PDT 24
Peak memory 225296 kb
Host smart-8cc4dfec-0d7c-4017-8127-351af98f63ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112623227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3112623227
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.243821340
Short name T421
Test name
Test status
Simulation time 7924561840 ps
CPU time 60.63 seconds
Started Aug 01 05:16:48 PM PDT 24
Finished Aug 01 05:17:49 PM PDT 24
Peak memory 257000 kb
Host smart-0f183f9a-c519-44f3-94c4-78a5cb1466d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243821340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.243821340
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.476224277
Short name T619
Test name
Test status
Simulation time 49188300301 ps
CPU time 170.13 seconds
Started Aug 01 05:17:06 PM PDT 24
Finished Aug 01 05:19:56 PM PDT 24
Peak memory 256368 kb
Host smart-3c949a88-7769-4787-b369-ecf9671e0c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476224277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.476224277
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3191799235
Short name T203
Test name
Test status
Simulation time 8048913365 ps
CPU time 18.74 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:17:09 PM PDT 24
Peak memory 224528 kb
Host smart-6683b3ee-993c-48db-98a9-8297d91fe82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191799235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3191799235
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2660333130
Short name T553
Test name
Test status
Simulation time 5002247621 ps
CPU time 19.64 seconds
Started Aug 01 05:17:10 PM PDT 24
Finished Aug 01 05:17:30 PM PDT 24
Peak memory 241628 kb
Host smart-ae8f2591-89bc-4a2a-812c-54c71ea42c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660333130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2660333130
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.627270381
Short name T484
Test name
Test status
Simulation time 30676008 ps
CPU time 1.03 seconds
Started Aug 01 05:16:46 PM PDT 24
Finished Aug 01 05:16:47 PM PDT 24
Peak memory 218392 kb
Host smart-d176dcc0-fb4f-42db-9cfc-b87a65d73abc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627270381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.627270381
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2638007403
Short name T210
Test name
Test status
Simulation time 715647472 ps
CPU time 4.07 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:16:54 PM PDT 24
Peak memory 225196 kb
Host smart-31334723-729e-42d1-9e64-203aaac5278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638007403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2638007403
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1167651667
Short name T680
Test name
Test status
Simulation time 2559861349 ps
CPU time 8.16 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:16:57 PM PDT 24
Peak memory 233528 kb
Host smart-a28d1da2-3445-4145-9c29-8aa0cef9fba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167651667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1167651667
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.903637670
Short name T370
Test name
Test status
Simulation time 474901197 ps
CPU time 7.66 seconds
Started Aug 01 05:17:06 PM PDT 24
Finished Aug 01 05:17:14 PM PDT 24
Peak memory 221072 kb
Host smart-9cc87fff-0b95-4cef-9f35-cebc93c94437
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=903637670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.903637670
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1059430269
Short name T48
Test name
Test status
Simulation time 202299343759 ps
CPU time 968.76 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:32:59 PM PDT 24
Peak memory 266308 kb
Host smart-56cdaf55-99b9-4ad9-9881-4dca19471b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059430269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1059430269
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3295262243
Short name T1012
Test name
Test status
Simulation time 1934918914 ps
CPU time 29.02 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:17:22 PM PDT 24
Peak memory 220012 kb
Host smart-3ba55aad-77bb-42b8-b625-20cbf3dd529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295262243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3295262243
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1838978514
Short name T757
Test name
Test status
Simulation time 6615173567 ps
CPU time 4.52 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:56 PM PDT 24
Peak memory 216956 kb
Host smart-1529b2ef-04cd-41bf-a136-cd3a1c25a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838978514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1838978514
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2682321414
Short name T994
Test name
Test status
Simulation time 99068241 ps
CPU time 1.76 seconds
Started Aug 01 05:16:50 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 216836 kb
Host smart-b32fbb4c-9d6d-41f1-83be-baeadff63eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682321414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2682321414
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2079022062
Short name T51
Test name
Test status
Simulation time 52619026 ps
CPU time 0.83 seconds
Started Aug 01 05:16:49 PM PDT 24
Finished Aug 01 05:16:50 PM PDT 24
Peak memory 206400 kb
Host smart-b27ae0d8-a4c6-47ee-8798-80426e753fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079022062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2079022062
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1602312237
Short name T968
Test name
Test status
Simulation time 9765416711 ps
CPU time 12.43 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:17:04 PM PDT 24
Peak memory 241344 kb
Host smart-4f875b6e-4442-4340-bf70-e3262cfbdfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602312237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1602312237
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3765181720
Short name T403
Test name
Test status
Simulation time 50859185 ps
CPU time 0.73 seconds
Started Aug 01 05:17:02 PM PDT 24
Finished Aug 01 05:17:03 PM PDT 24
Peak memory 205720 kb
Host smart-3f85f52b-d818-40bd-bb61-de75dd0632d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765181720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3765181720
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.305228293
Short name T331
Test name
Test status
Simulation time 68514129 ps
CPU time 2.43 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:16:54 PM PDT 24
Peak memory 232924 kb
Host smart-25352c53-b9d1-4697-a913-e8774a01bb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305228293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.305228293
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3129654896
Short name T705
Test name
Test status
Simulation time 32726751 ps
CPU time 0.76 seconds
Started Aug 01 05:17:05 PM PDT 24
Finished Aug 01 05:17:06 PM PDT 24
Peak memory 207304 kb
Host smart-bbe209c4-dbd2-47bc-967d-7d0d7e304de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129654896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3129654896
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2589398191
Short name T26
Test name
Test status
Simulation time 10091148313 ps
CPU time 116.6 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:19:00 PM PDT 24
Peak memory 255068 kb
Host smart-6533db34-6c11-4c30-bd29-e2789bc9fa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589398191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2589398191
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.972792395
Short name T782
Test name
Test status
Simulation time 38839087761 ps
CPU time 291.15 seconds
Started Aug 01 05:17:00 PM PDT 24
Finished Aug 01 05:21:51 PM PDT 24
Peak memory 252452 kb
Host smart-d9217818-3967-4ea5-9e25-10b31bc4f4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972792395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.972792395
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3909850285
Short name T774
Test name
Test status
Simulation time 9772128120 ps
CPU time 31.63 seconds
Started Aug 01 05:17:05 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 237332 kb
Host smart-fd4b84f4-afc7-4e1e-a6f2-03b6b30636e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909850285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3909850285
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1606290405
Short name T660
Test name
Test status
Simulation time 562004481 ps
CPU time 4.6 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:55 PM PDT 24
Peak memory 232736 kb
Host smart-4e893678-7283-40f8-8e2b-3c0cef485f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606290405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1606290405
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.984580777
Short name T339
Test name
Test status
Simulation time 101421523 ps
CPU time 2.2 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:16:54 PM PDT 24
Peak memory 233372 kb
Host smart-b84d8ad0-f82b-478b-bff4-4b9ed3986066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984580777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.984580777
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3766000799
Short name T460
Test name
Test status
Simulation time 17745367 ps
CPU time 0.96 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:16:53 PM PDT 24
Peak memory 218428 kb
Host smart-ba4466cb-7e38-42fc-94eb-13cb4b104377
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766000799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3766000799
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3796857266
Short name T463
Test name
Test status
Simulation time 615678012 ps
CPU time 2.29 seconds
Started Aug 01 05:17:06 PM PDT 24
Finished Aug 01 05:17:08 PM PDT 24
Peak memory 225140 kb
Host smart-c9027940-0108-42c5-82af-306b424cffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796857266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3796857266
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3672869654
Short name T889
Test name
Test status
Simulation time 6724470049 ps
CPU time 10.16 seconds
Started Aug 01 05:16:53 PM PDT 24
Finished Aug 01 05:17:03 PM PDT 24
Peak memory 233388 kb
Host smart-fbf6c9b3-9287-49fd-8846-242b51a8324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672869654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3672869654
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4126482029
Short name T862
Test name
Test status
Simulation time 5953987488 ps
CPU time 12.25 seconds
Started Aug 01 05:17:00 PM PDT 24
Finished Aug 01 05:17:13 PM PDT 24
Peak memory 222392 kb
Host smart-313b01e6-e4d2-41b0-8721-04b9793ee9bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4126482029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4126482029
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.794061653
Short name T928
Test name
Test status
Simulation time 109391765563 ps
CPU time 256.1 seconds
Started Aug 01 05:17:00 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 256404 kb
Host smart-4b9b3dd9-cdc0-44ce-8ed9-426d1167cd90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794061653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.794061653
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3591080878
Short name T616
Test name
Test status
Simulation time 1355284995 ps
CPU time 7.91 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:17:00 PM PDT 24
Peak memory 216984 kb
Host smart-01be2a4e-7139-476a-a138-b10bf1c19f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591080878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3591080878
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4052530999
Short name T1022
Test name
Test status
Simulation time 3236861528 ps
CPU time 7.04 seconds
Started Aug 01 05:16:51 PM PDT 24
Finished Aug 01 05:16:58 PM PDT 24
Peak memory 216968 kb
Host smart-1721398f-ff91-4a61-aea9-d1df8dfb8d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052530999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4052530999
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4231265804
Short name T467
Test name
Test status
Simulation time 469429148 ps
CPU time 3.76 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:16:56 PM PDT 24
Peak memory 216828 kb
Host smart-747ef78a-e924-4301-8ea7-4a1dd333ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231265804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4231265804
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.405472050
Short name T592
Test name
Test status
Simulation time 194271296 ps
CPU time 0.85 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:16:53 PM PDT 24
Peak memory 206452 kb
Host smart-d70258b8-0526-4239-adc3-5ad37d86bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405472050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.405472050
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2622841234
Short name T624
Test name
Test status
Simulation time 5955463171 ps
CPU time 20.33 seconds
Started Aug 01 05:16:52 PM PDT 24
Finished Aug 01 05:17:12 PM PDT 24
Peak memory 233388 kb
Host smart-1faa0d0a-5bac-47bf-90c5-cdee0bb89309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622841234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2622841234
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1702507759
Short name T594
Test name
Test status
Simulation time 11994202 ps
CPU time 0.73 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 205296 kb
Host smart-c4430f39-589b-4391-9532-2b21499dc2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702507759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
702507759
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1328351594
Short name T427
Test name
Test status
Simulation time 206544180 ps
CPU time 2.32 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 224344 kb
Host smart-81be33e3-d91e-4ab1-9af2-98c6aad7efea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328351594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1328351594
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.981951303
Short name T869
Test name
Test status
Simulation time 17543293 ps
CPU time 0.77 seconds
Started Aug 01 05:15:45 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 206280 kb
Host smart-2e400819-8f30-42ae-add7-0ebe8172f8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981951303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.981951303
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4167949641
Short name T235
Test name
Test status
Simulation time 4985671225 ps
CPU time 72.3 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:17:14 PM PDT 24
Peak memory 258004 kb
Host smart-947e7d16-3270-428e-9680-ccbbcc8fb8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167949641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4167949641
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3811546395
Short name T518
Test name
Test status
Simulation time 22146752909 ps
CPU time 48.31 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:16:32 PM PDT 24
Peak memory 225276 kb
Host smart-bb164865-e4f9-4931-bc86-78f56cf8f941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811546395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3811546395
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.793960868
Short name T309
Test name
Test status
Simulation time 1817087653 ps
CPU time 27.31 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:16:08 PM PDT 24
Peak memory 241668 kb
Host smart-2dfec317-ae9b-4c0c-af7d-ad6bcd988b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793960868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.793960868
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.145194563
Short name T884
Test name
Test status
Simulation time 3558839712 ps
CPU time 32.71 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:16:13 PM PDT 24
Peak memory 241792 kb
Host smart-2ee6d345-defd-498e-8f8f-8f09d1876a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145194563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
145194563
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1644010193
Short name T258
Test name
Test status
Simulation time 2478930415 ps
CPU time 12.74 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:56 PM PDT 24
Peak memory 233432 kb
Host smart-b5b167ac-3207-4ee5-acd4-9dc325fa24de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644010193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1644010193
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3139175705
Short name T73
Test name
Test status
Simulation time 53141859811 ps
CPU time 120.19 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:17:44 PM PDT 24
Peak memory 250776 kb
Host smart-4d54481f-28d4-4886-99bb-d6fff0ea0ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139175705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3139175705
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1835643266
Short name T481
Test name
Test status
Simulation time 17890765 ps
CPU time 1 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 218420 kb
Host smart-fd49c6a8-23fd-451b-96cb-ab8ef169d609
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835643266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1835643266
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1533832514
Short name T633
Test name
Test status
Simulation time 4149589808 ps
CPU time 12.83 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:55 PM PDT 24
Peak memory 234496 kb
Host smart-05033995-89fd-455a-9c15-957cd4bba55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533832514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1533832514
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3854543915
Short name T524
Test name
Test status
Simulation time 56010220 ps
CPU time 2.56 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:45 PM PDT 24
Peak memory 233336 kb
Host smart-038f0666-e621-4091-88b5-4d5d81e64b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854543915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3854543915
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2115341294
Short name T953
Test name
Test status
Simulation time 78640559 ps
CPU time 3.69 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:45 PM PDT 24
Peak memory 223768 kb
Host smart-302cc509-ad10-4683-b5e0-c4d811105731
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2115341294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2115341294
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.179414172
Short name T67
Test name
Test status
Simulation time 194379623 ps
CPU time 1.11 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 235500 kb
Host smart-bc3d3b41-2199-4190-a611-dab7568a7e50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179414172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.179414172
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3908646215
Short name T416
Test name
Test status
Simulation time 20621348385 ps
CPU time 24.77 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:16:06 PM PDT 24
Peak memory 216968 kb
Host smart-02c72c6c-83f1-445a-85d1-7fc2f779fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908646215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3908646215
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.944182357
Short name T787
Test name
Test status
Simulation time 393429550 ps
CPU time 2.8 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 216928 kb
Host smart-f2520440-b3e7-4b78-be4f-84218895ac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944182357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.944182357
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3394231681
Short name T813
Test name
Test status
Simulation time 1026924302 ps
CPU time 2.17 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:44 PM PDT 24
Peak memory 216932 kb
Host smart-ddcde007-3b9d-4d21-87e7-66b48af38d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394231681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3394231681
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3592851752
Short name T634
Test name
Test status
Simulation time 79304222 ps
CPU time 0.96 seconds
Started Aug 01 05:15:41 PM PDT 24
Finished Aug 01 05:15:42 PM PDT 24
Peak memory 206456 kb
Host smart-1a6fb749-c0e4-4beb-b89b-663f0f178be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592851752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3592851752
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1654022433
Short name T532
Test name
Test status
Simulation time 245372616 ps
CPU time 6.58 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:50 PM PDT 24
Peak memory 241464 kb
Host smart-3ba9b055-756c-4225-8642-ec68592988c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654022433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1654022433
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4067249827
Short name T497
Test name
Test status
Simulation time 150246535 ps
CPU time 0.68 seconds
Started Aug 01 05:16:59 PM PDT 24
Finished Aug 01 05:17:00 PM PDT 24
Peak memory 205776 kb
Host smart-27527d0b-107a-4960-ae42-82b9bd7bfa64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067249827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4067249827
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1987917094
Short name T604
Test name
Test status
Simulation time 151436776 ps
CPU time 3.44 seconds
Started Aug 01 05:17:02 PM PDT 24
Finished Aug 01 05:17:06 PM PDT 24
Peak memory 225332 kb
Host smart-d93d19a8-5e54-4815-928c-b68f48f1e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987917094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1987917094
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2711138521
Short name T686
Test name
Test status
Simulation time 13511335 ps
CPU time 0.76 seconds
Started Aug 01 05:17:02 PM PDT 24
Finished Aug 01 05:17:03 PM PDT 24
Peak memory 207396 kb
Host smart-f55676a5-cbdb-4c61-9b05-aa9e6746b623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711138521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2711138521
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3115457716
Short name T428
Test name
Test status
Simulation time 19372284172 ps
CPU time 158.2 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 251600 kb
Host smart-5d757113-4f64-4de1-8e7e-88bda2eaf3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115457716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3115457716
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.439175629
Short name T219
Test name
Test status
Simulation time 6402881085 ps
CPU time 94.02 seconds
Started Aug 01 05:17:01 PM PDT 24
Finished Aug 01 05:18:35 PM PDT 24
Peak memory 256620 kb
Host smart-645152d3-74bd-4465-84a1-973cc5595eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439175629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.439175629
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4958269
Short name T724
Test name
Test status
Simulation time 28846405378 ps
CPU time 254.11 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:21:18 PM PDT 24
Peak memory 264176 kb
Host smart-e1792d4c-be0a-4f68-88b4-bcc21ae27b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4958269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.4958269
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.944901648
Short name T858
Test name
Test status
Simulation time 686810996 ps
CPU time 5.67 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:10 PM PDT 24
Peak memory 237864 kb
Host smart-ca930a0f-5e6c-4459-a139-9f971a21cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944901648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.944901648
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1072144142
Short name T828
Test name
Test status
Simulation time 112403448628 ps
CPU time 199.27 seconds
Started Aug 01 05:16:59 PM PDT 24
Finished Aug 01 05:20:19 PM PDT 24
Peak memory 255508 kb
Host smart-4b22c810-35f3-460c-816b-eead1fe051db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072144142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1072144142
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3427926724
Short name T238
Test name
Test status
Simulation time 3960178957 ps
CPU time 11.56 seconds
Started Aug 01 05:17:07 PM PDT 24
Finished Aug 01 05:17:18 PM PDT 24
Peak memory 233368 kb
Host smart-635dcf6c-8bef-4eba-a6c9-e9fdc5905698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427926724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3427926724
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1139291412
Short name T571
Test name
Test status
Simulation time 12061684475 ps
CPU time 67.19 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:18:11 PM PDT 24
Peak memory 233532 kb
Host smart-95004976-c8ab-4ef6-ad5d-cfb92ba14a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139291412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1139291412
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1984786506
Short name T746
Test name
Test status
Simulation time 10355970862 ps
CPU time 17.41 seconds
Started Aug 01 05:17:02 PM PDT 24
Finished Aug 01 05:17:19 PM PDT 24
Peak memory 225132 kb
Host smart-1ec4fd21-3cf3-4100-9c57-46232f6a552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984786506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1984786506
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2153742987
Short name T840
Test name
Test status
Simulation time 5270175377 ps
CPU time 16.35 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:21 PM PDT 24
Peak memory 241028 kb
Host smart-69055a92-459f-4757-8f03-69fb00be38d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153742987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2153742987
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1175296670
Short name T453
Test name
Test status
Simulation time 167401280 ps
CPU time 4.24 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:07 PM PDT 24
Peak memory 223656 kb
Host smart-e5428b80-20fb-48fa-a858-cfb84fd0e5df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1175296670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1175296670
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1206209482
Short name T20
Test name
Test status
Simulation time 16477892567 ps
CPU time 206.2 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:20:29 PM PDT 24
Peak memory 258056 kb
Host smart-b283c53c-96b4-48cf-bb1d-0901305b6ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206209482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1206209482
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1188396179
Short name T326
Test name
Test status
Simulation time 1877177375 ps
CPU time 7.01 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:10 PM PDT 24
Peak memory 217272 kb
Host smart-c870f654-1f62-4e63-8737-1bf32078c648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188396179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1188396179
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3006371855
Short name T354
Test name
Test status
Simulation time 1582235688 ps
CPU time 4.57 seconds
Started Aug 01 05:17:02 PM PDT 24
Finished Aug 01 05:17:07 PM PDT 24
Peak memory 216952 kb
Host smart-73967c92-3d82-43c6-b0bd-c558e82362f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006371855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3006371855
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.594794486
Short name T377
Test name
Test status
Simulation time 30247165 ps
CPU time 1.17 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:04 PM PDT 24
Peak memory 208460 kb
Host smart-d7ad899a-6c86-4937-8af5-3a852e7fd761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594794486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.594794486
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2943737819
Short name T973
Test name
Test status
Simulation time 41668156 ps
CPU time 0.8 seconds
Started Aug 01 05:17:00 PM PDT 24
Finished Aug 01 05:17:01 PM PDT 24
Peak memory 206508 kb
Host smart-12e886d9-0a82-43cf-975a-fe1f908c40bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943737819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2943737819
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.958180349
Short name T574
Test name
Test status
Simulation time 85985942 ps
CPU time 2.34 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:05 PM PDT 24
Peak memory 225288 kb
Host smart-d71fdb72-38e8-449a-ab46-305c93fcb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958180349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.958180349
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.503194410
Short name T850
Test name
Test status
Simulation time 13797575 ps
CPU time 0.71 seconds
Started Aug 01 05:17:06 PM PDT 24
Finished Aug 01 05:17:07 PM PDT 24
Peak memory 206052 kb
Host smart-6e3065d4-09da-4060-9c88-3971ea32459e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503194410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.503194410
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.618560470
Short name T987
Test name
Test status
Simulation time 17990393114 ps
CPU time 19.7 seconds
Started Aug 01 05:17:02 PM PDT 24
Finished Aug 01 05:17:22 PM PDT 24
Peak memory 233484 kb
Host smart-c730ead7-42ac-4f45-8e45-12f5b3f6e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618560470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.618560470
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3364672758
Short name T539
Test name
Test status
Simulation time 28394056 ps
CPU time 0.77 seconds
Started Aug 01 05:17:00 PM PDT 24
Finished Aug 01 05:17:01 PM PDT 24
Peak memory 205944 kb
Host smart-fea60c31-1b20-40e9-ab1a-31ac7876eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364672758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3364672758
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4005535954
Short name T437
Test name
Test status
Simulation time 64566873677 ps
CPU time 123.08 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:19:07 PM PDT 24
Peak memory 250112 kb
Host smart-e95d6334-12a7-4438-9091-21bbe3a6aa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005535954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4005535954
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1945470999
Short name T552
Test name
Test status
Simulation time 2880212505 ps
CPU time 23.48 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:28 PM PDT 24
Peak memory 233428 kb
Host smart-6d8749c1-e6f5-473b-8374-471de88bd054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945470999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1945470999
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.562658106
Short name T927
Test name
Test status
Simulation time 146584725 ps
CPU time 2.51 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:07 PM PDT 24
Peak memory 219592 kb
Host smart-59ddab09-71e2-4485-88af-6372e555dc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562658106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.562658106
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1189405033
Short name T810
Test name
Test status
Simulation time 11769738194 ps
CPU time 14.7 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:18 PM PDT 24
Peak memory 233500 kb
Host smart-0a31e715-f95a-4f4e-8611-f337e568f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189405033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1189405033
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1779034090
Short name T656
Test name
Test status
Simulation time 51744046 ps
CPU time 2.6 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:06 PM PDT 24
Peak memory 233368 kb
Host smart-dad8e779-abc7-423a-88bf-7e6fc190ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779034090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1779034090
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2561015159
Short name T260
Test name
Test status
Simulation time 7332301673 ps
CPU time 29.97 seconds
Started Aug 01 05:17:00 PM PDT 24
Finished Aug 01 05:17:30 PM PDT 24
Peak memory 233452 kb
Host smart-9b5fd484-90ef-45ea-8c31-3ee32515ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561015159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2561015159
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2924072783
Short name T1015
Test name
Test status
Simulation time 73787136 ps
CPU time 2.6 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:07 PM PDT 24
Peak memory 233360 kb
Host smart-525f3329-a766-47c4-9552-7c2c840ccd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924072783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2924072783
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2122918369
Short name T191
Test name
Test status
Simulation time 13900215407 ps
CPU time 22.61 seconds
Started Aug 01 05:17:06 PM PDT 24
Finished Aug 01 05:17:29 PM PDT 24
Peak memory 241408 kb
Host smart-21e20e45-2e04-4dca-8e84-65bfa7a9db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122918369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2122918369
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2830874482
Short name T841
Test name
Test status
Simulation time 1787164896 ps
CPU time 5.25 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:09 PM PDT 24
Peak memory 221440 kb
Host smart-5a868b0f-bc38-453f-a39b-e1708af3a2a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2830874482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2830874482
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.132062342
Short name T267
Test name
Test status
Simulation time 28668786019 ps
CPU time 253.68 seconds
Started Aug 01 05:17:05 PM PDT 24
Finished Aug 01 05:21:18 PM PDT 24
Peak memory 253892 kb
Host smart-2ad4bc87-bf80-452d-93fd-aa82aaa428ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132062342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.132062342
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3152457043
Short name T693
Test name
Test status
Simulation time 5437340764 ps
CPU time 16.04 seconds
Started Aug 01 05:17:02 PM PDT 24
Finished Aug 01 05:17:18 PM PDT 24
Peak memory 216976 kb
Host smart-5cf90619-b4db-4646-84df-d92223ade031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152457043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3152457043
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1895438993
Short name T980
Test name
Test status
Simulation time 1384575742 ps
CPU time 1.59 seconds
Started Aug 01 05:17:05 PM PDT 24
Finished Aug 01 05:17:06 PM PDT 24
Peak memory 208272 kb
Host smart-50295daa-85fc-49d7-a106-fc802a81ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895438993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1895438993
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.387744074
Short name T456
Test name
Test status
Simulation time 81789833 ps
CPU time 1.32 seconds
Started Aug 01 05:16:59 PM PDT 24
Finished Aug 01 05:17:00 PM PDT 24
Peak memory 216780 kb
Host smart-eb4ff20a-f70e-4f0f-92e0-dfd738657b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387744074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.387744074
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2977191647
Short name T715
Test name
Test status
Simulation time 159782808 ps
CPU time 0.97 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:04 PM PDT 24
Peak memory 207620 kb
Host smart-579ac210-9b28-491b-9b13-7b6535baf70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977191647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2977191647
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.844644426
Short name T639
Test name
Test status
Simulation time 855720221 ps
CPU time 4.67 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:08 PM PDT 24
Peak memory 233480 kb
Host smart-a1a76eb2-ddfb-413c-81ff-f14afd16df9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844644426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.844644426
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1348780509
Short name T872
Test name
Test status
Simulation time 95785638 ps
CPU time 0.73 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:12 PM PDT 24
Peak memory 205852 kb
Host smart-efeb7b31-825b-4bb1-a82c-0ed9dc019b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348780509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1348780509
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2014932796
Short name T696
Test name
Test status
Simulation time 186700980 ps
CPU time 2.57 seconds
Started Aug 01 05:17:09 PM PDT 24
Finished Aug 01 05:17:12 PM PDT 24
Peak memory 233284 kb
Host smart-555e9fef-5959-4f14-aad2-26d74efc7b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014932796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2014932796
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.199893441
Short name T448
Test name
Test status
Simulation time 62866611 ps
CPU time 0.8 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:04 PM PDT 24
Peak memory 207132 kb
Host smart-be3316b7-7bfa-440f-b5d0-b1e507fa22f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199893441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.199893441
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1201407079
Short name T1021
Test name
Test status
Simulation time 12870548466 ps
CPU time 76.25 seconds
Started Aug 01 05:17:14 PM PDT 24
Finished Aug 01 05:18:30 PM PDT 24
Peak memory 235612 kb
Host smart-b2f8b257-0158-4d86-afd6-12bb6b7357f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201407079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1201407079
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1112467809
Short name T638
Test name
Test status
Simulation time 1818712134 ps
CPU time 44.8 seconds
Started Aug 01 05:17:12 PM PDT 24
Finished Aug 01 05:17:57 PM PDT 24
Peak memory 252576 kb
Host smart-5d5ee715-f24b-4a9d-bd72-37346ec00d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112467809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1112467809
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1193830891
Short name T194
Test name
Test status
Simulation time 30851824818 ps
CPU time 321.59 seconds
Started Aug 01 05:17:13 PM PDT 24
Finished Aug 01 05:22:34 PM PDT 24
Peak memory 265540 kb
Host smart-bbe6db1f-bd8c-41fc-a43b-17c6492f2ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193830891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1193830891
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3413267381
Short name T740
Test name
Test status
Simulation time 2843160199 ps
CPU time 9.18 seconds
Started Aug 01 05:17:10 PM PDT 24
Finished Aug 01 05:17:19 PM PDT 24
Peak memory 235404 kb
Host smart-3419b91e-8545-4d49-a612-eefe6b2805a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413267381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3413267381
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2046941853
Short name T812
Test name
Test status
Simulation time 14477382200 ps
CPU time 57.5 seconds
Started Aug 01 05:17:16 PM PDT 24
Finished Aug 01 05:18:14 PM PDT 24
Peak memory 253820 kb
Host smart-1b70d0ae-79d1-4726-98a0-dd49abf9a909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046941853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2046941853
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2101053213
Short name T208
Test name
Test status
Simulation time 634214302 ps
CPU time 6.28 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:17 PM PDT 24
Peak memory 233400 kb
Host smart-d18e9244-fccf-4345-b121-d591d254118e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101053213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2101053213
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2363578136
Short name T91
Test name
Test status
Simulation time 2032866431 ps
CPU time 17.18 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:28 PM PDT 24
Peak memory 225152 kb
Host smart-958be18d-863f-425e-b8ca-48f6f0c98f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363578136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2363578136
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.144291984
Short name T790
Test name
Test status
Simulation time 6810568815 ps
CPU time 3.96 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:08 PM PDT 24
Peak memory 233520 kb
Host smart-cd3ba065-a3ec-4e44-afc7-60a8fde4c9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144291984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.144291984
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4048450531
Short name T470
Test name
Test status
Simulation time 4353303694 ps
CPU time 15.09 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:20 PM PDT 24
Peak memory 233548 kb
Host smart-ec3239eb-376a-4d74-9c10-12fe9f52ab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048450531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4048450531
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4075195349
Short name T677
Test name
Test status
Simulation time 2932028822 ps
CPU time 7.33 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:18 PM PDT 24
Peak memory 220048 kb
Host smart-5c446128-2315-4287-a27d-109e32eb8c71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4075195349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4075195349
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.530085949
Short name T159
Test name
Test status
Simulation time 1036623525 ps
CPU time 4.72 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:16 PM PDT 24
Peak memory 225156 kb
Host smart-fc53af15-c6a0-475e-80b0-1f6f72d7badd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530085949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.530085949
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1410181689
Short name T503
Test name
Test status
Simulation time 4316847979 ps
CPU time 19.93 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:24 PM PDT 24
Peak memory 217012 kb
Host smart-f88c0b32-a3ff-4210-84d7-f86ecbf11d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410181689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1410181689
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1272152556
Short name T839
Test name
Test status
Simulation time 946419691 ps
CPU time 7.15 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:11 PM PDT 24
Peak memory 216824 kb
Host smart-02c8ae31-a117-4b0a-9ef5-97ff1b49326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272152556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1272152556
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2521788588
Short name T560
Test name
Test status
Simulation time 24712929 ps
CPU time 1.05 seconds
Started Aug 01 05:17:04 PM PDT 24
Finished Aug 01 05:17:05 PM PDT 24
Peak memory 208552 kb
Host smart-8630b259-8aba-49ba-82be-d9dd5ed77018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521788588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2521788588
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.104303330
Short name T692
Test name
Test status
Simulation time 254592625 ps
CPU time 0.8 seconds
Started Aug 01 05:17:03 PM PDT 24
Finished Aug 01 05:17:04 PM PDT 24
Peak memory 206568 kb
Host smart-7f3247c6-9aeb-4be2-9e8a-2d58fea97f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104303330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.104303330
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.334917497
Short name T988
Test name
Test status
Simulation time 803734973 ps
CPU time 5.44 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:26 PM PDT 24
Peak memory 233420 kb
Host smart-f56997ef-e073-4c77-9cba-62dd135eb9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334917497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.334917497
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.857935894
Short name T651
Test name
Test status
Simulation time 13551100 ps
CPU time 0.71 seconds
Started Aug 01 05:17:13 PM PDT 24
Finished Aug 01 05:17:14 PM PDT 24
Peak memory 205296 kb
Host smart-b7054a12-9bbe-4c10-b9d3-3f259fa89acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857935894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.857935894
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.501247679
Short name T827
Test name
Test status
Simulation time 2957459086 ps
CPU time 35.44 seconds
Started Aug 01 05:17:19 PM PDT 24
Finished Aug 01 05:17:54 PM PDT 24
Peak memory 225252 kb
Host smart-e838fbd8-db6b-4706-9514-12dc4a25fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501247679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.501247679
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1491854622
Short name T387
Test name
Test status
Simulation time 15137724 ps
CPU time 0.79 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:21 PM PDT 24
Peak memory 206012 kb
Host smart-145fdaa4-b783-4092-91b3-fde4b886630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491854622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1491854622
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3427970609
Short name T925
Test name
Test status
Simulation time 3849470228 ps
CPU time 83.73 seconds
Started Aug 01 05:17:18 PM PDT 24
Finished Aug 01 05:18:42 PM PDT 24
Peak memory 266196 kb
Host smart-7ef67b82-5771-4b7e-a9e5-fa0878219b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427970609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3427970609
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3407348212
Short name T45
Test name
Test status
Simulation time 4872273259 ps
CPU time 65.9 seconds
Started Aug 01 05:17:15 PM PDT 24
Finished Aug 01 05:18:21 PM PDT 24
Peak memory 249964 kb
Host smart-7185c9aa-e83f-4f69-85df-3443dd89d5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407348212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3407348212
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4112175018
Short name T33
Test name
Test status
Simulation time 142864771 ps
CPU time 5.48 seconds
Started Aug 01 05:17:13 PM PDT 24
Finished Aug 01 05:17:18 PM PDT 24
Peak memory 235784 kb
Host smart-c2bc23cd-7327-4886-9379-8946212fdc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112175018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4112175018
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2784564141
Short name T1005
Test name
Test status
Simulation time 51983177148 ps
CPU time 45.41 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:18:07 PM PDT 24
Peak memory 256628 kb
Host smart-23b951cb-8ae5-426c-84a5-7371f0665855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784564141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2784564141
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2224958918
Short name T654
Test name
Test status
Simulation time 4711612491 ps
CPU time 12.05 seconds
Started Aug 01 05:17:13 PM PDT 24
Finished Aug 01 05:17:26 PM PDT 24
Peak memory 228328 kb
Host smart-828d54e5-7930-4a9c-b4fe-3e64cc8816a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224958918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2224958918
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2327412197
Short name T661
Test name
Test status
Simulation time 10508423396 ps
CPU time 47.73 seconds
Started Aug 01 05:17:19 PM PDT 24
Finished Aug 01 05:18:07 PM PDT 24
Peak memory 241336 kb
Host smart-c84c9a09-480c-4623-9442-682104eab19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327412197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2327412197
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3806157164
Short name T821
Test name
Test status
Simulation time 712252916 ps
CPU time 3.03 seconds
Started Aug 01 05:17:10 PM PDT 24
Finished Aug 01 05:17:13 PM PDT 24
Peak memory 233420 kb
Host smart-48ede94e-1885-45eb-a42d-9f69d3bd5373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806157164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3806157164
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.388011240
Short name T919
Test name
Test status
Simulation time 11306014355 ps
CPU time 8.91 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:20 PM PDT 24
Peak memory 225176 kb
Host smart-e788458e-0c8b-4b75-a8ec-dae863900149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388011240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.388011240
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3215868398
Short name T78
Test name
Test status
Simulation time 904603259 ps
CPU time 4.43 seconds
Started Aug 01 05:17:15 PM PDT 24
Finished Aug 01 05:17:19 PM PDT 24
Peak memory 219628 kb
Host smart-fa28faea-e6e6-4d9f-b38f-cca5e184d94a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3215868398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3215868398
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3724775986
Short name T769
Test name
Test status
Simulation time 54749505 ps
CPU time 0.99 seconds
Started Aug 01 05:17:18 PM PDT 24
Finished Aug 01 05:17:19 PM PDT 24
Peak memory 207396 kb
Host smart-718a6b6d-321f-4268-9582-7749a7aabaa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724775986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3724775986
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.343699179
Short name T961
Test name
Test status
Simulation time 4654203829 ps
CPU time 25.46 seconds
Started Aug 01 05:17:10 PM PDT 24
Finished Aug 01 05:17:36 PM PDT 24
Peak memory 218612 kb
Host smart-3bc51f2e-42b0-4254-b7d7-04ff03b9b087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343699179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.343699179
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4192334265
Short name T495
Test name
Test status
Simulation time 37938560 ps
CPU time 0.72 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:22 PM PDT 24
Peak memory 206240 kb
Host smart-d1af4ec9-478a-4e6b-860e-506ff030f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192334265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4192334265
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1370848571
Short name T752
Test name
Test status
Simulation time 64219833 ps
CPU time 1.34 seconds
Started Aug 01 05:17:13 PM PDT 24
Finished Aug 01 05:17:14 PM PDT 24
Peak memory 217048 kb
Host smart-ee79a7cd-5a5d-4dae-a640-0409f79b0104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370848571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1370848571
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3133467635
Short name T537
Test name
Test status
Simulation time 24898924 ps
CPU time 0.71 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:12 PM PDT 24
Peak memory 206496 kb
Host smart-8a423102-2660-437f-9cdc-95ff66590606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133467635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3133467635
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3530375815
Short name T271
Test name
Test status
Simulation time 1016897407 ps
CPU time 6.44 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:18 PM PDT 24
Peak memory 225152 kb
Host smart-a6a187ac-364a-4bc0-8965-ab9e5b12f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530375815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3530375815
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.376880396
Short name T504
Test name
Test status
Simulation time 15416301 ps
CPU time 0.72 seconds
Started Aug 01 05:17:20 PM PDT 24
Finished Aug 01 05:17:21 PM PDT 24
Peak memory 205172 kb
Host smart-2b7fc049-1da7-4951-a591-54593f54a8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376880396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.376880396
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2514943507
Short name T776
Test name
Test status
Simulation time 569168928 ps
CPU time 4.71 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:26 PM PDT 24
Peak memory 233184 kb
Host smart-aba11947-ab0d-47dd-ba2b-eab29ea02c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514943507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2514943507
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4053593616
Short name T712
Test name
Test status
Simulation time 48862241 ps
CPU time 0.75 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:11 PM PDT 24
Peak memory 207244 kb
Host smart-31181c0e-438d-4e9d-9398-ba1786dd3715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053593616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4053593616
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2723873725
Short name T165
Test name
Test status
Simulation time 9574816013 ps
CPU time 40.18 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:18:02 PM PDT 24
Peak memory 254656 kb
Host smart-e366c68c-c10b-4855-87af-c5b9c3bf497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723873725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2723873725
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3938592480
Short name T1020
Test name
Test status
Simulation time 45169170659 ps
CPU time 132.67 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 251024 kb
Host smart-4048deb5-07ce-478c-9002-7ad9e5641a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938592480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3938592480
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2229045106
Short name T313
Test name
Test status
Simulation time 303042061 ps
CPU time 9.68 seconds
Started Aug 01 05:17:14 PM PDT 24
Finished Aug 01 05:17:24 PM PDT 24
Peak memory 235544 kb
Host smart-18bddc9c-7622-43bb-bda5-0f73e1046b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229045106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2229045106
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.371205267
Short name T959
Test name
Test status
Simulation time 155597269742 ps
CPU time 287.35 seconds
Started Aug 01 05:17:15 PM PDT 24
Finished Aug 01 05:22:02 PM PDT 24
Peak memory 249956 kb
Host smart-b9c6e940-9d62-41b9-a4ea-195e4e088253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371205267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.371205267
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2097602080
Short name T718
Test name
Test status
Simulation time 4034259222 ps
CPU time 17.27 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:29 PM PDT 24
Peak memory 233548 kb
Host smart-5e6836fb-3e87-4fd6-a5f4-7167e448995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097602080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2097602080
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2948363081
Short name T914
Test name
Test status
Simulation time 4566250870 ps
CPU time 46 seconds
Started Aug 01 05:17:18 PM PDT 24
Finished Aug 01 05:18:04 PM PDT 24
Peak memory 240052 kb
Host smart-65671c8e-aac8-42d0-9691-2d9e148acaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948363081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2948363081
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.334976872
Short name T288
Test name
Test status
Simulation time 2973000425 ps
CPU time 11.06 seconds
Started Aug 01 05:17:10 PM PDT 24
Finished Aug 01 05:17:21 PM PDT 24
Peak memory 225220 kb
Host smart-669333d5-a5cd-4e9a-96bf-f3373cad9b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334976872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.334976872
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3644938071
Short name T225
Test name
Test status
Simulation time 5892215454 ps
CPU time 7.49 seconds
Started Aug 01 05:17:13 PM PDT 24
Finished Aug 01 05:17:21 PM PDT 24
Peak memory 233424 kb
Host smart-29dff1c7-af9f-44b1-9915-b520e5392a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644938071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3644938071
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1322245844
Short name T500
Test name
Test status
Simulation time 1709811015 ps
CPU time 7.18 seconds
Started Aug 01 05:17:23 PM PDT 24
Finished Aug 01 05:17:30 PM PDT 24
Peak memory 223688 kb
Host smart-ed8c96d2-52a4-4bbe-a543-c1972f11c7e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322245844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1322245844
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3683837543
Short name T303
Test name
Test status
Simulation time 146910115645 ps
CPU time 420.84 seconds
Started Aug 01 05:17:23 PM PDT 24
Finished Aug 01 05:24:24 PM PDT 24
Peak memory 272760 kb
Host smart-e31efea2-d01e-4f6d-b16b-75678d3e33f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683837543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3683837543
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3547373657
Short name T423
Test name
Test status
Simulation time 2785969539 ps
CPU time 15.09 seconds
Started Aug 01 05:17:20 PM PDT 24
Finished Aug 01 05:17:35 PM PDT 24
Peak memory 220420 kb
Host smart-f0cd34ed-7dad-489f-8d58-d0e908b80a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547373657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3547373657
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1346468751
Short name T972
Test name
Test status
Simulation time 3369143881 ps
CPU time 3.07 seconds
Started Aug 01 05:17:17 PM PDT 24
Finished Aug 01 05:17:20 PM PDT 24
Peak memory 216996 kb
Host smart-b6aa2680-7e7e-4bfd-bde4-06d672fd1714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346468751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1346468751
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2852147898
Short name T878
Test name
Test status
Simulation time 73591896 ps
CPU time 1.74 seconds
Started Aug 01 05:17:14 PM PDT 24
Finished Aug 01 05:17:15 PM PDT 24
Peak memory 217004 kb
Host smart-856122d8-3396-4c47-a060-57e215b7efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852147898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2852147898
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.63887784
Short name T374
Test name
Test status
Simulation time 173898193 ps
CPU time 0.81 seconds
Started Aug 01 05:17:11 PM PDT 24
Finished Aug 01 05:17:12 PM PDT 24
Peak memory 206476 kb
Host smart-0dd84159-d3ab-4fe9-af53-331a5b90b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63887784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.63887784
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2492673903
Short name T418
Test name
Test status
Simulation time 3635799355 ps
CPU time 11.4 seconds
Started Aug 01 05:17:19 PM PDT 24
Finished Aug 01 05:17:30 PM PDT 24
Peak memory 233424 kb
Host smart-d687d9bd-7d4e-466c-877a-d2562252abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492673903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2492673903
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1250966518
Short name T1018
Test name
Test status
Simulation time 875625381 ps
CPU time 5.05 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:26 PM PDT 24
Peak memory 225124 kb
Host smart-d4b11394-5ccf-4fd6-803e-c3dce12b8278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250966518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1250966518
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.715174170
Short name T606
Test name
Test status
Simulation time 59599570 ps
CPU time 0.76 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:22 PM PDT 24
Peak memory 206240 kb
Host smart-a28409e1-f501-448b-9cbe-d1dba634c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715174170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.715174170
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.397681026
Short name T413
Test name
Test status
Simulation time 21993487 ps
CPU time 0.82 seconds
Started Aug 01 05:17:37 PM PDT 24
Finished Aug 01 05:17:38 PM PDT 24
Peak memory 216472 kb
Host smart-bccd3969-0bcc-4a25-913e-a8eb280e040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397681026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.397681026
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1938485566
Short name T572
Test name
Test status
Simulation time 218974751 ps
CPU time 0.86 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:35 PM PDT 24
Peak memory 217468 kb
Host smart-3d960abc-c46b-40ad-9950-67c4610afd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938485566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1938485566
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2840297791
Short name T905
Test name
Test status
Simulation time 7154024702 ps
CPU time 21.08 seconds
Started Aug 01 05:17:22 PM PDT 24
Finished Aug 01 05:17:43 PM PDT 24
Peak memory 249760 kb
Host smart-c25c8baf-e679-43dc-9fda-ebd9a420457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840297791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2840297791
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2667132264
Short name T863
Test name
Test status
Simulation time 12792306377 ps
CPU time 65.19 seconds
Started Aug 01 05:17:22 PM PDT 24
Finished Aug 01 05:18:27 PM PDT 24
Peak memory 249908 kb
Host smart-d71dfdae-89e5-45d0-ab0d-13431f2b6642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667132264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2667132264
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2804151795
Short name T965
Test name
Test status
Simulation time 1987065331 ps
CPU time 23.8 seconds
Started Aug 01 05:17:23 PM PDT 24
Finished Aug 01 05:17:47 PM PDT 24
Peak memory 233340 kb
Host smart-ceec33b9-3778-48e6-8a12-c3d81ad62e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804151795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2804151795
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3881424634
Short name T710
Test name
Test status
Simulation time 551286644 ps
CPU time 6.33 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:28 PM PDT 24
Peak memory 240076 kb
Host smart-74fdf6eb-51cd-4109-ae3f-afa1b9d21898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881424634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3881424634
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1866250684
Short name T771
Test name
Test status
Simulation time 842574689 ps
CPU time 4.77 seconds
Started Aug 01 05:17:26 PM PDT 24
Finished Aug 01 05:17:30 PM PDT 24
Peak memory 233436 kb
Host smart-a408a445-c5ff-49fe-b6be-a620c530c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866250684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1866250684
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.231299407
Short name T985
Test name
Test status
Simulation time 3220208947 ps
CPU time 13.89 seconds
Started Aug 01 05:17:26 PM PDT 24
Finished Aug 01 05:17:40 PM PDT 24
Peak memory 233504 kb
Host smart-26afd9f2-2802-4f33-9de3-6b6f131ad2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231299407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.231299407
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3839853143
Short name T419
Test name
Test status
Simulation time 1185617736 ps
CPU time 11.93 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:47 PM PDT 24
Peak memory 222196 kb
Host smart-c6a3c94a-28b8-40e1-852f-706c153c8c04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839853143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3839853143
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3227108552
Short name T34
Test name
Test status
Simulation time 21543643637 ps
CPU time 201.55 seconds
Started Aug 01 05:17:37 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 251108 kb
Host smart-0c5c5962-8168-4743-9c26-5a8ab2455d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227108552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3227108552
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2274133426
Short name T74
Test name
Test status
Simulation time 909565682 ps
CPU time 5.95 seconds
Started Aug 01 05:17:21 PM PDT 24
Finished Aug 01 05:17:27 PM PDT 24
Peak memory 216944 kb
Host smart-f0bfe531-6ff0-4c6e-83c5-9c9a1592dea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274133426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2274133426
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1165102424
Short name T407
Test name
Test status
Simulation time 4361527548 ps
CPU time 9.48 seconds
Started Aug 01 05:17:22 PM PDT 24
Finished Aug 01 05:17:32 PM PDT 24
Peak memory 216912 kb
Host smart-ab97fef9-9d93-4939-bcbf-9890bc6b6cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165102424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1165102424
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.46486421
Short name T528
Test name
Test status
Simulation time 673823441 ps
CPU time 2.41 seconds
Started Aug 01 05:17:22 PM PDT 24
Finished Aug 01 05:17:24 PM PDT 24
Peak memory 216908 kb
Host smart-e40bd11b-6fdf-42ee-bd32-c17c20d265df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46486421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.46486421
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1924468125
Short name T365
Test name
Test status
Simulation time 15827856 ps
CPU time 0.73 seconds
Started Aug 01 05:17:20 PM PDT 24
Finished Aug 01 05:17:21 PM PDT 24
Peak memory 206460 kb
Host smart-d8dcaaaf-6564-45bf-8f51-12f9956a2433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924468125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1924468125
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2677886687
Short name T764
Test name
Test status
Simulation time 1186404074 ps
CPU time 7.82 seconds
Started Aug 01 05:17:20 PM PDT 24
Finished Aug 01 05:17:28 PM PDT 24
Peak memory 225204 kb
Host smart-8aad75a6-ebc3-440e-8048-0201bd717b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677886687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2677886687
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3233916388
Short name T355
Test name
Test status
Simulation time 18402290 ps
CPU time 0.72 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:36 PM PDT 24
Peak memory 205784 kb
Host smart-dc4380ac-8b98-4f41-b70f-53a98190011f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233916388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3233916388
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.445869842
Short name T648
Test name
Test status
Simulation time 4074847964 ps
CPU time 9.73 seconds
Started Aug 01 05:17:33 PM PDT 24
Finished Aug 01 05:17:43 PM PDT 24
Peak memory 233488 kb
Host smart-7561865a-052d-475e-a0fe-136a4116e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445869842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.445869842
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4002788686
Short name T343
Test name
Test status
Simulation time 54156323 ps
CPU time 0.76 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 207364 kb
Host smart-1a91a201-6035-41a4-9139-5ee40a6dd46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002788686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4002788686
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1462925820
Short name T429
Test name
Test status
Simulation time 9104574968 ps
CPU time 63.51 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:18:39 PM PDT 24
Peak memory 250076 kb
Host smart-6176155e-62dc-46b9-a605-70b3c49a6f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462925820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1462925820
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2383720575
Short name T699
Test name
Test status
Simulation time 5154269743 ps
CPU time 94.88 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:19:11 PM PDT 24
Peak memory 255096 kb
Host smart-f0298ca8-751a-4ecb-827d-7cb141e1ead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383720575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2383720575
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1702152148
Short name T422
Test name
Test status
Simulation time 40671691334 ps
CPU time 122.34 seconds
Started Aug 01 05:17:32 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 252468 kb
Host smart-92821f85-1295-4eae-96b8-f8592693b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702152148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1702152148
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3077546138
Short name T1016
Test name
Test status
Simulation time 13199594600 ps
CPU time 35.37 seconds
Started Aug 01 05:17:38 PM PDT 24
Finished Aug 01 05:18:13 PM PDT 24
Peak memory 233416 kb
Host smart-46f99825-128c-452b-9b7b-869fdde0aeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077546138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3077546138
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3882401641
Short name T480
Test name
Test status
Simulation time 57189844430 ps
CPU time 98.86 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 249892 kb
Host smart-0131bc49-06be-4d16-a43e-1baaed351bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882401641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3882401641
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1687615659
Short name T228
Test name
Test status
Simulation time 1152937649 ps
CPU time 9.15 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:44 PM PDT 24
Peak memory 233288 kb
Host smart-acdc29d8-d236-4613-aa93-d8913382791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687615659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1687615659
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2846682990
Short name T733
Test name
Test status
Simulation time 644346732 ps
CPU time 10.52 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:46 PM PDT 24
Peak memory 241536 kb
Host smart-7853a729-28ee-4968-86fc-4efd5268097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846682990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2846682990
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2336130954
Short name T294
Test name
Test status
Simulation time 71594163446 ps
CPU time 24.09 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:58 PM PDT 24
Peak memory 225184 kb
Host smart-939ba155-e16d-430e-89a5-bcfb31915d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336130954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2336130954
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1970882234
Short name T213
Test name
Test status
Simulation time 3352685516 ps
CPU time 11.61 seconds
Started Aug 01 05:17:32 PM PDT 24
Finished Aug 01 05:17:44 PM PDT 24
Peak memory 225296 kb
Host smart-b5a08e9a-16f3-4e2c-8a6e-49f80c023729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970882234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1970882234
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.723243701
Short name T830
Test name
Test status
Simulation time 4252011765 ps
CPU time 10.06 seconds
Started Aug 01 05:17:33 PM PDT 24
Finished Aug 01 05:17:43 PM PDT 24
Peak memory 219936 kb
Host smart-2c085f2e-c533-4be4-a21a-85216efe07f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=723243701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.723243701
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1099768699
Short name T282
Test name
Test status
Simulation time 23060973646 ps
CPU time 285.38 seconds
Started Aug 01 05:17:38 PM PDT 24
Finished Aug 01 05:22:23 PM PDT 24
Peak memory 265108 kb
Host smart-001faadf-1e7a-4ff6-b53b-2679bd6713c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099768699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1099768699
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.599822559
Short name T1007
Test name
Test status
Simulation time 2232057458 ps
CPU time 5.88 seconds
Started Aug 01 05:17:32 PM PDT 24
Finished Aug 01 05:17:38 PM PDT 24
Peak memory 216960 kb
Host smart-99f1180e-6989-4d21-ab19-c419f4b38bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599822559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.599822559
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3442101857
Short name T458
Test name
Test status
Simulation time 21833509 ps
CPU time 0.73 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:35 PM PDT 24
Peak memory 206008 kb
Host smart-6d75a3a1-0c1d-45fc-b777-508431a03234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442101857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3442101857
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3209498245
Short name T494
Test name
Test status
Simulation time 246295931 ps
CPU time 1.76 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 216920 kb
Host smart-c2258ea6-8be4-4f83-9832-fa137b528dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209498245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3209498245
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.223419672
Short name T369
Test name
Test status
Simulation time 77302607 ps
CPU time 0.78 seconds
Started Aug 01 05:17:33 PM PDT 24
Finished Aug 01 05:17:34 PM PDT 24
Peak memory 206548 kb
Host smart-813b1c33-503c-43a9-b360-c6937ad4132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223419672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.223419672
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.724624894
Short name T7
Test name
Test status
Simulation time 1577379771 ps
CPU time 6.22 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:41 PM PDT 24
Peak memory 225172 kb
Host smart-b2dc8121-3b5e-43cf-80d1-80635db3a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724624894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.724624894
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2269002360
Short name T756
Test name
Test status
Simulation time 40314855 ps
CPU time 0.71 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 205756 kb
Host smart-d3dd6333-38a9-4cee-a559-7ed540d8d53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269002360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2269002360
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4094919785
Short name T688
Test name
Test status
Simulation time 3951688840 ps
CPU time 11 seconds
Started Aug 01 05:17:32 PM PDT 24
Finished Aug 01 05:17:44 PM PDT 24
Peak memory 233548 kb
Host smart-9c4caeb1-fc58-45fb-bdc5-0b4161989a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094919785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4094919785
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3186491783
Short name T886
Test name
Test status
Simulation time 17364951 ps
CPU time 0.81 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 206964 kb
Host smart-9bd7fc2b-9ef5-483f-bde8-cdb1c6f5f7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186491783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3186491783
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2766790584
Short name T202
Test name
Test status
Simulation time 2844080791 ps
CPU time 35.44 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:18:10 PM PDT 24
Peak memory 249804 kb
Host smart-7e0ebf37-f7bf-4e48-b0f7-bbe0ef883f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766790584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2766790584
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1375966217
Short name T35
Test name
Test status
Simulation time 17422494082 ps
CPU time 131.57 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:19:47 PM PDT 24
Peak memory 256112 kb
Host smart-746f512b-a485-4c54-9c3a-33bd7ffe00fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375966217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1375966217
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1591423220
Short name T887
Test name
Test status
Simulation time 12059282908 ps
CPU time 46.33 seconds
Started Aug 01 05:17:33 PM PDT 24
Finished Aug 01 05:18:20 PM PDT 24
Peak memory 237984 kb
Host smart-cd5f1995-a36d-4b72-bba9-444bc576c3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591423220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1591423220
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2298354223
Short name T780
Test name
Test status
Simulation time 1041654316 ps
CPU time 7.09 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:42 PM PDT 24
Peak memory 249808 kb
Host smart-8f9bee87-f1f3-4296-9f13-14345573643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298354223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2298354223
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.603519462
Short name T877
Test name
Test status
Simulation time 34303912 ps
CPU time 0.77 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:36 PM PDT 24
Peak memory 216348 kb
Host smart-e38570b9-ae08-4b56-a964-17faefe77f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603519462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.603519462
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3549891859
Short name T922
Test name
Test status
Simulation time 1677985390 ps
CPU time 7.21 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:43 PM PDT 24
Peak memory 233292 kb
Host smart-dd0c3d6c-f895-489b-ac35-9b15ab2994dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549891859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3549891859
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1339840461
Short name T414
Test name
Test status
Simulation time 1510095688 ps
CPU time 5.52 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:41 PM PDT 24
Peak memory 233416 kb
Host smart-60377994-2459-4ebd-8bb4-c7edb2f3cd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339840461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1339840461
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1089795145
Short name T615
Test name
Test status
Simulation time 347070951 ps
CPU time 2.72 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:39 PM PDT 24
Peak memory 225108 kb
Host smart-ce1c996b-44de-4022-9ba8-1b1157e624ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089795145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1089795145
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.265883708
Short name T837
Test name
Test status
Simulation time 348188694 ps
CPU time 5.21 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:39 PM PDT 24
Peak memory 223044 kb
Host smart-956ba1a1-f4e3-4443-9c7d-0e58c2d288ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=265883708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.265883708
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2290052459
Short name T50
Test name
Test status
Simulation time 5496578796 ps
CPU time 84.87 seconds
Started Aug 01 05:17:38 PM PDT 24
Finished Aug 01 05:19:03 PM PDT 24
Peak memory 250564 kb
Host smart-bb57df00-53f3-4180-bd10-4f0dc0c5c842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290052459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2290052459
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3100915198
Short name T745
Test name
Test status
Simulation time 25283899158 ps
CPU time 28.37 seconds
Started Aug 01 05:17:33 PM PDT 24
Finished Aug 01 05:18:01 PM PDT 24
Peak memory 217364 kb
Host smart-a7ca198d-0413-4bf2-a145-6b380c8857a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100915198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3100915198
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4082687096
Short name T409
Test name
Test status
Simulation time 694649282 ps
CPU time 2.95 seconds
Started Aug 01 05:17:32 PM PDT 24
Finished Aug 01 05:17:35 PM PDT 24
Peak memory 217020 kb
Host smart-f811a919-f510-41f6-b2d0-7cc359dff020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082687096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4082687096
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3245393092
Short name T623
Test name
Test status
Simulation time 99472373 ps
CPU time 0.85 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 206976 kb
Host smart-a23f21b0-a226-4ae9-9f51-dad644650aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245393092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3245393092
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2915488639
Short name T517
Test name
Test status
Simulation time 11237421 ps
CPU time 0.72 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:36 PM PDT 24
Peak memory 206000 kb
Host smart-8955637f-1791-47c4-87c0-7a20333bd504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915488639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2915488639
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.751924618
Short name T944
Test name
Test status
Simulation time 3583525899 ps
CPU time 3.52 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:40 PM PDT 24
Peak memory 233432 kb
Host smart-b5655852-2daf-45c8-b872-ac66efff2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751924618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.751924618
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2769647179
Short name T853
Test name
Test status
Simulation time 11358389 ps
CPU time 0.71 seconds
Started Aug 01 05:17:48 PM PDT 24
Finished Aug 01 05:17:49 PM PDT 24
Peak memory 205900 kb
Host smart-9b6fc60b-b4f7-442b-b9de-3abac6365eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769647179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2769647179
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2934622190
Short name T107
Test name
Test status
Simulation time 233226041 ps
CPU time 3.32 seconds
Started Aug 01 05:17:48 PM PDT 24
Finished Aug 01 05:17:52 PM PDT 24
Peak memory 233324 kb
Host smart-1ccde5aa-f289-498b-96fe-455eb8ae05f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934622190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2934622190
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1543207744
Short name T870
Test name
Test status
Simulation time 59931026 ps
CPU time 0.8 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 206984 kb
Host smart-4a324026-536d-40e7-a4ba-bd9837760c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543207744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1543207744
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.796077127
Short name T990
Test name
Test status
Simulation time 45311191374 ps
CPU time 232.39 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:21:43 PM PDT 24
Peak memory 274080 kb
Host smart-5de35210-4201-4394-a1e6-5911bfc571f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796077127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.796077127
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.801995440
Short name T527
Test name
Test status
Simulation time 3647708581 ps
CPU time 83.53 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:19:14 PM PDT 24
Peak memory 249852 kb
Host smart-89f04ba9-5e1a-4360-8c88-3bb6607391b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801995440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.801995440
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4008198325
Short name T929
Test name
Test status
Simulation time 14281496727 ps
CPU time 72.81 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:19:03 PM PDT 24
Peak memory 232004 kb
Host smart-ea5bc220-cb3e-4afd-98ed-f4cb0e265212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008198325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4008198325
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1198038269
Short name T367
Test name
Test status
Simulation time 457531159 ps
CPU time 4.28 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:17:54 PM PDT 24
Peak memory 225196 kb
Host smart-5c1d37d2-218c-4666-9fa1-a531328b15c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198038269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1198038269
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1474874068
Short name T179
Test name
Test status
Simulation time 31346611261 ps
CPU time 81.58 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:19:11 PM PDT 24
Peak memory 249872 kb
Host smart-99aa171b-b311-40f0-bdc3-7fd97be82640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474874068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1474874068
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2330126413
Short name T678
Test name
Test status
Simulation time 187733876 ps
CPU time 4.59 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:38 PM PDT 24
Peak memory 233392 kb
Host smart-e3b13947-4354-4fd5-9760-aff5cced2ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330126413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2330126413
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1481707086
Short name T625
Test name
Test status
Simulation time 5790637071 ps
CPU time 19.9 seconds
Started Aug 01 05:17:37 PM PDT 24
Finished Aug 01 05:17:57 PM PDT 24
Peak memory 225276 kb
Host smart-d39ce4ee-f9ed-4bf5-b6a7-0b16027f7e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481707086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1481707086
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3937264446
Short name T804
Test name
Test status
Simulation time 309654585 ps
CPU time 2.83 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:38 PM PDT 24
Peak memory 233468 kb
Host smart-7971a3c9-a75d-447f-a7b5-150f3954a420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937264446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3937264446
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1023694770
Short name T964
Test name
Test status
Simulation time 791060647 ps
CPU time 8.47 seconds
Started Aug 01 05:17:35 PM PDT 24
Finished Aug 01 05:17:44 PM PDT 24
Peak memory 233316 kb
Host smart-ef04daf3-a5de-494e-8f67-0e4c61894d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023694770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1023694770
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1184564551
Short name T842
Test name
Test status
Simulation time 3726405029 ps
CPU time 11.69 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:18:01 PM PDT 24
Peak memory 220044 kb
Host smart-3465fd59-f2d8-47f5-8013-24f71b78477c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1184564551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1184564551
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.843817603
Short name T1008
Test name
Test status
Simulation time 5811420822 ps
CPU time 115.48 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 264168 kb
Host smart-e3e22706-beb2-4cc9-afc9-4d084b460fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843817603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.843817603
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3617716553
Short name T836
Test name
Test status
Simulation time 1206810880 ps
CPU time 10.85 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:45 PM PDT 24
Peak memory 216904 kb
Host smart-6621cea8-e2b6-42f5-88ab-835f01c55343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617716553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3617716553
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1257028243
Short name T957
Test name
Test status
Simulation time 9065339085 ps
CPU time 5.8 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:40 PM PDT 24
Peak memory 217004 kb
Host smart-dd97729c-3210-4c44-9ada-9a1c14bdf2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257028243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1257028243
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.831537428
Short name T351
Test name
Test status
Simulation time 73888946 ps
CPU time 1.22 seconds
Started Aug 01 05:17:32 PM PDT 24
Finished Aug 01 05:17:33 PM PDT 24
Peak memory 208696 kb
Host smart-2f8cf7ac-dab1-479c-96a2-ac00fa31225c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831537428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.831537428
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3449671144
Short name T573
Test name
Test status
Simulation time 182169633 ps
CPU time 0.81 seconds
Started Aug 01 05:17:36 PM PDT 24
Finished Aug 01 05:17:37 PM PDT 24
Peak memory 206572 kb
Host smart-31c128de-6522-4559-9ffa-6a72ee648834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449671144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3449671144
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.224115473
Short name T183
Test name
Test status
Simulation time 13438628035 ps
CPU time 15.8 seconds
Started Aug 01 05:17:34 PM PDT 24
Finished Aug 01 05:17:50 PM PDT 24
Peak memory 249892 kb
Host smart-310d9752-7752-4a15-b0ef-6e3d7b913819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224115473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.224115473
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1301033605
Short name T698
Test name
Test status
Simulation time 18689197 ps
CPU time 0.7 seconds
Started Aug 01 05:17:54 PM PDT 24
Finished Aug 01 05:17:55 PM PDT 24
Peak memory 205184 kb
Host smart-ef46d30f-c9ed-4633-bc67-d18e2566ee66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301033605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1301033605
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1034613640
Short name T578
Test name
Test status
Simulation time 323482326 ps
CPU time 4.24 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:17:54 PM PDT 24
Peak memory 233368 kb
Host smart-0db11680-7f15-432a-9cef-4966d1e73136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034613640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1034613640
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3346384551
Short name T811
Test name
Test status
Simulation time 39898222 ps
CPU time 0.77 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:17:53 PM PDT 24
Peak memory 206996 kb
Host smart-c658ab57-0529-4d56-ad09-4263748a4357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346384551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3346384551
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1793403720
Short name T230
Test name
Test status
Simulation time 19698636921 ps
CPU time 70.05 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:18:59 PM PDT 24
Peak memory 255832 kb
Host smart-c9b9097c-b34f-4a82-8d18-7806275bcaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793403720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1793403720
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1076278127
Short name T39
Test name
Test status
Simulation time 91879296016 ps
CPU time 96.93 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:19:28 PM PDT 24
Peak memory 258036 kb
Host smart-e94d31a3-ca64-4151-9157-7603632e071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076278127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1076278127
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.16464149
Short name T993
Test name
Test status
Simulation time 13946068500 ps
CPU time 120.45 seconds
Started Aug 01 05:17:55 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 249852 kb
Host smart-db0ccc90-97ce-4e05-aa3f-8a1361a2a040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16464149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.16464149
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2863408273
Short name T94
Test name
Test status
Simulation time 83604347 ps
CPU time 4.63 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:17:56 PM PDT 24
Peak memory 225228 kb
Host smart-6837ccbe-7914-4a1a-81b2-2508b6c456c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863408273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2863408273
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2726075550
Short name T593
Test name
Test status
Simulation time 37805739992 ps
CPU time 74.73 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:19:06 PM PDT 24
Peak memory 252728 kb
Host smart-7f043e55-876d-4ab3-9d5d-5b1368274028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726075550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2726075550
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.502008894
Short name T256
Test name
Test status
Simulation time 819400937 ps
CPU time 10.23 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:18:00 PM PDT 24
Peak memory 233392 kb
Host smart-36bc177e-ca8d-48a6-abab-07cb97d2249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502008894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.502008894
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1380240332
Short name T542
Test name
Test status
Simulation time 13808918145 ps
CPU time 139.45 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 241704 kb
Host smart-fb440895-d9bf-4fb4-a9b1-93792ef23d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380240332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1380240332
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1595119577
Short name T806
Test name
Test status
Simulation time 1930385878 ps
CPU time 8.19 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:17:57 PM PDT 24
Peak memory 225180 kb
Host smart-28d79935-9315-4a16-b80c-e281bab9db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595119577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1595119577
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1764688950
Short name T849
Test name
Test status
Simulation time 331620619 ps
CPU time 3.79 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:17:53 PM PDT 24
Peak memory 225280 kb
Host smart-99a77d34-8d5f-4a33-a9bb-6fbaf9627cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764688950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1764688950
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1630474218
Short name T3
Test name
Test status
Simulation time 947099856 ps
CPU time 9.03 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:18:00 PM PDT 24
Peak memory 220708 kb
Host smart-542d45f9-bd7a-4d80-abe0-c911977e6d8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1630474218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1630474218
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3290250969
Short name T30
Test name
Test status
Simulation time 321480602 ps
CPU time 1 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:17:51 PM PDT 24
Peak memory 207376 kb
Host smart-f6242124-aed8-4f33-b1bd-bcb493654138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290250969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3290250969
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.534504249
Short name T958
Test name
Test status
Simulation time 1709511788 ps
CPU time 12.2 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:18:03 PM PDT 24
Peak memory 216944 kb
Host smart-7dbbfbfc-1e89-4a05-9cfd-7d14fe8ef66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534504249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.534504249
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1290984099
Short name T71
Test name
Test status
Simulation time 106748492 ps
CPU time 1.57 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:17:51 PM PDT 24
Peak memory 208416 kb
Host smart-ee2aced0-4e5c-4f7b-a7f1-42604ff24f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290984099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1290984099
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2535245644
Short name T12
Test name
Test status
Simulation time 49569143 ps
CPU time 1.31 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:17:50 PM PDT 24
Peak memory 208496 kb
Host smart-b4cf1338-926b-4e46-9725-400190dcfad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535245644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2535245644
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3161231409
Short name T742
Test name
Test status
Simulation time 31536445 ps
CPU time 0.83 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:17:52 PM PDT 24
Peak memory 206508 kb
Host smart-f3e7c5cd-5627-4df6-9853-fa91872d3a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161231409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3161231409
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.362820932
Short name T597
Test name
Test status
Simulation time 10358726683 ps
CPU time 10.91 seconds
Started Aug 01 05:17:48 PM PDT 24
Finished Aug 01 05:17:59 PM PDT 24
Peak memory 241616 kb
Host smart-7fc743df-e0d9-4d1a-8b10-ea3ef807cf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362820932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.362820932
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4270935586
Short name T8
Test name
Test status
Simulation time 23728226 ps
CPU time 0.68 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:15:59 PM PDT 24
Peak memory 205800 kb
Host smart-ab4e0aa4-3ac9-46a9-94d5-1e3df4cb822e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270935586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
270935586
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2451876222
Short name T519
Test name
Test status
Simulation time 1043493699 ps
CPU time 3.1 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 233336 kb
Host smart-fd1e2c89-814c-4b36-bc7f-94f5f47d46c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451876222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2451876222
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3117409974
Short name T59
Test name
Test status
Simulation time 57822577 ps
CPU time 0.78 seconds
Started Aug 01 05:15:40 PM PDT 24
Finished Aug 01 05:15:41 PM PDT 24
Peak memory 206964 kb
Host smart-2f04a08f-773e-4a1b-a384-a08b43a44014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117409974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3117409974
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1170597963
Short name T893
Test name
Test status
Simulation time 48881707143 ps
CPU time 152.47 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:18:16 PM PDT 24
Peak memory 237936 kb
Host smart-07e9041f-7fd7-48d9-af20-febba8a01f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170597963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1170597963
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3240572931
Short name T201
Test name
Test status
Simulation time 17856710245 ps
CPU time 67.85 seconds
Started Aug 01 05:15:44 PM PDT 24
Finished Aug 01 05:16:52 PM PDT 24
Peak memory 249900 kb
Host smart-ef81ab8d-5431-4c97-8ae3-c76e228b0fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240572931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3240572931
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.484394467
Short name T951
Test name
Test status
Simulation time 13965776700 ps
CPU time 33.18 seconds
Started Aug 01 05:15:46 PM PDT 24
Finished Aug 01 05:16:19 PM PDT 24
Peak memory 225304 kb
Host smart-28a60d5d-af67-43bf-8d1d-7f4414e7e8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484394467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
484394467
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2713395669
Short name T391
Test name
Test status
Simulation time 43000919 ps
CPU time 2.67 seconds
Started Aug 01 05:15:45 PM PDT 24
Finished Aug 01 05:15:48 PM PDT 24
Peak memory 233372 kb
Host smart-29fc485e-6440-4c4a-8b7a-fe4ced999596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713395669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2713395669
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3143244344
Short name T570
Test name
Test status
Simulation time 3743536477 ps
CPU time 19.81 seconds
Started Aug 01 05:15:45 PM PDT 24
Finished Aug 01 05:16:05 PM PDT 24
Peak memory 250252 kb
Host smart-e48e1480-45b3-431b-8a56-ffc9821cb240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143244344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3143244344
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.273800465
Short name T404
Test name
Test status
Simulation time 59639460 ps
CPU time 2.61 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 227220 kb
Host smart-2ed7d9f4-ea64-4465-a17c-681d6f02a56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273800465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.273800465
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3446299151
Short name T890
Test name
Test status
Simulation time 864906619 ps
CPU time 16.97 seconds
Started Aug 01 05:15:44 PM PDT 24
Finished Aug 01 05:16:01 PM PDT 24
Peak memory 250328 kb
Host smart-db3c5376-a0cc-4bdd-8f5d-e629f4549eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446299151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3446299151
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2567126407
Short name T630
Test name
Test status
Simulation time 37914237 ps
CPU time 1.14 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:44 PM PDT 24
Peak memory 217088 kb
Host smart-54394b23-6d7d-44ab-8f13-4252ab3b5238
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567126407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2567126407
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3670002828
Short name T25
Test name
Test status
Simulation time 2402967138 ps
CPU time 8.03 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:51 PM PDT 24
Peak memory 233488 kb
Host smart-514bf578-62cf-4e6b-ab10-8c7807b13a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670002828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3670002828
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2094741185
Short name T523
Test name
Test status
Simulation time 8028360173 ps
CPU time 5.13 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:49 PM PDT 24
Peak memory 233416 kb
Host smart-f91c6838-e96a-4a76-85e0-88079777b132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094741185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2094741185
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3500031132
Short name T978
Test name
Test status
Simulation time 383597935 ps
CPU time 3.36 seconds
Started Aug 01 05:15:46 PM PDT 24
Finished Aug 01 05:15:50 PM PDT 24
Peak memory 220064 kb
Host smart-6011821d-7ce7-4883-aff6-8176ff3659dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3500031132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3500031132
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2617749445
Short name T66
Test name
Test status
Simulation time 50822934 ps
CPU time 1 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:15:57 PM PDT 24
Peak memory 235468 kb
Host smart-245418d7-25e3-42f1-82aa-0d347c26dc7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617749445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2617749445
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.671065787
Short name T281
Test name
Test status
Simulation time 18404240529 ps
CPU time 216.03 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:19:36 PM PDT 24
Peak memory 257464 kb
Host smart-060bc1e1-9dde-4f8e-9380-1b72ff82d3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671065787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.671065787
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2730108438
Short name T491
Test name
Test status
Simulation time 15153391164 ps
CPU time 16.96 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:17 PM PDT 24
Peak memory 216904 kb
Host smart-bb169a32-7362-41eb-b44c-608ac00c8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730108438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2730108438
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.215195677
Short name T912
Test name
Test status
Simulation time 589441067 ps
CPU time 2.15 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 216848 kb
Host smart-1ca7ff9b-fee9-43ac-a0c5-082e9932b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215195677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.215195677
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1345548447
Short name T547
Test name
Test status
Simulation time 285428334 ps
CPU time 2.72 seconds
Started Aug 01 05:15:43 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 216848 kb
Host smart-adc48ece-0ed1-4cfe-a965-404559046465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345548447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1345548447
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.126310808
Short name T719
Test name
Test status
Simulation time 140316494 ps
CPU time 0.85 seconds
Started Aug 01 05:15:42 PM PDT 24
Finished Aug 01 05:15:43 PM PDT 24
Peak memory 206464 kb
Host smart-21f7fd68-7df9-46ef-b227-68d2cd57047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126310808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.126310808
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1157936170
Short name T667
Test name
Test status
Simulation time 3460893907 ps
CPU time 12.06 seconds
Started Aug 01 05:15:46 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 225228 kb
Host smart-4f9db405-9ea0-4671-9d1b-0963be6664aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157936170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1157936170
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2453793407
Short name T799
Test name
Test status
Simulation time 12955044 ps
CPU time 0.72 seconds
Started Aug 01 05:17:55 PM PDT 24
Finished Aug 01 05:17:56 PM PDT 24
Peak memory 205856 kb
Host smart-1d4d0486-c852-4bf9-8094-0913e192d144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453793407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2453793407
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1711237242
Short name T852
Test name
Test status
Simulation time 67712170 ps
CPU time 2.65 seconds
Started Aug 01 05:17:52 PM PDT 24
Finished Aug 01 05:17:55 PM PDT 24
Peak memory 233532 kb
Host smart-c165f53b-e7a5-427d-8310-1c415154e67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711237242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1711237242
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2376662297
Short name T899
Test name
Test status
Simulation time 18355757 ps
CPU time 0.79 seconds
Started Aug 01 05:17:55 PM PDT 24
Finished Aug 01 05:17:56 PM PDT 24
Peak memory 207252 kb
Host smart-dd076c17-2731-47ae-9e72-de62e9380b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376662297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2376662297
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1350749208
Short name T229
Test name
Test status
Simulation time 1976698793 ps
CPU time 27.95 seconds
Started Aug 01 05:17:53 PM PDT 24
Finished Aug 01 05:18:21 PM PDT 24
Peak memory 241688 kb
Host smart-7487edfe-518c-415b-bf9b-e686fa1c5fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350749208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1350749208
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1236405352
Short name T655
Test name
Test status
Simulation time 8653075630 ps
CPU time 73.96 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:19:06 PM PDT 24
Peak memory 249160 kb
Host smart-9e32eb42-9307-4429-85bc-d979861f838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236405352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1236405352
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1240195602
Short name T186
Test name
Test status
Simulation time 10700163990 ps
CPU time 118.9 seconds
Started Aug 01 05:17:53 PM PDT 24
Finished Aug 01 05:19:52 PM PDT 24
Peak memory 257704 kb
Host smart-629bd106-f1d0-4828-8941-7dfb2890d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240195602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1240195602
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1146783743
Short name T632
Test name
Test status
Simulation time 1309231231 ps
CPU time 4.99 seconds
Started Aug 01 05:17:52 PM PDT 24
Finished Aug 01 05:17:58 PM PDT 24
Peak memory 233440 kb
Host smart-6d262fba-2d1d-4e6c-8eb5-9589c8ec1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146783743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1146783743
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3080042373
Short name T380
Test name
Test status
Simulation time 1178678890 ps
CPU time 11.99 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:18:03 PM PDT 24
Peak memory 225156 kb
Host smart-213e03f0-5ee4-4863-91d4-c99e8fcb1c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080042373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3080042373
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1651206735
Short name T223
Test name
Test status
Simulation time 1942104964 ps
CPU time 19.05 seconds
Started Aug 01 05:17:53 PM PDT 24
Finished Aug 01 05:18:12 PM PDT 24
Peak memory 225292 kb
Host smart-cde65dcb-f202-443b-b078-ff29479e0b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651206735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1651206735
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3236409344
Short name T1001
Test name
Test status
Simulation time 601610873 ps
CPU time 2.36 seconds
Started Aug 01 05:17:49 PM PDT 24
Finished Aug 01 05:17:52 PM PDT 24
Peak memory 225056 kb
Host smart-01bb4300-3479-462d-8004-e3ed0b79a075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236409344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3236409344
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2751496463
Short name T540
Test name
Test status
Simulation time 5637277368 ps
CPU time 9.06 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:18:00 PM PDT 24
Peak memory 240276 kb
Host smart-29d94605-29dd-4a0f-9cb9-deb1c9c6231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751496463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2751496463
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3174598027
Short name T809
Test name
Test status
Simulation time 126304257 ps
CPU time 4.11 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:17:56 PM PDT 24
Peak memory 223156 kb
Host smart-94470871-f319-4717-8d6c-da09145b4f41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3174598027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3174598027
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2066621802
Short name T383
Test name
Test status
Simulation time 129850239 ps
CPU time 1.9 seconds
Started Aug 01 05:17:50 PM PDT 24
Finished Aug 01 05:17:52 PM PDT 24
Peak memory 216912 kb
Host smart-834082cf-7d75-4477-974a-5a6d7e162eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066621802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2066621802
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2804808786
Short name T805
Test name
Test status
Simulation time 543186009 ps
CPU time 2.95 seconds
Started Aug 01 05:17:54 PM PDT 24
Finished Aug 01 05:17:57 PM PDT 24
Peak memory 216892 kb
Host smart-34a45323-c6e1-475c-9d42-3e91b1413bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804808786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2804808786
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.426248607
Short name T28
Test name
Test status
Simulation time 132337941 ps
CPU time 2.06 seconds
Started Aug 01 05:17:55 PM PDT 24
Finished Aug 01 05:17:57 PM PDT 24
Peak memory 216816 kb
Host smart-7c5a3504-4eee-4a78-b158-1f4decd642c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426248607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.426248607
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.365345991
Short name T525
Test name
Test status
Simulation time 507070715 ps
CPU time 0.99 seconds
Started Aug 01 05:17:52 PM PDT 24
Finished Aug 01 05:17:54 PM PDT 24
Peak memory 207644 kb
Host smart-f9d64d73-980a-4606-ace1-ba98feedd60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365345991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.365345991
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2641988397
Short name T997
Test name
Test status
Simulation time 4184844931 ps
CPU time 15.27 seconds
Started Aug 01 05:17:52 PM PDT 24
Finished Aug 01 05:18:07 PM PDT 24
Peak memory 225292 kb
Host smart-dc7ae4ae-f32a-4751-85de-01d79ae06d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641988397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2641988397
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2404685833
Short name T475
Test name
Test status
Simulation time 81511157 ps
CPU time 0.7 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:03 PM PDT 24
Peak memory 205720 kb
Host smart-f927ebe6-5b71-4577-8ef7-50170221d343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404685833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2404685833
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3709272837
Short name T436
Test name
Test status
Simulation time 44163355 ps
CPU time 2.66 seconds
Started Aug 01 05:18:01 PM PDT 24
Finished Aug 01 05:18:03 PM PDT 24
Peak memory 233320 kb
Host smart-9aaa84d0-368a-42bb-967d-ac4b21e6adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709272837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3709272837
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.632108864
Short name T334
Test name
Test status
Simulation time 75716771 ps
CPU time 0.81 seconds
Started Aug 01 05:17:53 PM PDT 24
Finished Aug 01 05:17:54 PM PDT 24
Peak memory 207076 kb
Host smart-09ea88bc-4872-4f3c-a241-c3cb4558266e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632108864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.632108864
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.464804944
Short name T44
Test name
Test status
Simulation time 21070669355 ps
CPU time 153.44 seconds
Started Aug 01 05:18:00 PM PDT 24
Finished Aug 01 05:20:33 PM PDT 24
Peak memory 249920 kb
Host smart-1dabd453-07e5-488c-8e3c-f2191b05beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464804944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.464804944
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2049780012
Short name T908
Test name
Test status
Simulation time 82013450665 ps
CPU time 161.66 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 249640 kb
Host smart-0a2ca1c7-d362-4cdd-8b9d-b33daca15fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049780012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2049780012
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2483302060
Short name T1026
Test name
Test status
Simulation time 7055123166 ps
CPU time 100.06 seconds
Started Aug 01 05:18:04 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 267052 kb
Host smart-23228bfb-2143-4985-a745-e227e1e98d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483302060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2483302060
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2564012603
Short name T734
Test name
Test status
Simulation time 87794758 ps
CPU time 4.52 seconds
Started Aug 01 05:18:20 PM PDT 24
Finished Aug 01 05:18:25 PM PDT 24
Peak memory 225192 kb
Host smart-c43a4a50-cfff-4f87-bd66-05d5a7d84782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564012603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2564012603
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.847033298
Short name T584
Test name
Test status
Simulation time 14147866446 ps
CPU time 76.1 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:19:18 PM PDT 24
Peak memory 249804 kb
Host smart-040817eb-0e8b-40a3-a9aa-3a72323d79a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847033298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.847033298
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.418266266
Short name T473
Test name
Test status
Simulation time 124106441 ps
CPU time 2.33 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:18:12 PM PDT 24
Peak memory 233436 kb
Host smart-c4847f22-2dd5-4334-a7d1-cb354b8cc785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418266266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.418266266
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2921142528
Short name T134
Test name
Test status
Simulation time 1009978366 ps
CPU time 8.48 seconds
Started Aug 01 05:18:00 PM PDT 24
Finished Aug 01 05:18:09 PM PDT 24
Peak memory 225112 kb
Host smart-ffbfc482-20e6-4fb9-8c7c-a5ce64ceb1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921142528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2921142528
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2325873025
Short name T603
Test name
Test status
Simulation time 8289664344 ps
CPU time 25.7 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:28 PM PDT 24
Peak memory 233404 kb
Host smart-8babc763-8b01-4448-b930-5343aa757f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325873025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2325873025
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3729098003
Short name T629
Test name
Test status
Simulation time 112694057 ps
CPU time 2.24 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:07 PM PDT 24
Peak memory 224940 kb
Host smart-2209e26d-d7f5-46f0-b124-456034bc8606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729098003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3729098003
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4209037252
Short name T445
Test name
Test status
Simulation time 923767887 ps
CPU time 11.47 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:18:21 PM PDT 24
Peak memory 219780 kb
Host smart-e523e5f1-955b-4d2e-8faf-5929a22ab5d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209037252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4209037252
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.763407516
Short name T894
Test name
Test status
Simulation time 8807721896 ps
CPU time 95.13 seconds
Started Aug 01 05:18:03 PM PDT 24
Finished Aug 01 05:19:39 PM PDT 24
Peak memory 255404 kb
Host smart-d7e90a91-6894-40d6-a1b5-8899a03e21cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763407516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.763407516
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3591539859
Short name T777
Test name
Test status
Simulation time 5085093035 ps
CPU time 21.56 seconds
Started Aug 01 05:17:51 PM PDT 24
Finished Aug 01 05:18:12 PM PDT 24
Peak memory 217396 kb
Host smart-18274eaa-ab85-4e64-8c44-3ed4e52d8292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591539859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3591539859
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.173154
Short name T930
Test name
Test status
Simulation time 15821539544 ps
CPU time 9.99 seconds
Started Aug 01 05:17:52 PM PDT 24
Finished Aug 01 05:18:03 PM PDT 24
Peak memory 216956 kb
Host smart-f302f060-d179-4750-8821-9023ef92a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.173154
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3075349505
Short name T700
Test name
Test status
Simulation time 137610398 ps
CPU time 1.03 seconds
Started Aug 01 05:18:12 PM PDT 24
Finished Aug 01 05:18:13 PM PDT 24
Peak memory 208692 kb
Host smart-e5ce1f39-2565-42fa-bb03-b85475b723f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075349505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3075349505
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.545315735
Short name T84
Test name
Test status
Simulation time 26962467 ps
CPU time 0.74 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:18:09 PM PDT 24
Peak memory 206556 kb
Host smart-90510907-f0d6-4dcb-a01f-3a6541495435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545315735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.545315735
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3846070117
Short name T883
Test name
Test status
Simulation time 2860946628 ps
CPU time 5.75 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:08 PM PDT 24
Peak memory 233528 kb
Host smart-00f2f37c-54af-4a69-9e1e-80ec86cde03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846070117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3846070117
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.61926361
Short name T906
Test name
Test status
Simulation time 60603839 ps
CPU time 0.74 seconds
Started Aug 01 05:18:03 PM PDT 24
Finished Aug 01 05:18:04 PM PDT 24
Peak memory 205764 kb
Host smart-12c8743f-9da8-47d3-b2e3-6202e90f0123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61926361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.61926361
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1645592146
Short name T545
Test name
Test status
Simulation time 192186355 ps
CPU time 3.15 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:09 PM PDT 24
Peak memory 233420 kb
Host smart-d6be8b16-b0a5-414f-a2fd-99735f6668fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645592146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1645592146
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3965633108
Short name T340
Test name
Test status
Simulation time 14179641 ps
CPU time 0.77 seconds
Started Aug 01 05:18:06 PM PDT 24
Finished Aug 01 05:18:07 PM PDT 24
Peak memory 206960 kb
Host smart-c30742b6-e43e-499a-a5ea-8d183c690918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965633108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3965633108
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1513429874
Short name T236
Test name
Test status
Simulation time 30502233370 ps
CPU time 227.65 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:21:56 PM PDT 24
Peak memory 253732 kb
Host smart-f9ccde6a-eb78-4453-ab0d-a886fdabb018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513429874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1513429874
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.484525179
Short name T325
Test name
Test status
Simulation time 68561182506 ps
CPU time 322.45 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:23:31 PM PDT 24
Peak memory 266348 kb
Host smart-2d6eace4-82ae-447f-941f-79a4ecd6693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484525179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.484525179
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3942815006
Short name T674
Test name
Test status
Simulation time 1892929656 ps
CPU time 29.13 seconds
Started Aug 01 05:18:06 PM PDT 24
Finished Aug 01 05:18:35 PM PDT 24
Peak memory 218228 kb
Host smart-f05f3559-e667-4296-a28f-c660b51fb83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942815006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3942815006
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4156992961
Short name T544
Test name
Test status
Simulation time 2358126776 ps
CPU time 10.82 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:13 PM PDT 24
Peak memory 233612 kb
Host smart-4c0dd390-0a95-4311-ab78-09a04a1d1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156992961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4156992961
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3670601389
Short name T659
Test name
Test status
Simulation time 43257095837 ps
CPU time 103.96 seconds
Started Aug 01 05:18:06 PM PDT 24
Finished Aug 01 05:19:50 PM PDT 24
Peak memory 252428 kb
Host smart-f5cc01d1-1e83-47fc-b41b-215bc485671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670601389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3670601389
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2877621014
Short name T664
Test name
Test status
Simulation time 10785972788 ps
CPU time 25.61 seconds
Started Aug 01 05:18:01 PM PDT 24
Finished Aug 01 05:18:27 PM PDT 24
Peak memory 230868 kb
Host smart-376d94d1-38f8-416e-91d4-897b321a9ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877621014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2877621014
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.216563987
Short name T471
Test name
Test status
Simulation time 23281433958 ps
CPU time 109.37 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:19:58 PM PDT 24
Peak memory 225140 kb
Host smart-935aee9e-0e4b-4af1-9cdd-8dd29cb70600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216563987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.216563987
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.762984478
Short name T758
Test name
Test status
Simulation time 1651315978 ps
CPU time 9.73 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:18:19 PM PDT 24
Peak memory 233328 kb
Host smart-39469f2d-75ce-47d3-9779-ede7d6888f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762984478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.762984478
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.994814276
Short name T785
Test name
Test status
Simulation time 3922400089 ps
CPU time 4.92 seconds
Started Aug 01 05:18:01 PM PDT 24
Finished Aug 01 05:18:06 PM PDT 24
Peak memory 233484 kb
Host smart-efe11614-86fd-4d60-88c4-8c90fd1c426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994814276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.994814276
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2583965196
Short name T549
Test name
Test status
Simulation time 1868618270 ps
CPU time 7.88 seconds
Started Aug 01 05:18:03 PM PDT 24
Finished Aug 01 05:18:11 PM PDT 24
Peak memory 223596 kb
Host smart-3a73ed55-e13a-4555-9372-462bdfb03122
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2583965196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2583965196
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.281631407
Short name T375
Test name
Test status
Simulation time 167389533 ps
CPU time 0.99 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:03 PM PDT 24
Peak memory 208032 kb
Host smart-6a2b96a8-21d3-46ff-a83d-fbffa0121715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281631407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.281631407
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.254882382
Short name T86
Test name
Test status
Simulation time 1774499509 ps
CPU time 3.49 seconds
Started Aug 01 05:18:03 PM PDT 24
Finished Aug 01 05:18:06 PM PDT 24
Peak memory 216884 kb
Host smart-a8493c0b-9a12-4f5f-8ca6-44de1a2b4712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254882382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.254882382
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2289700358
Short name T338
Test name
Test status
Simulation time 19542083835 ps
CPU time 14.79 seconds
Started Aug 01 05:18:07 PM PDT 24
Finished Aug 01 05:18:22 PM PDT 24
Peak memory 217064 kb
Host smart-98f9f725-77ee-4693-897c-2571279b20e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289700358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2289700358
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.494613677
Short name T720
Test name
Test status
Simulation time 99577636 ps
CPU time 4.31 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:10 PM PDT 24
Peak memory 216844 kb
Host smart-c754ca68-c8fd-46d1-a999-95814df0a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494613677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.494613677
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.617247508
Short name T345
Test name
Test status
Simulation time 72126554 ps
CPU time 0.93 seconds
Started Aug 01 05:18:04 PM PDT 24
Finished Aug 01 05:18:05 PM PDT 24
Peak memory 207500 kb
Host smart-4a02efc8-fd77-4616-8415-8d31a7a110b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617247508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.617247508
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.587012379
Short name T861
Test name
Test status
Simulation time 32011298247 ps
CPU time 20.05 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:18:28 PM PDT 24
Peak memory 240336 kb
Host smart-05b7c6d5-d407-4d4c-999b-517b3ed48b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587012379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.587012379
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.269579740
Short name T415
Test name
Test status
Simulation time 61510644 ps
CPU time 0.73 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:18:09 PM PDT 24
Peak memory 205196 kb
Host smart-34f15485-e6e9-4230-b136-f417fd1036b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269579740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.269579740
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3384863608
Short name T257
Test name
Test status
Simulation time 774657019 ps
CPU time 3.99 seconds
Started Aug 01 05:18:06 PM PDT 24
Finished Aug 01 05:18:10 PM PDT 24
Peak memory 225164 kb
Host smart-e2c558bd-cd60-4761-ab80-43fb12c4f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384863608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3384863608
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2830160643
Short name T621
Test name
Test status
Simulation time 16565439 ps
CPU time 0.78 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:18:10 PM PDT 24
Peak memory 207052 kb
Host smart-fa83bb5b-cb83-430b-87e9-5f397e1eecfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830160643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2830160643
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3627468830
Short name T185
Test name
Test status
Simulation time 88457746370 ps
CPU time 161.41 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:20:46 PM PDT 24
Peak memory 250780 kb
Host smart-4931f3f1-c14d-4e46-9236-a2337b5da66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627468830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3627468830
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2395936219
Short name T891
Test name
Test status
Simulation time 5751168210 ps
CPU time 22.38 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:28 PM PDT 24
Peak memory 234780 kb
Host smart-9c67d745-9742-4971-b2be-c985c3fe7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395936219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2395936219
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3936095249
Short name T465
Test name
Test status
Simulation time 7788892149 ps
CPU time 29.18 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:35 PM PDT 24
Peak memory 218328 kb
Host smart-4014e70c-e1f7-45cc-a8d7-e21a2369117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936095249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3936095249
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.671361671
Short name T154
Test name
Test status
Simulation time 2037879027 ps
CPU time 30.91 seconds
Started Aug 01 05:18:04 PM PDT 24
Finished Aug 01 05:18:35 PM PDT 24
Peak memory 235380 kb
Host smart-b0b813d1-b661-4637-8306-34b15c68f0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671361671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.671361671
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2356755625
Short name T950
Test name
Test status
Simulation time 9382097160 ps
CPU time 31.65 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:33 PM PDT 24
Peak memory 249812 kb
Host smart-5372b4b9-b88c-478a-a550-3352b830ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356755625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2356755625
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3419124144
Short name T808
Test name
Test status
Simulation time 2126033193 ps
CPU time 8.53 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:10 PM PDT 24
Peak memory 233436 kb
Host smart-17610add-1b6f-4302-aba9-602d6a9e995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419124144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3419124144
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1559141325
Short name T106
Test name
Test status
Simulation time 1884243943 ps
CPU time 8.55 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:18:18 PM PDT 24
Peak memory 225080 kb
Host smart-085288a1-4e88-4ab1-a9e0-600a15347b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559141325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1559141325
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.650871404
Short name T860
Test name
Test status
Simulation time 3701310255 ps
CPU time 4.35 seconds
Started Aug 01 05:18:06 PM PDT 24
Finished Aug 01 05:18:11 PM PDT 24
Peak memory 225244 kb
Host smart-d1ea847a-2eea-4a13-a95b-e26dfa6822e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650871404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.650871404
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1939160327
Short name T669
Test name
Test status
Simulation time 601310779 ps
CPU time 5.04 seconds
Started Aug 01 05:18:04 PM PDT 24
Finished Aug 01 05:18:09 PM PDT 24
Peak memory 225124 kb
Host smart-59914356-81e9-49f3-9f7f-e5a089c60710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939160327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1939160327
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3461747688
Short name T361
Test name
Test status
Simulation time 3732392122 ps
CPU time 9.78 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:18:19 PM PDT 24
Peak memory 221264 kb
Host smart-e10650ca-ea56-415f-b03c-b024460d2233
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3461747688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3461747688
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2679365792
Short name T49
Test name
Test status
Simulation time 12668742370 ps
CPU time 84.62 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 266320 kb
Host smart-e667d1b4-d6d6-47ca-bd37-6feeffac51ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679365792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2679365792
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3713590958
Short name T87
Test name
Test status
Simulation time 1601638644 ps
CPU time 14.85 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:20 PM PDT 24
Peak memory 219684 kb
Host smart-bafd390c-4726-4e59-ac89-c17ba56fbb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713590958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3713590958
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1587829653
Short name T845
Test name
Test status
Simulation time 14092565532 ps
CPU time 9.43 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:14 PM PDT 24
Peak memory 217100 kb
Host smart-6da9a3f9-2016-48cc-9994-577fbcfa5bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587829653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1587829653
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3097669514
Short name T794
Test name
Test status
Simulation time 196690630 ps
CPU time 4.14 seconds
Started Aug 01 05:18:06 PM PDT 24
Finished Aug 01 05:18:10 PM PDT 24
Peak memory 216940 kb
Host smart-f5171936-faeb-496b-9b21-7e52136c1b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097669514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3097669514
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.417681769
Short name T701
Test name
Test status
Simulation time 47763242 ps
CPU time 0.78 seconds
Started Aug 01 05:18:06 PM PDT 24
Finished Aug 01 05:18:07 PM PDT 24
Peak memory 206640 kb
Host smart-44d2ae38-f972-435b-aa99-c0a884da6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417681769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.417681769
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.803972192
Short name T741
Test name
Test status
Simulation time 88220737 ps
CPU time 2.3 seconds
Started Aug 01 05:18:04 PM PDT 24
Finished Aug 01 05:18:06 PM PDT 24
Peak memory 224480 kb
Host smart-6272b76a-15c6-499a-b2e5-5d1e6ed7e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803972192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.803972192
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1026965838
Short name T346
Test name
Test status
Simulation time 14080066 ps
CPU time 0.75 seconds
Started Aug 01 05:18:24 PM PDT 24
Finished Aug 01 05:18:25 PM PDT 24
Peak memory 206076 kb
Host smart-a06e5beb-59e9-496a-abc8-1283496ac1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026965838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1026965838
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4043498042
Short name T999
Test name
Test status
Simulation time 932314589 ps
CPU time 13.01 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:18:21 PM PDT 24
Peak memory 225108 kb
Host smart-f4451287-d60b-422a-b133-aca48ea8277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043498042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4043498042
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3176096078
Short name T977
Test name
Test status
Simulation time 19078823 ps
CPU time 0.79 seconds
Started Aug 01 05:18:04 PM PDT 24
Finished Aug 01 05:18:05 PM PDT 24
Peak memory 206940 kb
Host smart-b7c981fa-933b-4b21-9d05-a8b39c3d49cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176096078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3176096078
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2266809033
Short name T199
Test name
Test status
Simulation time 9061198787 ps
CPU time 51.91 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:57 PM PDT 24
Peak memory 256660 kb
Host smart-aa64b7fc-28ca-4694-a350-88ba866ad557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266809033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2266809033
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3949665354
Short name T879
Test name
Test status
Simulation time 16716332104 ps
CPU time 99.68 seconds
Started Aug 01 05:18:12 PM PDT 24
Finished Aug 01 05:19:52 PM PDT 24
Peak memory 268552 kb
Host smart-15695774-70ec-41b3-99fe-6a807482b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949665354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3949665354
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2400038697
Short name T311
Test name
Test status
Simulation time 252481811 ps
CPU time 3.95 seconds
Started Aug 01 05:18:07 PM PDT 24
Finished Aug 01 05:18:12 PM PDT 24
Peak memory 233376 kb
Host smart-434caf2e-be6e-463a-a86d-17af1eea4d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400038697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2400038697
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3146056197
Short name T233
Test name
Test status
Simulation time 434068312 ps
CPU time 8.42 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:18:16 PM PDT 24
Peak memory 233396 kb
Host smart-6e47a6fc-81a6-43cb-b931-9a1e617416e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146056197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3146056197
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4130031162
Short name T626
Test name
Test status
Simulation time 59228627 ps
CPU time 2.47 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:05 PM PDT 24
Peak memory 232932 kb
Host smart-90d5b7ae-76e0-4f08-b82e-a0da99e87ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130031162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4130031162
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2381640450
Short name T728
Test name
Test status
Simulation time 246085067 ps
CPU time 3.83 seconds
Started Aug 01 05:18:09 PM PDT 24
Finished Aug 01 05:18:13 PM PDT 24
Peak memory 225144 kb
Host smart-ef0d7773-8ce4-4a12-9aae-dea9e55c41dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381640450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2381640450
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1530857342
Short name T197
Test name
Test status
Simulation time 8789299084 ps
CPU time 12.46 seconds
Started Aug 01 05:18:02 PM PDT 24
Finished Aug 01 05:18:15 PM PDT 24
Peak memory 239644 kb
Host smart-5b4d4cd5-bf14-41ed-af0b-7800f9f1eaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530857342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1530857342
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.465884784
Short name T478
Test name
Test status
Simulation time 334064460 ps
CPU time 3.77 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:09 PM PDT 24
Peak memory 223056 kb
Host smart-03004f02-ff5b-4f60-afb3-d8587e652224
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=465884784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.465884784
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1160062012
Short name T157
Test name
Test status
Simulation time 72620730 ps
CPU time 1.19 seconds
Started Aug 01 05:18:21 PM PDT 24
Finished Aug 01 05:18:22 PM PDT 24
Peak memory 208144 kb
Host smart-f6dad783-1c1b-4500-bbfc-31283b6862c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160062012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1160062012
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.336665672
Short name T635
Test name
Test status
Simulation time 2359287537 ps
CPU time 7.23 seconds
Started Aug 01 05:18:03 PM PDT 24
Finished Aug 01 05:18:11 PM PDT 24
Peak memory 217120 kb
Host smart-24346ffa-36ba-4b85-baec-63c214bd61ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336665672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.336665672
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1069542515
Short name T816
Test name
Test status
Simulation time 1164536517 ps
CPU time 6.67 seconds
Started Aug 01 05:18:05 PM PDT 24
Finished Aug 01 05:18:11 PM PDT 24
Peak memory 216840 kb
Host smart-8307dc3f-4297-473b-8599-ead4d7a86b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069542515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1069542515
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.563293564
Short name T526
Test name
Test status
Simulation time 94345789 ps
CPU time 0.82 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:18:09 PM PDT 24
Peak memory 207116 kb
Host smart-f97fbd59-2875-4f69-90a6-a4d451f1b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563293564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.563293564
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1344758284
Short name T617
Test name
Test status
Simulation time 29082673 ps
CPU time 0.87 seconds
Started Aug 01 05:18:04 PM PDT 24
Finished Aug 01 05:18:05 PM PDT 24
Peak memory 206476 kb
Host smart-f68e4bc3-5c81-4751-a259-06819b8f546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344758284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1344758284
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.591840240
Short name T227
Test name
Test status
Simulation time 132962625 ps
CPU time 3.04 seconds
Started Aug 01 05:18:08 PM PDT 24
Finished Aug 01 05:18:11 PM PDT 24
Peak memory 225132 kb
Host smart-b129eb0f-ca70-43d9-ac47-9a58f67206f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591840240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.591840240
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1207505699
Short name T834
Test name
Test status
Simulation time 11148444 ps
CPU time 0.69 seconds
Started Aug 01 05:18:16 PM PDT 24
Finished Aug 01 05:18:16 PM PDT 24
Peak memory 205956 kb
Host smart-e93925f3-ad5b-470d-a4b3-962b944bfa2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207505699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1207505699
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1122136204
Short name T92
Test name
Test status
Simulation time 62012733 ps
CPU time 2.86 seconds
Started Aug 01 05:18:23 PM PDT 24
Finished Aug 01 05:18:26 PM PDT 24
Peak memory 233444 kb
Host smart-3c74f83b-84f5-4e88-9fa4-235317f6cafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122136204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1122136204
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1134320177
Short name T989
Test name
Test status
Simulation time 33133238 ps
CPU time 0.82 seconds
Started Aug 01 05:18:15 PM PDT 24
Finished Aug 01 05:18:16 PM PDT 24
Peak memory 207044 kb
Host smart-e34a439d-425b-4337-8bab-594d21960325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134320177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1134320177
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.559889853
Short name T204
Test name
Test status
Simulation time 28457139276 ps
CPU time 219.19 seconds
Started Aug 01 05:18:23 PM PDT 24
Finished Aug 01 05:22:02 PM PDT 24
Peak memory 249864 kb
Host smart-1dbca880-9080-45db-8fef-06d24ce2e9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559889853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.559889853
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1471890620
Short name T575
Test name
Test status
Simulation time 27483716355 ps
CPU time 36.73 seconds
Started Aug 01 05:18:18 PM PDT 24
Finished Aug 01 05:18:55 PM PDT 24
Peak memory 218244 kb
Host smart-bbc5633f-5f93-4d95-9274-fde09ddb9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471890620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1471890620
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3173411741
Short name T4
Test name
Test status
Simulation time 4533473403 ps
CPU time 18.91 seconds
Started Aug 01 05:18:22 PM PDT 24
Finished Aug 01 05:18:41 PM PDT 24
Peak memory 218200 kb
Host smart-23880bbc-2984-44db-bb13-f8cd73dc749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173411741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3173411741
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2291880275
Short name T307
Test name
Test status
Simulation time 24172653264 ps
CPU time 27.59 seconds
Started Aug 01 05:18:15 PM PDT 24
Finished Aug 01 05:18:43 PM PDT 24
Peak memory 225236 kb
Host smart-4a1c79bf-5352-4832-9e8a-0bf24c33da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291880275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2291880275
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4176727013
Short name T279
Test name
Test status
Simulation time 92021887875 ps
CPU time 316.87 seconds
Started Aug 01 05:18:12 PM PDT 24
Finished Aug 01 05:23:29 PM PDT 24
Peak memory 249872 kb
Host smart-9de6a1cd-24f9-4d7a-acc9-8321f32396fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176727013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4176727013
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3807776839
Short name T612
Test name
Test status
Simulation time 4031411419 ps
CPU time 9.94 seconds
Started Aug 01 05:18:12 PM PDT 24
Finished Aug 01 05:18:22 PM PDT 24
Peak memory 233712 kb
Host smart-7ef46467-8588-4bcb-bc10-224e121a42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807776839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3807776839
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3827695625
Short name T363
Test name
Test status
Simulation time 104777442 ps
CPU time 2.4 seconds
Started Aug 01 05:18:22 PM PDT 24
Finished Aug 01 05:18:25 PM PDT 24
Peak memory 223476 kb
Host smart-fe82e67e-667e-4ad8-adb6-7c19a7eb238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827695625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3827695625
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1693931198
Short name T681
Test name
Test status
Simulation time 29573264 ps
CPU time 2.04 seconds
Started Aug 01 05:18:21 PM PDT 24
Finished Aug 01 05:18:23 PM PDT 24
Peak memory 225112 kb
Host smart-639d7975-0f36-4122-b1be-68458fe6a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693931198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1693931198
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4258377163
Short name T775
Test name
Test status
Simulation time 15066254574 ps
CPU time 23.15 seconds
Started Aug 01 05:18:22 PM PDT 24
Finished Aug 01 05:18:45 PM PDT 24
Peak memory 233464 kb
Host smart-0d2a169e-5f5a-41bc-9e19-89377ef3c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258377163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4258377163
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.921834192
Short name T829
Test name
Test status
Simulation time 1403484046 ps
CPU time 11.18 seconds
Started Aug 01 05:18:21 PM PDT 24
Finished Aug 01 05:18:32 PM PDT 24
Peak memory 220956 kb
Host smart-627aa3a6-bf6e-4fa2-9777-88f9e6f3a827
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=921834192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.921834192
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.540853441
Short name T778
Test name
Test status
Simulation time 51372155 ps
CPU time 1.08 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:27 PM PDT 24
Peak memory 208076 kb
Host smart-89016044-482b-4f21-b536-67dc8ff77114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540853441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.540853441
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2204360622
Short name T926
Test name
Test status
Simulation time 1923848127 ps
CPU time 26.18 seconds
Started Aug 01 05:18:20 PM PDT 24
Finished Aug 01 05:18:47 PM PDT 24
Peak memory 217108 kb
Host smart-9ba7b138-c699-49d2-909c-2c25fae5dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204360622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2204360622
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2842097975
Short name T1011
Test name
Test status
Simulation time 11693624 ps
CPU time 0.72 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:26 PM PDT 24
Peak memory 206124 kb
Host smart-2a8e653c-3b2f-487e-97fa-f7b2d69e1fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842097975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2842097975
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.586864938
Short name T43
Test name
Test status
Simulation time 614949959 ps
CPU time 1.24 seconds
Started Aug 01 05:18:21 PM PDT 24
Finished Aug 01 05:18:23 PM PDT 24
Peak memory 208736 kb
Host smart-d58512e1-b2e2-4c3d-9a32-c54e787e93f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586864938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.586864938
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.82141317
Short name T835
Test name
Test status
Simulation time 99148744 ps
CPU time 0.75 seconds
Started Aug 01 05:18:22 PM PDT 24
Finished Aug 01 05:18:22 PM PDT 24
Peak memory 206440 kb
Host smart-ee5e2992-a009-4126-bf62-acec0fe12992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82141317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.82141317
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2012510522
Short name T786
Test name
Test status
Simulation time 7045554681 ps
CPU time 6.3 seconds
Started Aug 01 05:18:24 PM PDT 24
Finished Aug 01 05:18:30 PM PDT 24
Peak memory 225216 kb
Host smart-b92ce1a8-a40d-4a0b-b90f-1ca04b3e04eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012510522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2012510522
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.887247028
Short name T356
Test name
Test status
Simulation time 12737702 ps
CPU time 0.71 seconds
Started Aug 01 05:18:20 PM PDT 24
Finished Aug 01 05:18:21 PM PDT 24
Peak memory 205188 kb
Host smart-d5f81465-08c1-4dff-bc2f-7653214ca828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887247028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.887247028
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1439008950
Short name T807
Test name
Test status
Simulation time 3173025538 ps
CPU time 4.21 seconds
Started Aug 01 05:18:17 PM PDT 24
Finished Aug 01 05:18:21 PM PDT 24
Peak memory 225232 kb
Host smart-08aacd95-866c-4d9a-83e9-3c9d4d4c6899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439008950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1439008950
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.138675954
Short name T892
Test name
Test status
Simulation time 59840781 ps
CPU time 0.79 seconds
Started Aug 01 05:18:20 PM PDT 24
Finished Aug 01 05:18:21 PM PDT 24
Peak memory 206956 kb
Host smart-ce262128-a859-42cd-8b3f-eaa12d847079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138675954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.138675954
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2301986889
Short name T222
Test name
Test status
Simulation time 45455650324 ps
CPU time 310.84 seconds
Started Aug 01 05:18:22 PM PDT 24
Finished Aug 01 05:23:33 PM PDT 24
Peak memory 262644 kb
Host smart-f0cfde5f-daf5-411c-b031-7606131d0dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301986889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2301986889
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2207542240
Short name T253
Test name
Test status
Simulation time 1932496296 ps
CPU time 39.92 seconds
Started Aug 01 05:18:14 PM PDT 24
Finished Aug 01 05:18:54 PM PDT 24
Peak memory 249828 kb
Host smart-533f0cb4-bf2f-4640-a0c7-c1546f4faa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207542240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2207542240
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2545541705
Short name T546
Test name
Test status
Simulation time 3716606911 ps
CPU time 61.58 seconds
Started Aug 01 05:18:21 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 238516 kb
Host smart-d6824cc5-d6c3-4778-bda2-e11be20c0d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545541705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2545541705
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3994124775
Short name T493
Test name
Test status
Simulation time 2420051674 ps
CPU time 11.42 seconds
Started Aug 01 05:18:13 PM PDT 24
Finished Aug 01 05:18:25 PM PDT 24
Peak memory 225184 kb
Host smart-a7dffa9f-00a8-4642-9ba1-f4fa0554342c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994124775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3994124775
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2021619573
Short name T96
Test name
Test status
Simulation time 104110716640 ps
CPU time 174.55 seconds
Started Aug 01 05:18:24 PM PDT 24
Finished Aug 01 05:21:19 PM PDT 24
Peak memory 252796 kb
Host smart-9e06f7f3-0c97-4cf1-9e53-6c420788a8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021619573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2021619573
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1990216315
Short name T721
Test name
Test status
Simulation time 687777442 ps
CPU time 6.96 seconds
Started Aug 01 05:18:15 PM PDT 24
Finished Aug 01 05:18:23 PM PDT 24
Peak memory 233416 kb
Host smart-e61a13ed-9251-4ee7-b418-3eedf06239cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990216315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1990216315
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.762694053
Short name T622
Test name
Test status
Simulation time 1129945243 ps
CPU time 7.1 seconds
Started Aug 01 05:18:20 PM PDT 24
Finished Aug 01 05:18:27 PM PDT 24
Peak memory 233372 kb
Host smart-40e66b70-ac84-4c1e-801b-b255402f0708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762694053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.762694053
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4126185793
Short name T272
Test name
Test status
Simulation time 121657889 ps
CPU time 2.32 seconds
Started Aug 01 05:18:12 PM PDT 24
Finished Aug 01 05:18:14 PM PDT 24
Peak memory 233444 kb
Host smart-efda7cee-5e1f-430a-bbec-cace4492405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126185793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4126185793
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2444600021
Short name T761
Test name
Test status
Simulation time 87477237 ps
CPU time 2.8 seconds
Started Aug 01 05:18:23 PM PDT 24
Finished Aug 01 05:18:26 PM PDT 24
Peak memory 233372 kb
Host smart-e1bb1322-0cf5-43d4-a979-decc0bde1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444600021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2444600021
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2194786985
Short name T384
Test name
Test status
Simulation time 944214382 ps
CPU time 4.52 seconds
Started Aug 01 05:18:22 PM PDT 24
Finished Aug 01 05:18:27 PM PDT 24
Peak memory 220508 kb
Host smart-a62319d2-30d7-47fb-9f55-024ff8480a58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2194786985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2194786985
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2467652194
Short name T322
Test name
Test status
Simulation time 129395182720 ps
CPU time 310.16 seconds
Started Aug 01 05:18:20 PM PDT 24
Finished Aug 01 05:23:30 PM PDT 24
Peak memory 253556 kb
Host smart-788c6e23-609a-4414-a671-bc7b8b8107ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467652194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2467652194
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1218598036
Short name T559
Test name
Test status
Simulation time 9323997091 ps
CPU time 8.57 seconds
Started Aug 01 05:18:24 PM PDT 24
Finished Aug 01 05:18:33 PM PDT 24
Peak memory 217032 kb
Host smart-548303f3-127c-4080-86dc-bc1aa96780ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218598036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1218598036
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3348336937
Short name T364
Test name
Test status
Simulation time 8161259333 ps
CPU time 25.2 seconds
Started Aug 01 05:18:18 PM PDT 24
Finished Aug 01 05:18:43 PM PDT 24
Peak memory 216908 kb
Host smart-0f34f0be-6de4-4304-9633-f8116f230e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348336937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3348336937
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2946963746
Short name T580
Test name
Test status
Simulation time 28828819 ps
CPU time 1.1 seconds
Started Aug 01 05:18:13 PM PDT 24
Finished Aug 01 05:18:14 PM PDT 24
Peak memory 208388 kb
Host smart-2db3f899-ac48-468d-96c8-5732eaf59825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946963746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2946963746
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3465657784
Short name T521
Test name
Test status
Simulation time 1430606409 ps
CPU time 0.9 seconds
Started Aug 01 05:18:14 PM PDT 24
Finished Aug 01 05:18:15 PM PDT 24
Peak memory 206556 kb
Host smart-f245d533-3adc-4bb7-ac63-15bc787ade97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465657784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3465657784
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2203642415
Short name T706
Test name
Test status
Simulation time 4734119796 ps
CPU time 10.85 seconds
Started Aug 01 05:18:13 PM PDT 24
Finished Aug 01 05:18:24 PM PDT 24
Peak memory 233596 kb
Host smart-e8ac4931-7104-404b-b1da-4dcdc89054d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203642415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2203642415
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2865398424
Short name T798
Test name
Test status
Simulation time 15224640 ps
CPU time 0.7 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:26 PM PDT 24
Peak memory 206120 kb
Host smart-5db6bc04-1237-497d-93a9-04fdd4fd139b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865398424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2865398424
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.717998115
Short name T588
Test name
Test status
Simulation time 1736868746 ps
CPU time 4.77 seconds
Started Aug 01 05:18:24 PM PDT 24
Finished Aug 01 05:18:29 PM PDT 24
Peak memory 225112 kb
Host smart-ca2ef712-eef5-403f-988a-598fac527730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717998115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.717998115
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2075943234
Short name T55
Test name
Test status
Simulation time 60966387 ps
CPU time 0.78 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:27 PM PDT 24
Peak memory 205896 kb
Host smart-cd276d73-2d55-49db-be9c-8cdeed9ab2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075943234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2075943234
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1699311521
Short name T722
Test name
Test status
Simulation time 40291807457 ps
CPU time 277.13 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:23:03 PM PDT 24
Peak memory 257872 kb
Host smart-25b02982-bb43-4882-a3b3-6f9c6e01a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699311521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1699311521
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2228537641
Short name T328
Test name
Test status
Simulation time 2937514244 ps
CPU time 13.92 seconds
Started Aug 01 05:18:34 PM PDT 24
Finished Aug 01 05:18:48 PM PDT 24
Peak memory 225260 kb
Host smart-9a169424-5ee1-4dce-bf10-60c783d2d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228537641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2228537641
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2689953640
Short name T300
Test name
Test status
Simulation time 21008552843 ps
CPU time 147.68 seconds
Started Aug 01 05:18:28 PM PDT 24
Finished Aug 01 05:20:55 PM PDT 24
Peak memory 266284 kb
Host smart-f58e37de-18cb-4cae-8a5f-f1866e00ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689953640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2689953640
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.484693516
Short name T587
Test name
Test status
Simulation time 1906162128 ps
CPU time 6.88 seconds
Started Aug 01 05:18:35 PM PDT 24
Finished Aug 01 05:18:42 PM PDT 24
Peak memory 225120 kb
Host smart-37e7797d-f450-448f-a38c-801f0f182227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484693516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.484693516
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2730625173
Short name T56
Test name
Test status
Simulation time 335400393 ps
CPU time 6.98 seconds
Started Aug 01 05:18:29 PM PDT 24
Finished Aug 01 05:18:36 PM PDT 24
Peak memory 224412 kb
Host smart-1b49bc35-ade9-427f-a5ea-710f14e3cf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730625173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2730625173
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4017796652
Short name T1019
Test name
Test status
Simulation time 172700804 ps
CPU time 3.74 seconds
Started Aug 01 05:18:33 PM PDT 24
Finished Aug 01 05:18:37 PM PDT 24
Peak memory 225176 kb
Host smart-f2b4f338-c322-4bb5-887c-f03bb37196cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017796652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4017796652
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3169437009
Short name T1013
Test name
Test status
Simulation time 11620707173 ps
CPU time 42.23 seconds
Started Aug 01 05:18:27 PM PDT 24
Finished Aug 01 05:19:10 PM PDT 24
Peak memory 234476 kb
Host smart-a7e08288-cdff-49f1-941e-7f45920d5d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169437009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3169437009
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1612404105
Short name T855
Test name
Test status
Simulation time 1158768184 ps
CPU time 7.63 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:34 PM PDT 24
Peak memory 233284 kb
Host smart-caaaf270-fac5-4a10-8cf4-3eda3a6ed08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612404105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1612404105
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3401300122
Short name T510
Test name
Test status
Simulation time 662933971 ps
CPU time 8.2 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:33 PM PDT 24
Peak memory 249752 kb
Host smart-75dfec2d-c584-4ad9-b33e-f2f0d7ef9054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401300122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3401300122
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3095672428
Short name T942
Test name
Test status
Simulation time 1801775891 ps
CPU time 14.87 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:40 PM PDT 24
Peak memory 222960 kb
Host smart-63449ef9-7721-4ca3-b3a0-619663ac8294
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095672428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3095672428
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4090332236
Short name T826
Test name
Test status
Simulation time 20919837899 ps
CPU time 219.35 seconds
Started Aug 01 05:18:29 PM PDT 24
Finished Aug 01 05:22:09 PM PDT 24
Peak memory 254164 kb
Host smart-021fce1b-c050-42c3-8d98-c3edaf388e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090332236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4090332236
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3257540620
Short name T411
Test name
Test status
Simulation time 17004239346 ps
CPU time 26.57 seconds
Started Aug 01 05:18:15 PM PDT 24
Finished Aug 01 05:18:42 PM PDT 24
Peak memory 216932 kb
Host smart-4cc9def0-98bc-4d20-8dd6-48be91e306dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257540620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3257540620
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1235638805
Short name T585
Test name
Test status
Simulation time 5868197950 ps
CPU time 6.42 seconds
Started Aug 01 05:18:23 PM PDT 24
Finished Aug 01 05:18:30 PM PDT 24
Peak memory 216972 kb
Host smart-ff64059b-f5db-4865-9194-54ba79c1858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235638805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1235638805
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.692638114
Short name T797
Test name
Test status
Simulation time 376360523 ps
CPU time 2.34 seconds
Started Aug 01 05:18:31 PM PDT 24
Finished Aug 01 05:18:33 PM PDT 24
Peak memory 216968 kb
Host smart-e1536502-09f8-49d7-a603-a88ef9a8170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692638114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.692638114
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1058600439
Short name T581
Test name
Test status
Simulation time 158517921 ps
CPU time 0.85 seconds
Started Aug 01 05:18:22 PM PDT 24
Finished Aug 01 05:18:23 PM PDT 24
Peak memory 206516 kb
Host smart-eb5a9851-364a-406b-b8fd-20010fedd876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058600439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1058600439
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.642654070
Short name T743
Test name
Test status
Simulation time 7717431946 ps
CPU time 8.37 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:34 PM PDT 24
Peak memory 225312 kb
Host smart-86d7027e-ad0a-44dd-8cf9-64e3c7c289e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642654070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.642654070
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2320797502
Short name T744
Test name
Test status
Simulation time 37844952 ps
CPU time 0.71 seconds
Started Aug 01 05:18:29 PM PDT 24
Finished Aug 01 05:18:30 PM PDT 24
Peak memory 206204 kb
Host smart-1e0bffa6-e2a6-4cb7-ad34-a3fdad2042eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320797502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2320797502
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3014333332
Short name T245
Test name
Test status
Simulation time 412797880 ps
CPU time 6.35 seconds
Started Aug 01 05:18:29 PM PDT 24
Finished Aug 01 05:18:35 PM PDT 24
Peak memory 233352 kb
Host smart-ff8882a9-66c3-45a7-8f3d-8052cf16cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014333332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3014333332
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1748027218
Short name T691
Test name
Test status
Simulation time 15738380 ps
CPU time 0.74 seconds
Started Aug 01 05:18:31 PM PDT 24
Finished Aug 01 05:18:32 PM PDT 24
Peak memory 206368 kb
Host smart-de40f909-a9b0-49f8-b380-411a759c4d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748027218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1748027218
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1714775494
Short name T520
Test name
Test status
Simulation time 18521584427 ps
CPU time 138.91 seconds
Started Aug 01 05:18:27 PM PDT 24
Finished Aug 01 05:20:46 PM PDT 24
Peak memory 233508 kb
Host smart-d23e1b8f-9289-4d0c-93bd-c84286e6b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714775494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1714775494
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.284231095
Short name T268
Test name
Test status
Simulation time 248429160525 ps
CPU time 549.25 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 270324 kb
Host smart-37b5391c-2276-4deb-ba6b-0f420757526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284231095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.284231095
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3215634766
Short name T133
Test name
Test status
Simulation time 17170427696 ps
CPU time 201.43 seconds
Started Aug 01 05:18:24 PM PDT 24
Finished Aug 01 05:21:46 PM PDT 24
Peak memory 257088 kb
Host smart-7e3b47e6-12fd-4c2e-be12-91685a6f32cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215634766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3215634766
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1445490383
Short name T490
Test name
Test status
Simulation time 10571133797 ps
CPU time 18.31 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:43 PM PDT 24
Peak memory 225240 kb
Host smart-dc218d21-d5ba-4c16-9fab-7b00b3bb1f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445490383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1445490383
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3251785892
Short name T739
Test name
Test status
Simulation time 1061877677 ps
CPU time 6.19 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:32 PM PDT 24
Peak memory 233340 kb
Host smart-00a191fb-31f3-4544-88a9-90d708471ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251785892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3251785892
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2876891411
Short name T270
Test name
Test status
Simulation time 505864410 ps
CPU time 5.87 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:32 PM PDT 24
Peak memory 233392 kb
Host smart-cb26645d-f26f-48e3-8246-57771e7c9b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876891411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2876891411
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.753088387
Short name T817
Test name
Test status
Simulation time 1912095399 ps
CPU time 5.9 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:31 PM PDT 24
Peak memory 233344 kb
Host smart-f8b700ab-870a-413a-9534-acffe689bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753088387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.753088387
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1163025655
Short name T1009
Test name
Test status
Simulation time 30968119 ps
CPU time 2.08 seconds
Started Aug 01 05:18:27 PM PDT 24
Finished Aug 01 05:18:29 PM PDT 24
Peak memory 223620 kb
Host smart-b22d3351-0050-43f4-bf70-5473a2c8258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163025655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1163025655
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1145274778
Short name T760
Test name
Test status
Simulation time 1164814527 ps
CPU time 8.01 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:34 PM PDT 24
Peak memory 221312 kb
Host smart-795fb1a8-9d91-462a-9041-edc6ece219a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1145274778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1145274778
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2074353656
Short name T160
Test name
Test status
Simulation time 25339499349 ps
CPU time 120.98 seconds
Started Aug 01 05:18:27 PM PDT 24
Finished Aug 01 05:20:28 PM PDT 24
Peak memory 258048 kb
Host smart-a82b4cba-3257-43ce-8ada-bd6839b88cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074353656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2074353656
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1674949679
Short name T85
Test name
Test status
Simulation time 6347241499 ps
CPU time 30.06 seconds
Started Aug 01 05:18:31 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 217028 kb
Host smart-0be58dd8-cbd1-469a-9ced-69b1ad6bf097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674949679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1674949679
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2579354225
Short name T947
Test name
Test status
Simulation time 887692690 ps
CPU time 4.76 seconds
Started Aug 01 05:18:34 PM PDT 24
Finished Aug 01 05:18:39 PM PDT 24
Peak memory 216852 kb
Host smart-3ee2ba3e-b693-4460-896d-c54b35f7dd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579354225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2579354225
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1576893382
Short name T684
Test name
Test status
Simulation time 124783226 ps
CPU time 1.86 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:28 PM PDT 24
Peak memory 216920 kb
Host smart-45a8d93f-f392-41e1-abf4-e6407f83d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576893382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1576893382
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.916241910
Short name T920
Test name
Test status
Simulation time 55370174 ps
CPU time 0.67 seconds
Started Aug 01 05:18:25 PM PDT 24
Finished Aug 01 05:18:26 PM PDT 24
Peak memory 206116 kb
Host smart-855cb42e-bc18-4631-b5b1-bfbce68f52e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916241910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.916241910
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.977300640
Short name T923
Test name
Test status
Simulation time 630376039 ps
CPU time 2.85 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:29 PM PDT 24
Peak memory 225312 kb
Host smart-f6ef3d7b-b0fe-444a-aa2d-61e76c66dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977300640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.977300640
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1198516632
Short name T462
Test name
Test status
Simulation time 21688566 ps
CPU time 0.73 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:37 PM PDT 24
Peak memory 206120 kb
Host smart-a120d31e-a264-429b-a67c-2c0a8869162c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198516632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1198516632
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2517181169
Short name T40
Test name
Test status
Simulation time 73344085 ps
CPU time 2.31 seconds
Started Aug 01 05:18:29 PM PDT 24
Finished Aug 01 05:18:32 PM PDT 24
Peak memory 224576 kb
Host smart-f10d92d4-23cb-4395-a3f5-0f4221184c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517181169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2517181169
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1223021127
Short name T788
Test name
Test status
Simulation time 63770443 ps
CPU time 0.78 seconds
Started Aug 01 05:18:27 PM PDT 24
Finished Aug 01 05:18:28 PM PDT 24
Peak memory 205888 kb
Host smart-fb69d67f-4156-47bb-9725-753e0d1192f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223021127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1223021127
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3930072624
Short name T737
Test name
Test status
Simulation time 2439301435 ps
CPU time 57.1 seconds
Started Aug 01 05:18:32 PM PDT 24
Finished Aug 01 05:19:29 PM PDT 24
Peak memory 256776 kb
Host smart-6ded52bf-5b38-4936-bfb2-9a85ae283df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930072624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3930072624
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3566061375
Short name T814
Test name
Test status
Simulation time 5204451018 ps
CPU time 53.3 seconds
Started Aug 01 05:18:32 PM PDT 24
Finished Aug 01 05:19:25 PM PDT 24
Peak memory 233476 kb
Host smart-6f7683d4-6b55-42a5-8c21-e3b8b99f13fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566061375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3566061375
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.218325415
Short name T583
Test name
Test status
Simulation time 10746902620 ps
CPU time 25.18 seconds
Started Aug 01 05:18:39 PM PDT 24
Finished Aug 01 05:19:04 PM PDT 24
Peak memory 249636 kb
Host smart-694210d2-2eda-461c-8c51-47cff0ef9f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218325415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.218325415
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2618371828
Short name T196
Test name
Test status
Simulation time 93230523503 ps
CPU time 88.53 seconds
Started Aug 01 05:18:34 PM PDT 24
Finished Aug 01 05:20:03 PM PDT 24
Peak memory 266148 kb
Host smart-2f52efbf-df4a-4f68-9979-45b77d895f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618371828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2618371828
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4075447494
Short name T333
Test name
Test status
Simulation time 57165519 ps
CPU time 2.34 seconds
Started Aug 01 05:18:33 PM PDT 24
Finished Aug 01 05:18:36 PM PDT 24
Peak memory 227300 kb
Host smart-cb2dca27-3717-461b-9fee-a37f27db8ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075447494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4075447494
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1411066564
Short name T713
Test name
Test status
Simulation time 4801453684 ps
CPU time 19.71 seconds
Started Aug 01 05:18:30 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 225324 kb
Host smart-41a4246d-9d64-431c-9b41-96abf0229031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411066564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1411066564
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.914923094
Short name T220
Test name
Test status
Simulation time 1594288774 ps
CPU time 7.23 seconds
Started Aug 01 05:18:29 PM PDT 24
Finished Aug 01 05:18:37 PM PDT 24
Peak memory 225068 kb
Host smart-9c7d8008-2374-40c4-b899-9158a771c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914923094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.914923094
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.664298614
Short name T709
Test name
Test status
Simulation time 2163882036 ps
CPU time 9.55 seconds
Started Aug 01 05:18:30 PM PDT 24
Finished Aug 01 05:18:40 PM PDT 24
Peak memory 233548 kb
Host smart-fec03adb-2481-4050-93b1-516acc9723f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664298614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.664298614
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2801039188
Short name T135
Test name
Test status
Simulation time 104716666 ps
CPU time 3.73 seconds
Started Aug 01 05:18:27 PM PDT 24
Finished Aug 01 05:18:31 PM PDT 24
Peak memory 223212 kb
Host smart-73942fb1-de33-46b8-9d44-264957aac7d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2801039188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2801039188
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1180457214
Short name T1
Test name
Test status
Simulation time 332057166 ps
CPU time 2.48 seconds
Started Aug 01 05:18:27 PM PDT 24
Finished Aug 01 05:18:30 PM PDT 24
Peak memory 216832 kb
Host smart-dcf52fa5-2bcd-49a1-95b6-ce3a5189e7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180457214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1180457214
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.241637984
Short name T496
Test name
Test status
Simulation time 9019798608 ps
CPU time 6.69 seconds
Started Aug 01 05:18:28 PM PDT 24
Finished Aug 01 05:18:35 PM PDT 24
Peak memory 217056 kb
Host smart-7306dc62-5c82-438b-989d-5410818829fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241637984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.241637984
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.666483145
Short name T529
Test name
Test status
Simulation time 2459732666 ps
CPU time 3.23 seconds
Started Aug 01 05:18:28 PM PDT 24
Finished Aug 01 05:18:31 PM PDT 24
Peak memory 216936 kb
Host smart-148cd299-19af-42a3-8ed5-0cc845f426f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666483145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.666483145
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3757966222
Short name T353
Test name
Test status
Simulation time 105351925 ps
CPU time 0.98 seconds
Started Aug 01 05:18:26 PM PDT 24
Finished Aug 01 05:18:27 PM PDT 24
Peak memory 207592 kb
Host smart-6d282897-fdd5-41de-bcae-176d911a799e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757966222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3757966222
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1672827738
Short name T255
Test name
Test status
Simulation time 7990461184 ps
CPU time 15.01 seconds
Started Aug 01 05:18:33 PM PDT 24
Finished Aug 01 05:18:49 PM PDT 24
Peak memory 238688 kb
Host smart-163717f7-24e8-4895-8823-f757e2610a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672827738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1672827738
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3003828205
Short name T442
Test name
Test status
Simulation time 104512266 ps
CPU time 0.71 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 205208 kb
Host smart-314b29ed-5ed6-4506-b60b-874d527ef0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003828205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
003828205
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.901826780
Short name T434
Test name
Test status
Simulation time 1294976605 ps
CPU time 10.72 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:10 PM PDT 24
Peak memory 233296 kb
Host smart-220e06ed-9453-4e53-b564-6630201a7c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901826780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.901826780
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3259592720
Short name T344
Test name
Test status
Simulation time 53674146 ps
CPU time 0.91 seconds
Started Aug 01 05:16:03 PM PDT 24
Finished Aug 01 05:16:04 PM PDT 24
Peak memory 207076 kb
Host smart-3a94d12c-0ae7-408b-8ac8-a27a20d421fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259592720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3259592720
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1779014587
Short name T190
Test name
Test status
Simulation time 118895280772 ps
CPU time 438.02 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:23:16 PM PDT 24
Peak memory 266528 kb
Host smart-e6ab8e85-0f95-4a3b-a800-920bebcc112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779014587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1779014587
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2897062902
Short name T221
Test name
Test status
Simulation time 48941144922 ps
CPU time 165.01 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:18:45 PM PDT 24
Peak memory 267144 kb
Host smart-721a8c06-9698-45b9-97c6-cc3e8b4ee626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897062902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2897062902
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.173557744
Short name T79
Test name
Test status
Simulation time 15036572279 ps
CPU time 111.56 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:17:49 PM PDT 24
Peak memory 258016 kb
Host smart-9f13f725-c022-4938-9fe8-95952a1db020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173557744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
173557744
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1510159774
Short name T306
Test name
Test status
Simulation time 8765472537 ps
CPU time 95.45 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:17:32 PM PDT 24
Peak memory 253116 kb
Host smart-2d14bf06-2822-46f7-ad60-6c4f77efcb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510159774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1510159774
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2572757952
Short name T457
Test name
Test status
Simulation time 1759412193 ps
CPU time 4.86 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:16:02 PM PDT 24
Peak memory 225248 kb
Host smart-23997d89-2947-417d-977b-6cf1c90cd4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572757952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2572757952
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2403304098
Short name T971
Test name
Test status
Simulation time 7997319961 ps
CPU time 19.6 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:16:20 PM PDT 24
Peak memory 233448 kb
Host smart-387fe29d-2139-41bd-8eab-da5c8126fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403304098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2403304098
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2419299871
Short name T393
Test name
Test status
Simulation time 3565191944 ps
CPU time 10.85 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:10 PM PDT 24
Peak memory 241512 kb
Host smart-abab80da-eba3-492b-8ed9-738c87b23de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419299871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2419299871
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3464826513
Short name T37
Test name
Test status
Simulation time 24900489 ps
CPU time 1.04 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 217204 kb
Host smart-5a61233c-69b1-4e6a-8acf-b715c3ffe6d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464826513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3464826513
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4288081204
Short name T902
Test name
Test status
Simulation time 23102007844 ps
CPU time 18.31 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:16:15 PM PDT 24
Peak memory 225076 kb
Host smart-53048856-1eef-4013-9774-c17ba92c0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288081204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4288081204
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1043560776
Short name T192
Test name
Test status
Simulation time 881769619 ps
CPU time 4.76 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:16:01 PM PDT 24
Peak memory 233348 kb
Host smart-ceb94855-8d07-4e8f-afa6-11a75f2972d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043560776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1043560776
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1374418650
Short name T754
Test name
Test status
Simulation time 192388840 ps
CPU time 3.48 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:03 PM PDT 24
Peak memory 223136 kb
Host smart-4f8eb692-953a-4bcc-af6f-6f7ca353a72d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1374418650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1374418650
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.790362531
Short name T65
Test name
Test status
Simulation time 63659126 ps
CPU time 1.07 seconds
Started Aug 01 05:15:55 PM PDT 24
Finished Aug 01 05:15:56 PM PDT 24
Peak memory 235488 kb
Host smart-f84bda22-2883-4749-b51b-63892bec9c00
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790362531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.790362531
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.58948164
Short name T916
Test name
Test status
Simulation time 3217552072 ps
CPU time 26.68 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:25 PM PDT 24
Peak memory 225236 kb
Host smart-ec5bf08a-adb0-439d-bd0d-b067fed346a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58948164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.58948164
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3316323173
Short name T783
Test name
Test status
Simulation time 12589555 ps
CPU time 0.71 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 206096 kb
Host smart-6ed931af-fca8-43cd-8685-5cbf48af07a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316323173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3316323173
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.581062224
Short name T649
Test name
Test status
Simulation time 395682347 ps
CPU time 1.98 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:00 PM PDT 24
Peak memory 208488 kb
Host smart-567d8152-2a61-4201-a4f7-59064774c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581062224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.581062224
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2275435134
Short name T405
Test name
Test status
Simulation time 107852783 ps
CPU time 1.43 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 217012 kb
Host smart-ac9e870d-b54d-4dd0-a3ad-adb36d24235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275435134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2275435134
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.181479973
Short name T512
Test name
Test status
Simulation time 70919737 ps
CPU time 0.94 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:15:57 PM PDT 24
Peak memory 206932 kb
Host smart-1079dd7e-c561-433b-a25e-e7f571cdbd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181479973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.181479973
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1337610831
Short name T251
Test name
Test status
Simulation time 2737254693 ps
CPU time 10.14 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:16:07 PM PDT 24
Peak memory 249780 kb
Host smart-72f8626b-d45d-4cfb-a3e4-9df14c6b8a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337610831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1337610831
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2952553771
Short name T646
Test name
Test status
Simulation time 30453587 ps
CPU time 0.7 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:37 PM PDT 24
Peak memory 205856 kb
Host smart-395cb314-f3eb-4fa2-9df1-5238d7effa1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952553771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2952553771
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3161749981
Short name T389
Test name
Test status
Simulation time 1847487506 ps
CPU time 15.46 seconds
Started Aug 01 05:18:41 PM PDT 24
Finished Aug 01 05:18:56 PM PDT 24
Peak memory 225276 kb
Host smart-dee859ba-22ac-4cb5-a6a6-7f053220ea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161749981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3161749981
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3868961740
Short name T492
Test name
Test status
Simulation time 15930059 ps
CPU time 0.72 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:37 PM PDT 24
Peak memory 205968 kb
Host smart-2d3cae60-baf6-4042-8e46-26cd31abf879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868961740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3868961740
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2266025575
Short name T672
Test name
Test status
Simulation time 170772727949 ps
CPU time 252.64 seconds
Started Aug 01 05:18:37 PM PDT 24
Finished Aug 01 05:22:50 PM PDT 24
Peak memory 251224 kb
Host smart-28ccd35f-456b-4992-b7e1-d5a44b03e9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266025575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2266025575
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2793740904
Short name T682
Test name
Test status
Simulation time 36659072684 ps
CPU time 221.08 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:22:17 PM PDT 24
Peak memory 254660 kb
Host smart-113cdbc8-2122-4463-b624-5fff9cd6c624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793740904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2793740904
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1627186963
Short name T962
Test name
Test status
Simulation time 145561964255 ps
CPU time 242.74 seconds
Started Aug 01 05:18:37 PM PDT 24
Finished Aug 01 05:22:40 PM PDT 24
Peak memory 256204 kb
Host smart-9fd6f5b2-6bc9-413f-9c2c-8c1d8af9ceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627186963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1627186963
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.461719631
Short name T637
Test name
Test status
Simulation time 3871221912 ps
CPU time 11.52 seconds
Started Aug 01 05:18:38 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 236304 kb
Host smart-448f8d7a-0239-4f5b-81a5-c86e302c497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461719631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.461719631
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.212295708
Short name T981
Test name
Test status
Simulation time 6995072872 ps
CPU time 87.63 seconds
Started Aug 01 05:18:42 PM PDT 24
Finished Aug 01 05:20:10 PM PDT 24
Peak memory 253348 kb
Host smart-7d2f41a1-49e1-4779-a2d4-548f07e5330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212295708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.212295708
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4217379525
Short name T856
Test name
Test status
Simulation time 1099893652 ps
CPU time 3.11 seconds
Started Aug 01 05:18:42 PM PDT 24
Finished Aug 01 05:18:45 PM PDT 24
Peak memory 233324 kb
Host smart-4faab6a4-8534-483c-8425-cb4945fbeac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217379525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4217379525
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2556944631
Short name T751
Test name
Test status
Simulation time 156973656 ps
CPU time 2.91 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:39 PM PDT 24
Peak memory 225140 kb
Host smart-4e5ca54e-c0bf-44cf-a8ef-f7e587038d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556944631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2556944631
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1121899512
Short name T263
Test name
Test status
Simulation time 7412610138 ps
CPU time 7.86 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:44 PM PDT 24
Peak memory 233512 kb
Host smart-b009b2ff-da1b-4e07-8252-62aafe24f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121899512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1121899512
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4161375409
Short name T566
Test name
Test status
Simulation time 16519054153 ps
CPU time 15.82 seconds
Started Aug 01 05:18:35 PM PDT 24
Finished Aug 01 05:18:51 PM PDT 24
Peak memory 233504 kb
Host smart-78409a4c-0a60-4dd5-8259-78f5161b86c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161375409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4161375409
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.514935660
Short name T454
Test name
Test status
Simulation time 6302095798 ps
CPU time 11.24 seconds
Started Aug 01 05:18:42 PM PDT 24
Finished Aug 01 05:18:53 PM PDT 24
Peak memory 222176 kb
Host smart-8d90e732-74fe-4896-9813-1d5af482717d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=514935660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.514935660
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1255967133
Short name T955
Test name
Test status
Simulation time 12943246 ps
CPU time 0.72 seconds
Started Aug 01 05:18:38 PM PDT 24
Finished Aug 01 05:18:39 PM PDT 24
Peak memory 206204 kb
Host smart-0aa3043b-6771-4e40-8122-8f6a5c85dfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255967133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1255967133
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2311669837
Short name T832
Test name
Test status
Simulation time 12235385196 ps
CPU time 19.78 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:56 PM PDT 24
Peak memory 216956 kb
Host smart-a3d1294f-8ddd-4610-bf7d-a61501b36cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311669837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2311669837
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4065277968
Short name T610
Test name
Test status
Simulation time 11968916 ps
CPU time 0.8 seconds
Started Aug 01 05:18:35 PM PDT 24
Finished Aug 01 05:18:36 PM PDT 24
Peak memory 206036 kb
Host smart-fdc2ee39-bd23-4f09-a6b9-650dd48528ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065277968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4065277968
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3227407354
Short name T88
Test name
Test status
Simulation time 252398317 ps
CPU time 0.81 seconds
Started Aug 01 05:18:37 PM PDT 24
Finished Aug 01 05:18:38 PM PDT 24
Peak memory 206560 kb
Host smart-aa24daa0-511c-421c-9588-66a3a44f29e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227407354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3227407354
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2882751627
Short name T838
Test name
Test status
Simulation time 519285964 ps
CPU time 5.67 seconds
Started Aug 01 05:18:39 PM PDT 24
Finished Aug 01 05:18:45 PM PDT 24
Peak memory 241452 kb
Host smart-04b76055-1705-44d1-804e-6d9ebbd0f577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882751627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2882751627
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3635648473
Short name T446
Test name
Test status
Simulation time 40709016 ps
CPU time 0.76 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 205208 kb
Host smart-e00f91ed-8b82-4e16-8bf7-83becf34a5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635648473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3635648473
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.250021708
Short name T249
Test name
Test status
Simulation time 12791867897 ps
CPU time 19.09 seconds
Started Aug 01 05:18:39 PM PDT 24
Finished Aug 01 05:18:59 PM PDT 24
Peak memory 233308 kb
Host smart-e215c79e-2fea-40fd-9ced-067f34bfba72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250021708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.250021708
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.942324154
Short name T163
Test name
Test status
Simulation time 29514965 ps
CPU time 0.8 seconds
Started Aug 01 05:18:38 PM PDT 24
Finished Aug 01 05:18:39 PM PDT 24
Peak memory 206900 kb
Host smart-2d060103-19b4-4bc0-a044-2b8c8dea54fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942324154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.942324154
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2201324412
Short name T320
Test name
Test status
Simulation time 33469185059 ps
CPU time 63.25 seconds
Started Aug 01 05:18:38 PM PDT 24
Finished Aug 01 05:19:41 PM PDT 24
Peak memory 236532 kb
Host smart-5ad26f5d-5f78-4f38-9831-555852680ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201324412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2201324412
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1473294195
Short name T1017
Test name
Test status
Simulation time 434978302621 ps
CPU time 233.02 seconds
Started Aug 01 05:18:37 PM PDT 24
Finished Aug 01 05:22:30 PM PDT 24
Peak memory 251100 kb
Host smart-aa46c7a8-a5d2-4ca1-9bd0-a79948bfa5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473294195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1473294195
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3161578128
Short name T312
Test name
Test status
Simulation time 1136634672 ps
CPU time 22.6 seconds
Started Aug 01 05:18:39 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 241556 kb
Host smart-cfb1d8bd-8191-4459-bcb5-f781b4418685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161578128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3161578128
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.920014926
Short name T180
Test name
Test status
Simulation time 6358519989 ps
CPU time 90.69 seconds
Started Aug 01 05:18:37 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 251036 kb
Host smart-474e35f9-9869-4b4f-a92f-93170cbcac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920014926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.920014926
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1555831950
Short name T240
Test name
Test status
Simulation time 438558167 ps
CPU time 5.68 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:42 PM PDT 24
Peak memory 233368 kb
Host smart-04d18ed2-f222-4909-91ea-d9d405f0d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555831950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1555831950
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1635049485
Short name T974
Test name
Test status
Simulation time 646298569 ps
CPU time 9.18 seconds
Started Aug 01 05:18:37 PM PDT 24
Finished Aug 01 05:18:46 PM PDT 24
Peak memory 225180 kb
Host smart-58c27d37-518d-48c4-901f-0d590a9a023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635049485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1635049485
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3199534717
Short name T41
Test name
Test status
Simulation time 531060421 ps
CPU time 3.85 seconds
Started Aug 01 05:18:38 PM PDT 24
Finished Aug 01 05:18:42 PM PDT 24
Peak memory 233500 kb
Host smart-2351ed94-ddd1-4a7a-b6da-cc6ca3fc97d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199534717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3199534717
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2178811792
Short name T589
Test name
Test status
Simulation time 519598733 ps
CPU time 2.48 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:38 PM PDT 24
Peak memory 225092 kb
Host smart-663463cf-1a14-4341-8cc0-946ab759c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178811792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2178811792
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1371484692
Short name T824
Test name
Test status
Simulation time 353871523 ps
CPU time 5.21 seconds
Started Aug 01 05:18:37 PM PDT 24
Finished Aug 01 05:18:43 PM PDT 24
Peak memory 222868 kb
Host smart-5878fbe8-f9d6-495f-bd00-f284f210d401
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1371484692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1371484692
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3917470507
Short name T590
Test name
Test status
Simulation time 3146483304 ps
CPU time 22.08 seconds
Started Aug 01 05:18:38 PM PDT 24
Finished Aug 01 05:19:00 PM PDT 24
Peak memory 217032 kb
Host smart-00b45df5-e979-4674-8330-cd3e13060774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917470507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3917470507
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3681089956
Short name T392
Test name
Test status
Simulation time 2065110980 ps
CPU time 2.23 seconds
Started Aug 01 05:18:36 PM PDT 24
Finished Aug 01 05:18:38 PM PDT 24
Peak memory 208452 kb
Host smart-9032f8d2-de4e-4f70-ac16-4360984b3553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681089956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3681089956
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1672537466
Short name T385
Test name
Test status
Simulation time 47742384 ps
CPU time 0.92 seconds
Started Aug 01 05:18:42 PM PDT 24
Finished Aug 01 05:18:43 PM PDT 24
Peak memory 207640 kb
Host smart-dfcc1e6f-5fb8-4e11-be1c-82e6a1b85c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672537466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1672537466
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1310172699
Short name T934
Test name
Test status
Simulation time 38456718 ps
CPU time 0.86 seconds
Started Aug 01 05:18:40 PM PDT 24
Finished Aug 01 05:18:41 PM PDT 24
Peak memory 207616 kb
Host smart-8efae94f-d172-4fb1-bf61-38f7d6c3c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310172699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1310172699
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2206699922
Short name T736
Test name
Test status
Simulation time 10889880599 ps
CPU time 6.32 seconds
Started Aug 01 05:18:39 PM PDT 24
Finished Aug 01 05:18:45 PM PDT 24
Peak memory 225232 kb
Host smart-36694cea-b76b-432b-8a02-72e9772c7207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206699922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2206699922
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.477868668
Short name T401
Test name
Test status
Simulation time 51175016 ps
CPU time 0.74 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:18:49 PM PDT 24
Peak memory 206128 kb
Host smart-41b543ca-3681-4632-b41b-b65793d59408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477868668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.477868668
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3272082505
Short name T611
Test name
Test status
Simulation time 109591829 ps
CPU time 2.13 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 225228 kb
Host smart-995060dc-e728-4dda-a294-adab05e1e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272082505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3272082505
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.714993836
Short name T895
Test name
Test status
Simulation time 21415145 ps
CPU time 0.76 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:18:48 PM PDT 24
Peak memory 206956 kb
Host smart-fe4ebf99-6fc8-47d6-a02c-f1237e829cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714993836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.714993836
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1435446326
Short name T907
Test name
Test status
Simulation time 3722433150 ps
CPU time 24.08 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:19:12 PM PDT 24
Peak memory 241704 kb
Host smart-0704dbcc-e02c-4a5a-b6f6-250f5a7f245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435446326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1435446326
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.727968299
Short name T143
Test name
Test status
Simulation time 37358291549 ps
CPU time 365 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:24:55 PM PDT 24
Peak memory 264208 kb
Host smart-4b87c869-5b9b-45f5-8041-a0b27f905007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727968299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.727968299
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1768263912
Short name T966
Test name
Test status
Simulation time 133769081278 ps
CPU time 364.31 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:24:53 PM PDT 24
Peak memory 266256 kb
Host smart-0230f91d-80eb-42f6-9fa9-a8f067e51884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768263912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1768263912
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3530204412
Short name T970
Test name
Test status
Simulation time 616836491 ps
CPU time 4.67 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:54 PM PDT 24
Peak memory 249732 kb
Host smart-fe7dab3c-06f5-49df-a171-bcdc5488b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530204412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3530204412
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1900560326
Short name T97
Test name
Test status
Simulation time 39121565288 ps
CPU time 273.89 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:23:23 PM PDT 24
Peak memory 267344 kb
Host smart-0f468e0d-b81e-44fb-8912-9e073c25cc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900560326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1900560326
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1479177073
Short name T468
Test name
Test status
Simulation time 143182260 ps
CPU time 3.37 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:18:51 PM PDT 24
Peak memory 233440 kb
Host smart-3a0e365f-a73f-44b8-9a6f-c0de9774a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479177073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1479177073
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.200768785
Short name T488
Test name
Test status
Simulation time 3081469822 ps
CPU time 22.61 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 233368 kb
Host smart-4c014655-c19b-47de-bb68-f32b004f7967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200768785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.200768785
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1079868326
Short name T762
Test name
Test status
Simulation time 967039016 ps
CPU time 7.25 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:18:57 PM PDT 24
Peak memory 233340 kb
Host smart-dda6f067-6ea7-4ea0-958f-a942c91232d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079868326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1079868326
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3146490992
Short name T449
Test name
Test status
Simulation time 31388918 ps
CPU time 2.19 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:18:51 PM PDT 24
Peak memory 233068 kb
Host smart-827f4735-3904-4f76-b251-47fbd2cfa9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146490992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3146490992
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2334355606
Short name T567
Test name
Test status
Simulation time 1023122646 ps
CPU time 7.99 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:58 PM PDT 24
Peak memory 219384 kb
Host smart-cf532876-b30e-439c-bb05-cc51309a6afb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2334355606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2334355606
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2913167674
Short name T162
Test name
Test status
Simulation time 6339243080 ps
CPU time 40.04 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:19:30 PM PDT 24
Peak memory 249896 kb
Host smart-bb412d68-dee9-45fd-9579-a0d9d3bccc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913167674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2913167674
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.900658933
Short name T607
Test name
Test status
Simulation time 27663115619 ps
CPU time 32.39 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:19:20 PM PDT 24
Peak memory 216956 kb
Host smart-1fbe9590-6ae4-4a54-b4e3-8d6d22a68fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900658933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.900658933
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2253288564
Short name T759
Test name
Test status
Simulation time 996003479 ps
CPU time 1.8 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 208528 kb
Host smart-b98fd729-4a12-4c96-b4dd-ac28575ee4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253288564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2253288564
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4244084538
Short name T323
Test name
Test status
Simulation time 132113689 ps
CPU time 1.28 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 208456 kb
Host smart-1f1ba0f2-da3b-4270-9081-3f9781dc5a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244084538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4244084538
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3738239521
Short name T857
Test name
Test status
Simulation time 14743576 ps
CPU time 0.71 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:50 PM PDT 24
Peak memory 206616 kb
Host smart-5bfabe94-e3b4-4e31-88e0-8583ddd40fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738239521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3738239521
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1626140838
Short name T859
Test name
Test status
Simulation time 747839530 ps
CPU time 7.78 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:18:56 PM PDT 24
Peak memory 233512 kb
Host smart-8ced6ddc-5f99-410a-a9fe-9686baf8c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626140838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1626140838
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.531313619
Short name T498
Test name
Test status
Simulation time 24430331 ps
CPU time 0.72 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 206224 kb
Host smart-eb6dd5b9-3fe2-44cc-9eea-21d0503444ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531313619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.531313619
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2676007876
Short name T109
Test name
Test status
Simulation time 541499291 ps
CPU time 8.71 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:58 PM PDT 24
Peak memory 225076 kb
Host smart-38214555-d9f8-4fad-b166-be78a172a928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676007876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2676007876
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2336392621
Short name T382
Test name
Test status
Simulation time 14322172 ps
CPU time 0.78 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:49 PM PDT 24
Peak memory 206968 kb
Host smart-fcc5ebe9-a73d-41fe-98b4-bdb62ea9b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336392621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2336392621
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3084406224
Short name T336
Test name
Test status
Simulation time 12224080 ps
CPU time 0.75 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:18:51 PM PDT 24
Peak memory 216460 kb
Host smart-9f2cbf6a-3ad6-45b4-afc3-faed6ceafa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084406224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3084406224
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2173977751
Short name T299
Test name
Test status
Simulation time 45234846326 ps
CPU time 101.03 seconds
Started Aug 01 05:18:51 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 249800 kb
Host smart-3e9509e6-2510-4057-b716-2e36f0eecb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173977751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2173977751
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.749641229
Short name T582
Test name
Test status
Simulation time 1147120357 ps
CPU time 7.48 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:18:58 PM PDT 24
Peak memory 225244 kb
Host smart-41fb5fb5-715a-485a-a201-9f9f1bc44a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749641229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.749641229
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2685175269
Short name T142
Test name
Test status
Simulation time 18535266485 ps
CPU time 51.58 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:19:40 PM PDT 24
Peak memory 249940 kb
Host smart-b7cce627-e33f-4c4a-a3c3-653570b0321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685175269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2685175269
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2552382707
Short name T372
Test name
Test status
Simulation time 703985658 ps
CPU time 4.48 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:18:53 PM PDT 24
Peak memory 225212 kb
Host smart-588e2977-ff31-4763-a7bc-95c4d0c24d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552382707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2552382707
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.982397099
Short name T685
Test name
Test status
Simulation time 3378421477 ps
CPU time 17.02 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:19:05 PM PDT 24
Peak memory 240452 kb
Host smart-8977e746-a91e-4e37-a699-b8e7382566b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982397099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.982397099
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2673493317
Short name T531
Test name
Test status
Simulation time 145197066 ps
CPU time 3.26 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:18:53 PM PDT 24
Peak memory 228356 kb
Host smart-1c979b01-10da-4424-a8f3-030dbbf81de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673493317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2673493317
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2321026844
Short name T864
Test name
Test status
Simulation time 208313006 ps
CPU time 3.66 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:18:53 PM PDT 24
Peak memory 225116 kb
Host smart-9c7ff5ae-6e56-4562-b5ed-ca2d6db6e17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321026844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2321026844
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.223905372
Short name T151
Test name
Test status
Simulation time 255231257 ps
CPU time 4.26 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:18:51 PM PDT 24
Peak memory 223192 kb
Host smart-b31c332b-b3d0-44cc-8c5d-de295c9870ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=223905372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.223905372
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.627625759
Short name T301
Test name
Test status
Simulation time 8381119401 ps
CPU time 65.83 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:19:56 PM PDT 24
Peak memory 255396 kb
Host smart-7576e1d0-7b91-4f64-a2d7-d3951f5c0017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627625759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.627625759
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2811611819
Short name T317
Test name
Test status
Simulation time 1558329740 ps
CPU time 20.7 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:19:10 PM PDT 24
Peak memory 220620 kb
Host smart-4d298ab4-e2dc-43d8-a798-e0860bf2b202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811611819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2811611819
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1900259554
Short name T779
Test name
Test status
Simulation time 7001365383 ps
CPU time 10 seconds
Started Aug 01 05:18:47 PM PDT 24
Finished Aug 01 05:18:57 PM PDT 24
Peak memory 216844 kb
Host smart-39c6a621-5890-4828-ae4d-db6e3abcb1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900259554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1900259554
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1558434558
Short name T714
Test name
Test status
Simulation time 41968699 ps
CPU time 0.69 seconds
Started Aug 01 05:18:48 PM PDT 24
Finished Aug 01 05:18:49 PM PDT 24
Peak memory 206028 kb
Host smart-c9d70fa9-f3e8-44de-bc25-fa44fb158dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558434558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1558434558
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3573035256
Short name T474
Test name
Test status
Simulation time 88809629 ps
CPU time 0.83 seconds
Started Aug 01 05:18:50 PM PDT 24
Finished Aug 01 05:18:51 PM PDT 24
Peak memory 206484 kb
Host smart-2e3341c2-7151-44a0-8733-b9bae0b33ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573035256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3573035256
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1045977781
Short name T209
Test name
Test status
Simulation time 170304949 ps
CPU time 2.9 seconds
Started Aug 01 05:18:49 PM PDT 24
Finished Aug 01 05:18:52 PM PDT 24
Peak memory 233316 kb
Host smart-21c15cf6-6746-4ec8-908d-7a0261a7bd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045977781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1045977781
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3570754164
Short name T643
Test name
Test status
Simulation time 14115487 ps
CPU time 0.73 seconds
Started Aug 01 05:18:58 PM PDT 24
Finished Aug 01 05:18:59 PM PDT 24
Peak memory 206208 kb
Host smart-e41e024b-dc5b-45e4-865f-f458c00642fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570754164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3570754164
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4157107924
Short name T1024
Test name
Test status
Simulation time 5666579431 ps
CPU time 7.25 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:19:09 PM PDT 24
Peak memory 225164 kb
Host smart-d9bf3041-f204-48f3-8574-7032899059c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157107924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4157107924
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1297749781
Short name T873
Test name
Test status
Simulation time 21056922 ps
CPU time 0.81 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:00 PM PDT 24
Peak memory 207036 kb
Host smart-7241a3f2-576d-434b-a168-6fbddda06e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297749781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1297749781
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3115886133
Short name T628
Test name
Test status
Simulation time 14105238979 ps
CPU time 50.79 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:50 PM PDT 24
Peak memory 255868 kb
Host smart-a1f0b1f7-7fab-44bd-a07f-034977d5d325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115886133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3115886133
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2312416491
Short name T181
Test name
Test status
Simulation time 1132317496 ps
CPU time 11.57 seconds
Started Aug 01 05:19:02 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 221876 kb
Host smart-7c2620ef-6353-4151-a65c-19c709b2302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312416491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2312416491
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.929265159
Short name T508
Test name
Test status
Simulation time 39032506102 ps
CPU time 363.14 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:25:04 PM PDT 24
Peak memory 251956 kb
Host smart-bc41aabb-2ace-4cc4-b209-372f8af292a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929265159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.929265159
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2470075836
Short name T431
Test name
Test status
Simulation time 3081461594 ps
CPU time 8.44 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:08 PM PDT 24
Peak memory 234908 kb
Host smart-393da654-a992-4ce1-be23-0e4f932afeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470075836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2470075836
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2934428229
Short name T216
Test name
Test status
Simulation time 541926749720 ps
CPU time 317.48 seconds
Started Aug 01 05:19:03 PM PDT 24
Finished Aug 01 05:24:20 PM PDT 24
Peak memory 249816 kb
Host smart-d22f17eb-32a9-41b7-becd-4a8a6f219081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934428229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2934428229
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2851684204
Short name T932
Test name
Test status
Simulation time 1971109030 ps
CPU time 6.91 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:07 PM PDT 24
Peak memory 233368 kb
Host smart-d6f986fe-8970-4d87-bfcf-8616cf26d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851684204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2851684204
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.987725962
Short name T254
Test name
Test status
Simulation time 6885864372 ps
CPU time 13.86 seconds
Started Aug 01 05:19:02 PM PDT 24
Finished Aug 01 05:19:16 PM PDT 24
Peak memory 224524 kb
Host smart-e49ad96c-2244-4c89-838f-9cbfc79851db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987725962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.987725962
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3341360788
Short name T866
Test name
Test status
Simulation time 283529541 ps
CPU time 2.68 seconds
Started Aug 01 05:18:58 PM PDT 24
Finished Aug 01 05:19:01 PM PDT 24
Peak memory 233464 kb
Host smart-8a02d347-2434-4098-b814-a417894673fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341360788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3341360788
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1488053419
Short name T275
Test name
Test status
Simulation time 7026719828 ps
CPU time 12.6 seconds
Started Aug 01 05:19:04 PM PDT 24
Finished Aug 01 05:19:17 PM PDT 24
Peak memory 225204 kb
Host smart-64dbb325-1656-4d7a-9d83-967453761f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488053419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1488053419
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2101469107
Short name T150
Test name
Test status
Simulation time 409916057 ps
CPU time 6.49 seconds
Started Aug 01 05:18:57 PM PDT 24
Finished Aug 01 05:19:04 PM PDT 24
Peak memory 219356 kb
Host smart-611b8666-946a-4cc2-8885-e44b814b9c41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2101469107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2101469107
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1816332398
Short name T287
Test name
Test status
Simulation time 5960974305 ps
CPU time 44.52 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:45 PM PDT 24
Peak memory 241656 kb
Host smart-bff4eaff-db66-4407-91c3-4caae6ac1217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816332398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1816332398
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4228899941
Short name T514
Test name
Test status
Simulation time 2299963410 ps
CPU time 5.12 seconds
Started Aug 01 05:18:58 PM PDT 24
Finished Aug 01 05:19:04 PM PDT 24
Peak memory 217088 kb
Host smart-cba2ecff-28f1-492e-8c35-aa1739b26b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228899941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4228899941
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2415295217
Short name T376
Test name
Test status
Simulation time 1116121590 ps
CPU time 7.61 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:07 PM PDT 24
Peak memory 216924 kb
Host smart-76245f00-591d-4c90-8c3e-1ea764274891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415295217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2415295217
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2619018884
Short name T487
Test name
Test status
Simulation time 335643124 ps
CPU time 1.44 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:01 PM PDT 24
Peak memory 216884 kb
Host smart-f37210d3-9fd9-4659-ac6e-29621b1040ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619018884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2619018884
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2669366933
Short name T735
Test name
Test status
Simulation time 227969266 ps
CPU time 0.95 seconds
Started Aug 01 05:19:04 PM PDT 24
Finished Aug 01 05:19:05 PM PDT 24
Peak memory 207524 kb
Host smart-8393f348-74b9-42dd-9595-d6a84577cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669366933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2669366933
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2363745151
Short name T550
Test name
Test status
Simulation time 5436452809 ps
CPU time 16.17 seconds
Started Aug 01 05:19:04 PM PDT 24
Finished Aug 01 05:19:20 PM PDT 24
Peak memory 249852 kb
Host smart-dcefcc65-8f3d-495e-bd40-540844dd2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363745151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2363745151
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2364287682
Short name T63
Test name
Test status
Simulation time 23862633 ps
CPU time 0.73 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:01 PM PDT 24
Peak memory 205740 kb
Host smart-02ac7556-a967-4c92-8c4f-3cf73e4166c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364287682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2364287682
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.772220822
Short name T502
Test name
Test status
Simulation time 114401112 ps
CPU time 2.04 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 225192 kb
Host smart-7e750a24-4b2e-4155-a708-a0ba53711ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772220822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.772220822
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.53201418
Short name T136
Test name
Test status
Simulation time 20961301 ps
CPU time 0.81 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:00 PM PDT 24
Peak memory 207440 kb
Host smart-40cdac82-7089-49ca-8369-7db0715e8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53201418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.53201418
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2214605070
Short name T711
Test name
Test status
Simulation time 28553034179 ps
CPU time 215.37 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:22:36 PM PDT 24
Peak memory 274064 kb
Host smart-a6b0707d-9cfb-4295-b1c4-b13435dadf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214605070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2214605070
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3496548966
Short name T725
Test name
Test status
Simulation time 30820415350 ps
CPU time 96.94 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:20:36 PM PDT 24
Peak memory 266104 kb
Host smart-f1b1d666-399c-4bae-9dfb-010b482be5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496548966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3496548966
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3845099894
Short name T350
Test name
Test status
Simulation time 167031123 ps
CPU time 5.88 seconds
Started Aug 01 05:18:58 PM PDT 24
Finished Aug 01 05:19:04 PM PDT 24
Peak memory 234684 kb
Host smart-445bf89e-bec6-41d8-945a-ace96c84fc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845099894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3845099894
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3747719308
Short name T232
Test name
Test status
Simulation time 17910886263 ps
CPU time 123.19 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:21:03 PM PDT 24
Peak memory 239824 kb
Host smart-b0df95a1-6632-4457-ae69-87bfec627740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747719308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3747719308
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1219683194
Short name T440
Test name
Test status
Simulation time 467063221 ps
CPU time 2.92 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:03 PM PDT 24
Peak memory 225128 kb
Host smart-49329bea-a28b-4609-bf1c-7d4dc676ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219683194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1219683194
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2867157110
Short name T767
Test name
Test status
Simulation time 3183463930 ps
CPU time 33.82 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 233556 kb
Host smart-8d1a482a-9e84-4316-b45e-321c534b7622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867157110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2867157110
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.868201706
Short name T568
Test name
Test status
Simulation time 34737776266 ps
CPU time 27.32 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:27 PM PDT 24
Peak memory 233396 kb
Host smart-53cecbc9-7459-4544-a115-fa3ee7e23934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868201706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.868201706
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1062509764
Short name T1014
Test name
Test status
Simulation time 2932524969 ps
CPU time 4.89 seconds
Started Aug 01 05:18:59 PM PDT 24
Finished Aug 01 05:19:04 PM PDT 24
Peak memory 225308 kb
Host smart-e0cec7eb-89e4-458f-b424-98897e824f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062509764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1062509764
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1190956120
Short name T687
Test name
Test status
Simulation time 154785515 ps
CPU time 4.25 seconds
Started Aug 01 05:19:02 PM PDT 24
Finished Aug 01 05:19:06 PM PDT 24
Peak memory 222460 kb
Host smart-1da74188-e03e-41c6-9eb8-1a73d55cf809
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1190956120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1190956120
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.210544133
Short name T161
Test name
Test status
Simulation time 167631718 ps
CPU time 0.96 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 206988 kb
Host smart-156e7f65-54ab-47a1-b68c-5b1f26902621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210544133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.210544133
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3179253278
Short name T910
Test name
Test status
Simulation time 7159617256 ps
CPU time 10.22 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:19:12 PM PDT 24
Peak memory 217272 kb
Host smart-a86fcaf1-6c19-4b17-b324-866fe7acf896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179253278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3179253278
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2433639777
Short name T341
Test name
Test status
Simulation time 28731422 ps
CPU time 1.09 seconds
Started Aug 01 05:18:58 PM PDT 24
Finished Aug 01 05:18:59 PM PDT 24
Peak memory 208044 kb
Host smart-5a182fdd-583c-44b7-897d-15fa1c804be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433639777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2433639777
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.948735689
Short name T477
Test name
Test status
Simulation time 40460538 ps
CPU time 0.7 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:19:02 PM PDT 24
Peak memory 206092 kb
Host smart-9f65d1b6-c83a-41c4-8bc4-e50b95b9a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948735689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.948735689
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4049456951
Short name T250
Test name
Test status
Simulation time 450893039 ps
CPU time 5.56 seconds
Started Aug 01 05:19:03 PM PDT 24
Finished Aug 01 05:19:08 PM PDT 24
Peak memory 241496 kb
Host smart-ab6baec4-a0f6-41a1-8b9a-d766902946f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049456951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4049456951
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.420067295
Short name T335
Test name
Test status
Simulation time 39498101 ps
CPU time 0.72 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:11 PM PDT 24
Peak memory 205736 kb
Host smart-85a89182-5c5c-4fe6-81f5-24e58874414d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420067295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.420067295
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2285667781
Short name T13
Test name
Test status
Simulation time 2155218342 ps
CPU time 7.57 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:18 PM PDT 24
Peak memory 233436 kb
Host smart-8256ca9c-ad17-4a98-bac3-04d4b36fa397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285667781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2285667781
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3601559873
Short name T579
Test name
Test status
Simulation time 54150926 ps
CPU time 0.75 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:01 PM PDT 24
Peak memory 206340 kb
Host smart-c3af83ee-d1f7-443e-b77c-39b282bb8194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601559873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3601559873
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4292936835
Short name T6
Test name
Test status
Simulation time 38453614 ps
CPU time 0.74 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:11 PM PDT 24
Peak memory 216348 kb
Host smart-14345553-6742-4292-b80b-7a1464f27602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292936835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4292936835
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2683306698
Short name T47
Test name
Test status
Simulation time 2402856818 ps
CPU time 56.43 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 249988 kb
Host smart-6eff1b85-bf93-4ed9-9abf-54da8158a4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683306698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2683306698
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2466208159
Short name T321
Test name
Test status
Simulation time 1590183433 ps
CPU time 24.94 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 241604 kb
Host smart-c3ac15fa-0eac-4c32-8e0e-ffecfe8c054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466208159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2466208159
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.269688257
Short name T653
Test name
Test status
Simulation time 273779353 ps
CPU time 7.37 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:18 PM PDT 24
Peak memory 241644 kb
Host smart-c62d5c09-5b86-4047-b20b-efa2dcc05dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269688257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.269688257
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3819767113
Short name T247
Test name
Test status
Simulation time 14021212512 ps
CPU time 34.51 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 249812 kb
Host smart-3aa23ef9-932a-42f1-94b2-6ab5aa825e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819767113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3819767113
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1783077974
Short name T831
Test name
Test status
Simulation time 342719508 ps
CPU time 5.01 seconds
Started Aug 01 05:19:03 PM PDT 24
Finished Aug 01 05:19:08 PM PDT 24
Peak memory 225212 kb
Host smart-9fd0128a-996c-473f-bca9-dd80e9ca054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783077974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1783077974
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3848174163
Short name T963
Test name
Test status
Simulation time 1330908655 ps
CPU time 11.43 seconds
Started Aug 01 05:19:11 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 225220 kb
Host smart-182718dc-c3d4-4e70-ab22-0027452cacee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848174163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3848174163
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1150168433
Short name T554
Test name
Test status
Simulation time 18416511091 ps
CPU time 22.77 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 233500 kb
Host smart-b122e0be-3d59-45d1-8c2f-19fb991e064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150168433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1150168433
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.485602857
Short name T847
Test name
Test status
Simulation time 272556697 ps
CPU time 3.65 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:04 PM PDT 24
Peak memory 225068 kb
Host smart-56ff5388-76a4-4132-8425-c6bf864fd695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485602857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.485602857
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.301761790
Short name T149
Test name
Test status
Simulation time 1267790376 ps
CPU time 5.55 seconds
Started Aug 01 05:19:11 PM PDT 24
Finished Aug 01 05:19:17 PM PDT 24
Peak memory 222184 kb
Host smart-38c1b298-a900-4bbe-9447-138df2ce3b40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=301761790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.301761790
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1497487990
Short name T511
Test name
Test status
Simulation time 31105546999 ps
CPU time 40.52 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:49 PM PDT 24
Peak memory 218392 kb
Host smart-bbb57de8-3108-44fa-84fd-28ed051cf618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497487990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1497487990
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1909436071
Short name T694
Test name
Test status
Simulation time 9670498772 ps
CPU time 22.91 seconds
Started Aug 01 05:19:02 PM PDT 24
Finished Aug 01 05:19:25 PM PDT 24
Peak memory 217020 kb
Host smart-9c599307-8448-4aee-b9b8-214daa662677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909436071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1909436071
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.399263202
Short name T984
Test name
Test status
Simulation time 728400333 ps
CPU time 6.03 seconds
Started Aug 01 05:19:01 PM PDT 24
Finished Aug 01 05:19:08 PM PDT 24
Peak memory 216856 kb
Host smart-8528decd-4192-4d8b-aadb-73a2538d557d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399263202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.399263202
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4009663986
Short name T337
Test name
Test status
Simulation time 109685813 ps
CPU time 0.9 seconds
Started Aug 01 05:19:00 PM PDT 24
Finished Aug 01 05:19:01 PM PDT 24
Peak memory 208440 kb
Host smart-693bd429-01a5-48b3-ae96-56e80c3f5730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009663986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4009663986
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2729451639
Short name T1006
Test name
Test status
Simulation time 24271975 ps
CPU time 0.73 seconds
Started Aug 01 05:19:03 PM PDT 24
Finished Aug 01 05:19:04 PM PDT 24
Peak memory 206500 kb
Host smart-54765690-5de9-41c7-a1c3-c929975828e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729451639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2729451639
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.593827235
Short name T676
Test name
Test status
Simulation time 263521863 ps
CPU time 5.66 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:15 PM PDT 24
Peak memory 241504 kb
Host smart-f0063d40-5bf7-4a17-9597-8243214279cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593827235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.593827235
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2530128681
Short name T406
Test name
Test status
Simulation time 19580280 ps
CPU time 0.76 seconds
Started Aug 01 05:19:12 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 205772 kb
Host smart-fc3460df-18e2-4e1b-89cc-e6bb3b90c22d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530128681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2530128681
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1853009885
Short name T530
Test name
Test status
Simulation time 649659451 ps
CPU time 3.49 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 233376 kb
Host smart-2b2f1e6d-741c-4f3a-8042-d25c2a2d83c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853009885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1853009885
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.244147533
Short name T802
Test name
Test status
Simulation time 58450527 ps
CPU time 0.77 seconds
Started Aug 01 05:19:14 PM PDT 24
Finished Aug 01 05:19:14 PM PDT 24
Peak memory 205940 kb
Host smart-c5bc9999-270d-4628-832a-533b2dc1865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244147533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.244147533
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.517300005
Short name T242
Test name
Test status
Simulation time 2948526148 ps
CPU time 39.19 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:48 PM PDT 24
Peak memory 253052 kb
Host smart-c1a62ef5-f49e-4a9a-990c-d84ef7bcda34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517300005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.517300005
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2687881344
Short name T237
Test name
Test status
Simulation time 231552493097 ps
CPU time 218.1 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:22:48 PM PDT 24
Peak memory 257452 kb
Host smart-f1e337ce-2dde-4894-9b69-005cf4ebd1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687881344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2687881344
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2447465839
Short name T234
Test name
Test status
Simulation time 49597094651 ps
CPU time 149.14 seconds
Started Aug 01 05:19:11 PM PDT 24
Finished Aug 01 05:21:40 PM PDT 24
Peak memory 251704 kb
Host smart-b7875009-4a02-4e35-9ed3-d8f7c36542aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447465839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2447465839
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2772206762
Short name T451
Test name
Test status
Simulation time 218618424 ps
CPU time 2.58 seconds
Started Aug 01 05:19:07 PM PDT 24
Finished Aug 01 05:19:10 PM PDT 24
Peak memory 233428 kb
Host smart-18310478-dc9f-4d58-9f39-568d14c34035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772206762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2772206762
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.4015472447
Short name T600
Test name
Test status
Simulation time 13938576 ps
CPU time 0.75 seconds
Started Aug 01 05:19:08 PM PDT 24
Finished Aug 01 05:19:09 PM PDT 24
Peak memory 216312 kb
Host smart-85e93a69-c9f0-4af0-ab8f-086a5ee6a9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015472447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.4015472447
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2244530269
Short name T915
Test name
Test status
Simulation time 1262384103 ps
CPU time 13.76 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:24 PM PDT 24
Peak memory 233308 kb
Host smart-4d1b0432-a4de-4ca2-a413-56ac68e21ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244530269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2244530269
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1303888836
Short name T469
Test name
Test status
Simulation time 13838956549 ps
CPU time 39.09 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:49 PM PDT 24
Peak memory 233552 kb
Host smart-7cb1e569-2510-4ead-9521-e511990882af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303888836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1303888836
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1816776822
Short name T851
Test name
Test status
Simulation time 244362798 ps
CPU time 5.54 seconds
Started Aug 01 05:19:08 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 233404 kb
Host smart-a2ef899d-910a-4104-917d-e6fcb1f3f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816776822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1816776822
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3052643040
Short name T368
Test name
Test status
Simulation time 107374851 ps
CPU time 2.06 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:11 PM PDT 24
Peak memory 224792 kb
Host smart-1670b2ee-6f7c-49be-8bbf-5a5854d1908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052643040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3052643040
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2894111908
Short name T72
Test name
Test status
Simulation time 998070197 ps
CPU time 10.6 seconds
Started Aug 01 05:19:11 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 221176 kb
Host smart-fb1e678c-536e-4913-bfef-9563973408bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2894111908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2894111908
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4256704464
Short name T22
Test name
Test status
Simulation time 229470168301 ps
CPU time 315.89 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:24:26 PM PDT 24
Peak memory 256808 kb
Host smart-2d354821-9cb9-4a03-b6a9-69aaa18055a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256704464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4256704464
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.825756038
Short name T576
Test name
Test status
Simulation time 401048647 ps
CPU time 4.71 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:14 PM PDT 24
Peak memory 217008 kb
Host smart-d00b001d-0b31-4950-bf36-28d335b55401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825756038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.825756038
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3986161158
Short name T818
Test name
Test status
Simulation time 11831895 ps
CPU time 0.7 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:10 PM PDT 24
Peak memory 206180 kb
Host smart-a95cbf16-5628-488a-9fb9-6fa53a529c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986161158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3986161158
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4177228970
Short name T358
Test name
Test status
Simulation time 234151452 ps
CPU time 1.3 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:10 PM PDT 24
Peak memory 216856 kb
Host smart-6689b174-19bb-4953-ae9b-b6e48e3f8cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177228970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4177228970
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1026395380
Short name T398
Test name
Test status
Simulation time 90984073 ps
CPU time 0.89 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:10 PM PDT 24
Peak memory 206808 kb
Host smart-5d3609b2-f5ed-4453-a3a4-08b26b6f464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026395380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1026395380
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2132127903
Short name T444
Test name
Test status
Simulation time 3088714602 ps
CPU time 9.13 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:19:18 PM PDT 24
Peak memory 233468 kb
Host smart-60417380-34a3-44f3-bf18-29ab0f31c0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132127903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2132127903
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2323274140
Short name T689
Test name
Test status
Simulation time 24323943 ps
CPU time 0.72 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:21 PM PDT 24
Peak memory 205680 kb
Host smart-2f3ae303-d712-4599-8a0a-08a403e58ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323274140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2323274140
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2966051486
Short name T397
Test name
Test status
Simulation time 36735567 ps
CPU time 2.18 seconds
Started Aug 01 05:19:11 PM PDT 24
Finished Aug 01 05:19:14 PM PDT 24
Peak memory 225268 kb
Host smart-9ac8ee3e-fa9a-4b3d-bbd3-2f646db5c4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966051486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2966051486
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2035272717
Short name T138
Test name
Test status
Simulation time 54204062 ps
CPU time 0.75 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:11 PM PDT 24
Peak memory 206036 kb
Host smart-13f6067d-7a12-4464-a385-9e013a88fa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035272717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2035272717
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1201501895
Short name T290
Test name
Test status
Simulation time 186066875853 ps
CPU time 150.53 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 257348 kb
Host smart-cb91845e-6f12-48b9-a501-cba76633acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201501895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1201501895
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2563935107
Short name T536
Test name
Test status
Simulation time 111385530540 ps
CPU time 276.82 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:23:56 PM PDT 24
Peak memory 252060 kb
Host smart-948a7191-23c9-425b-a3b6-42d5a243bfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563935107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2563935107
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2291380145
Short name T657
Test name
Test status
Simulation time 131148628000 ps
CPU time 306.42 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:24:26 PM PDT 24
Peak memory 257304 kb
Host smart-973c37ea-4b4e-472e-a428-e9451897cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291380145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2291380145
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2580189119
Short name T153
Test name
Test status
Simulation time 149439957 ps
CPU time 6.56 seconds
Started Aug 01 05:19:12 PM PDT 24
Finished Aug 01 05:19:18 PM PDT 24
Peak memory 240244 kb
Host smart-31bd8262-66ee-45e3-b077-18b2c5de31b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580189119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2580189119
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1392718650
Short name T283
Test name
Test status
Simulation time 4681080928 ps
CPU time 55.55 seconds
Started Aug 01 05:19:09 PM PDT 24
Finished Aug 01 05:20:05 PM PDT 24
Peak memory 252924 kb
Host smart-96c9b685-f386-4760-9541-423b3011cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392718650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1392718650
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.905675162
Short name T1000
Test name
Test status
Simulation time 31692704 ps
CPU time 2.1 seconds
Started Aug 01 05:19:11 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 224308 kb
Host smart-2484f9bd-9fcf-4664-bf88-ca9830f64481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905675162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.905675162
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.877405108
Short name T455
Test name
Test status
Simulation time 22295070849 ps
CPU time 24.98 seconds
Started Aug 01 05:19:14 PM PDT 24
Finished Aug 01 05:19:39 PM PDT 24
Peak memory 233420 kb
Host smart-9fd050c0-151c-48ae-bb60-1b0ca20b298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877405108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.877405108
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1720483772
Short name T42
Test name
Test status
Simulation time 7288249195 ps
CPU time 21.26 seconds
Started Aug 01 05:19:12 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 241120 kb
Host smart-9604265c-f4e4-4ae2-8502-5f3b2dbc982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720483772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1720483772
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1928604449
Short name T871
Test name
Test status
Simulation time 471268662 ps
CPU time 4.14 seconds
Started Aug 01 05:19:14 PM PDT 24
Finished Aug 01 05:19:18 PM PDT 24
Peak memory 225168 kb
Host smart-97554609-1cfb-4754-9a80-150b4b9677de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928604449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1928604449
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.229291810
Short name T704
Test name
Test status
Simulation time 74603597 ps
CPU time 3.59 seconds
Started Aug 01 05:19:11 PM PDT 24
Finished Aug 01 05:19:15 PM PDT 24
Peak memory 219816 kb
Host smart-afa86fc6-22ec-4282-aa06-380f07e66f23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=229291810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.229291810
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4007207439
Short name T792
Test name
Test status
Simulation time 4760200074 ps
CPU time 26.42 seconds
Started Aug 01 05:19:13 PM PDT 24
Finished Aug 01 05:19:39 PM PDT 24
Peak memory 216976 kb
Host smart-41e822f2-23ec-48fb-8107-19a9cc760810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007207439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4007207439
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2304353420
Short name T846
Test name
Test status
Simulation time 4225235949 ps
CPU time 10.64 seconds
Started Aug 01 05:19:12 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 216992 kb
Host smart-46efee5c-7f01-4ebf-8b31-8fbe1a4912a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304353420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2304353420
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2446935398
Short name T410
Test name
Test status
Simulation time 26286104 ps
CPU time 1.03 seconds
Started Aug 01 05:19:10 PM PDT 24
Finished Aug 01 05:19:12 PM PDT 24
Peak memory 207904 kb
Host smart-6ee95134-673d-415e-84a6-50d044262901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446935398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2446935398
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4215134156
Short name T541
Test name
Test status
Simulation time 97916503 ps
CPU time 0.86 seconds
Started Aug 01 05:19:12 PM PDT 24
Finished Aug 01 05:19:13 PM PDT 24
Peak memory 206476 kb
Host smart-db8259a6-8fed-483c-8f7a-5a57081fabf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215134156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4215134156
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1084608647
Short name T432
Test name
Test status
Simulation time 8618940420 ps
CPU time 10.41 seconds
Started Aug 01 05:19:12 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 233356 kb
Host smart-b122b221-42e4-42ff-9fde-74cb86da3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084608647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1084608647
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3690411979
Short name T464
Test name
Test status
Simulation time 44449805 ps
CPU time 0.76 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:19:20 PM PDT 24
Peak memory 205872 kb
Host smart-49c65b23-7d4c-4f11-a04c-f49eb6e6ea1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690411979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3690411979
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.345763268
Short name T108
Test name
Test status
Simulation time 483676117 ps
CPU time 2.31 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:19:21 PM PDT 24
Peak memory 225080 kb
Host smart-6216d082-37a6-44d2-92a7-e16f8dd52ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345763268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.345763268
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.99588045
Short name T670
Test name
Test status
Simulation time 33472727 ps
CPU time 0.77 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 206996 kb
Host smart-32512bde-91b8-4f21-bf5c-6fb2b251950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99588045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.99588045
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3856848578
Short name T979
Test name
Test status
Simulation time 6846150418 ps
CPU time 109.94 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:21:09 PM PDT 24
Peak memory 257508 kb
Host smart-c1594738-f313-4d81-bd33-4e39dbcd8607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856848578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3856848578
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.776664431
Short name T316
Test name
Test status
Simulation time 2875769372 ps
CPU time 8.43 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:19:27 PM PDT 24
Peak memory 218156 kb
Host smart-ef09a79f-31ec-49e3-a9b2-f5bf6f94e340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776664431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.776664431
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.19757860
Short name T730
Test name
Test status
Simulation time 325767468 ps
CPU time 3.85 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:24 PM PDT 24
Peak memory 233464 kb
Host smart-9c4f051e-cb85-4e05-aecf-a0a79a387510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19757860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.19757860
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.362587407
Short name T933
Test name
Test status
Simulation time 20328071625 ps
CPU time 89.18 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:20:50 PM PDT 24
Peak memory 241640 kb
Host smart-ecb1c07b-49be-4cfc-8347-1e42be2c1c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362587407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.362587407
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1867796886
Short name T800
Test name
Test status
Simulation time 218043981 ps
CPU time 3.3 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 225132 kb
Host smart-7001aae0-1c3f-4dcc-b549-538411872b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867796886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1867796886
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2322019268
Short name T332
Test name
Test status
Simulation time 19248621173 ps
CPU time 40.34 seconds
Started Aug 01 05:19:18 PM PDT 24
Finished Aug 01 05:19:58 PM PDT 24
Peak memory 233408 kb
Host smart-91cfd4c0-e306-456c-99c2-f92e79cb5e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322019268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2322019268
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1658244459
Short name T296
Test name
Test status
Simulation time 484676672 ps
CPU time 6.39 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:19:26 PM PDT 24
Peak memory 233440 kb
Host smart-b25fffe1-182c-46f3-a949-6eacaeae508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658244459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1658244459
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3746381841
Short name T543
Test name
Test status
Simulation time 1614840007 ps
CPU time 6.35 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:19:26 PM PDT 24
Peak memory 233408 kb
Host smart-e36ad7f4-a946-4c0c-b8e7-e593fc40db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746381841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3746381841
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2791155061
Short name T731
Test name
Test status
Simulation time 615121243 ps
CPU time 6.39 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:26 PM PDT 24
Peak memory 222748 kb
Host smart-442c2c3e-5374-4865-b31f-c8a255a623b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2791155061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2791155061
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1449916724
Short name T19
Test name
Test status
Simulation time 10013501704 ps
CPU time 25.4 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 218300 kb
Host smart-ff04d5c4-a0f4-45fa-bc70-5fc8f78c28e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449916724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1449916724
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.773105699
Short name T772
Test name
Test status
Simulation time 3012477581 ps
CPU time 7.1 seconds
Started Aug 01 05:19:18 PM PDT 24
Finished Aug 01 05:19:25 PM PDT 24
Peak memory 217124 kb
Host smart-382c10cd-b2b1-4615-9fd0-eed69ceec706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773105699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.773105699
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1308362947
Short name T608
Test name
Test status
Simulation time 3643399074 ps
CPU time 2.74 seconds
Started Aug 01 05:19:18 PM PDT 24
Finished Aug 01 05:19:21 PM PDT 24
Peak memory 216704 kb
Host smart-34c729a6-fd14-407d-8607-6fe4f7837550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308362947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1308362947
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4083576856
Short name T596
Test name
Test status
Simulation time 121831773 ps
CPU time 1.15 seconds
Started Aug 01 05:19:18 PM PDT 24
Finished Aug 01 05:19:19 PM PDT 24
Peak memory 216988 kb
Host smart-232d4882-162c-481e-a22f-165f248ea221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083576856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4083576856
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3811710709
Short name T599
Test name
Test status
Simulation time 14648778 ps
CPU time 0.7 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:21 PM PDT 24
Peak memory 206484 kb
Host smart-a9b011f5-0c0e-44ac-8eea-5c3c25946e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811710709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3811710709
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2649428669
Short name T402
Test name
Test status
Simulation time 369972388 ps
CPU time 8.7 seconds
Started Aug 01 05:19:17 PM PDT 24
Finished Aug 01 05:19:26 PM PDT 24
Peak memory 233380 kb
Host smart-0484a0e3-e6f3-40c1-88d1-30c7e29b8adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649428669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2649428669
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4093150801
Short name T558
Test name
Test status
Simulation time 11923918 ps
CPU time 0.7 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:15:57 PM PDT 24
Peak memory 205748 kb
Host smart-f9930353-0f6f-4f27-a3ae-8a1d1e764c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093150801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
093150801
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.893875263
Short name T485
Test name
Test status
Simulation time 96344319 ps
CPU time 1.96 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:03 PM PDT 24
Peak memory 224476 kb
Host smart-d1c70dd5-09ee-455d-a85d-149dac7a81c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893875263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.893875263
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2458115566
Short name T770
Test name
Test status
Simulation time 47144387 ps
CPU time 0.75 seconds
Started Aug 01 05:15:45 PM PDT 24
Finished Aug 01 05:15:46 PM PDT 24
Peak memory 205932 kb
Host smart-a8ddb136-28e5-474c-874d-3aa32f3ebef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458115566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2458115566
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4266130229
Short name T58
Test name
Test status
Simulation time 9013985172 ps
CPU time 29.26 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:29 PM PDT 24
Peak memory 241520 kb
Host smart-7cc40663-d02b-411a-a3e3-ceed6e6665e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266130229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4266130229
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.236024296
Short name T139
Test name
Test status
Simulation time 2826887529 ps
CPU time 58.58 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:57 PM PDT 24
Peak memory 249792 kb
Host smart-54302811-de93-4add-a19f-bc5c49890c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236024296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.236024296
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4233383490
Short name T195
Test name
Test status
Simulation time 39962089095 ps
CPU time 388.42 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 266396 kb
Host smart-a4a6eae0-d03b-4b12-b405-9e004802bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233383490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4233383490
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1870872018
Short name T373
Test name
Test status
Simulation time 639394517 ps
CPU time 7.11 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:16:07 PM PDT 24
Peak memory 225280 kb
Host smart-cbeef096-b561-4f67-a155-963e5792aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870872018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1870872018
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1366836386
Short name T690
Test name
Test status
Simulation time 27913709488 ps
CPU time 196.95 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:19:14 PM PDT 24
Peak memory 254356 kb
Host smart-3e37e4ce-3721-48a6-bff9-229a44908a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366836386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1366836386
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1953449606
Short name T738
Test name
Test status
Simulation time 2095662721 ps
CPU time 6.16 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:06 PM PDT 24
Peak memory 233388 kb
Host smart-67c6e1ff-bca0-47fb-ba6a-3beab6b08e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953449606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1953449606
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2838497388
Short name T975
Test name
Test status
Simulation time 206742617 ps
CPU time 7.5 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:06 PM PDT 24
Peak memory 240496 kb
Host smart-1b83327a-edcd-4d10-bd72-f997fbad631a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838497388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2838497388
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2814047670
Short name T954
Test name
Test status
Simulation time 26793558 ps
CPU time 1.03 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:00 PM PDT 24
Peak memory 217112 kb
Host smart-c1c68701-940f-4303-9b81-167d1a726440
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814047670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2814047670
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3390150229
Short name T911
Test name
Test status
Simulation time 785289406 ps
CPU time 3.03 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:02 PM PDT 24
Peak memory 225120 kb
Host smart-16c58682-6efd-4ed9-96dc-67c5154bd52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390150229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3390150229
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1040618880
Short name T261
Test name
Test status
Simulation time 18626049718 ps
CPU time 24.14 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:16:21 PM PDT 24
Peak memory 233512 kb
Host smart-a6700b08-3fcc-4c23-9d36-8f4fef167414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040618880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1040618880
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3414687727
Short name T417
Test name
Test status
Simulation time 4051705047 ps
CPU time 6.39 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:16:04 PM PDT 24
Peak memory 223776 kb
Host smart-6d33519e-0272-4c9c-9c3c-0c57818075b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3414687727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3414687727
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.270191958
Short name T909
Test name
Test status
Simulation time 14332806991 ps
CPU time 86.06 seconds
Started Aug 01 05:16:03 PM PDT 24
Finished Aug 01 05:17:29 PM PDT 24
Peak memory 266172 kb
Host smart-a6650171-d012-4596-b858-9034153fcd77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270191958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.270191958
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3078358146
Short name T315
Test name
Test status
Simulation time 5967258916 ps
CPU time 14.02 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:16 PM PDT 24
Peak memory 217188 kb
Host smart-0cae896a-ea15-43db-8510-6738e0d4a36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078358146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3078358146
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2510954993
Short name T348
Test name
Test status
Simulation time 1081587858 ps
CPU time 4.06 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:16:04 PM PDT 24
Peak memory 216792 kb
Host smart-bd65dc3a-965f-4a34-a5bd-bc9012f6b047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510954993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2510954993
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.929030920
Short name T605
Test name
Test status
Simulation time 343490651 ps
CPU time 1.8 seconds
Started Aug 01 05:15:55 PM PDT 24
Finished Aug 01 05:15:57 PM PDT 24
Peak memory 216880 kb
Host smart-152ddb8c-f392-45e8-9d58-588f4537dc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929030920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.929030920
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3477404249
Short name T141
Test name
Test status
Simulation time 50244244 ps
CPU time 0.75 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 206472 kb
Host smart-9ca7f487-e638-4f5a-aa7a-0f1c442d3a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477404249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3477404249
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2477829658
Short name T796
Test name
Test status
Simulation time 664855103 ps
CPU time 12.27 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:11 PM PDT 24
Peak memory 249524 kb
Host smart-bec96ace-97a4-4f2a-b6fb-49495fd9ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477829658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2477829658
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3641468816
Short name T591
Test name
Test status
Simulation time 27559186 ps
CPU time 0.74 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:16:01 PM PDT 24
Peak memory 206056 kb
Host smart-cb0d1a20-b706-4cde-9732-8be60808767b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641468816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
641468816
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.141062002
Short name T388
Test name
Test status
Simulation time 92191059 ps
CPU time 2.05 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:15:59 PM PDT 24
Peak memory 224792 kb
Host smart-88e6944d-28e4-41e2-88ae-6ff73d23b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141062002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.141062002
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.401695326
Short name T60
Test name
Test status
Simulation time 63615448 ps
CPU time 0.76 seconds
Started Aug 01 05:15:56 PM PDT 24
Finished Aug 01 05:15:57 PM PDT 24
Peak memory 206284 kb
Host smart-2e0a8cbc-39d2-40a5-b208-abf4d5ee63e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401695326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.401695326
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2588536164
Short name T266
Test name
Test status
Simulation time 32655085294 ps
CPU time 216.59 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:19:37 PM PDT 24
Peak memory 249816 kb
Host smart-3ec8cf2e-69f9-40a9-ba41-023d3d6d5563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588536164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2588536164
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1031403463
Short name T207
Test name
Test status
Simulation time 58661526555 ps
CPU time 526.56 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:24:44 PM PDT 24
Peak memory 258204 kb
Host smart-04071ebb-47fa-4423-a9a2-e8a317ece08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031403463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1031403463
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3194279920
Short name T293
Test name
Test status
Simulation time 239810571905 ps
CPU time 603.12 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 272736 kb
Host smart-08b874c8-beb2-4957-b3a9-d1980ff15a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194279920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3194279920
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2783539324
Short name T522
Test name
Test status
Simulation time 1648836705 ps
CPU time 8.48 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:16:05 PM PDT 24
Peak memory 233484 kb
Host smart-f1872bd2-a632-413c-a98b-7bb3a75550c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783539324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2783539324
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1340405572
Short name T885
Test name
Test status
Simulation time 5622394459 ps
CPU time 33.85 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:32 PM PDT 24
Peak memory 241044 kb
Host smart-ff0b4dd1-5a93-4355-8dcc-a4f05e0b0a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340405572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1340405572
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3987457168
Short name T671
Test name
Test status
Simulation time 192900371 ps
CPU time 2.84 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:02 PM PDT 24
Peak memory 233348 kb
Host smart-762b175f-1eaa-4fd1-b808-d5493781779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987457168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3987457168
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3500877780
Short name T881
Test name
Test status
Simulation time 1409272477 ps
CPU time 9.2 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:16:07 PM PDT 24
Peak memory 233460 kb
Host smart-5f860819-c826-4433-b3a7-5f37432b4bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500877780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3500877780
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3043582409
Short name T38
Test name
Test status
Simulation time 49159391 ps
CPU time 1.04 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 217092 kb
Host smart-c9b1c5e5-8564-48a3-89fa-f56a7ca5af63
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043582409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3043582409
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1786109811
Short name T189
Test name
Test status
Simulation time 401877947 ps
CPU time 5.76 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:05 PM PDT 24
Peak memory 241460 kb
Host smart-06eb4402-618a-4740-a96d-a16a78691cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786109811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1786109811
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4129186720
Short name T53
Test name
Test status
Simulation time 88573210 ps
CPU time 2.37 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:01 PM PDT 24
Peak memory 225080 kb
Host smart-471173e3-b221-45ec-8706-79aa3a31f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129186720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4129186720
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3210863089
Short name T426
Test name
Test status
Simulation time 8696257638 ps
CPU time 9.85 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:12 PM PDT 24
Peak memory 222800 kb
Host smart-1bdc7062-2bf8-44ee-9349-3e47d1cba35b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3210863089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3210863089
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3705078994
Short name T57
Test name
Test status
Simulation time 51928854 ps
CPU time 0.93 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:15:59 PM PDT 24
Peak memory 207052 kb
Host smart-32db801c-395e-40b4-a509-6cdbace36200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705078994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3705078994
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.98024727
Short name T784
Test name
Test status
Simulation time 6951055680 ps
CPU time 7.41 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:09 PM PDT 24
Peak memory 217048 kb
Host smart-03100d89-c4cd-4f8a-a5ad-ba1e91e9cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98024727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.98024727
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.91574805
Short name T501
Test name
Test status
Simulation time 164525659 ps
CPU time 0.98 seconds
Started Aug 01 05:16:03 PM PDT 24
Finished Aug 01 05:16:04 PM PDT 24
Peak memory 206568 kb
Host smart-0454c663-40ad-4f73-a824-ec8b9bccb9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91574805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.91574805
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.526587452
Short name T716
Test name
Test status
Simulation time 186188099 ps
CPU time 1.32 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:00 PM PDT 24
Peak memory 208744 kb
Host smart-d3d21df8-8293-4b6f-94e4-e29d8ceeb4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526587452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.526587452
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3951354957
Short name T357
Test name
Test status
Simulation time 38813539 ps
CPU time 0.71 seconds
Started Aug 01 05:15:57 PM PDT 24
Finished Aug 01 05:15:58 PM PDT 24
Peak memory 206476 kb
Host smart-d758d74b-4e94-4141-beb6-e158dc33a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951354957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3951354957
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2710219599
Short name T276
Test name
Test status
Simulation time 1206232949 ps
CPU time 7.51 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:16:06 PM PDT 24
Peak memory 233368 kb
Host smart-45d7b3c2-6c57-44b3-b1b1-4a0d229ea1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710219599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2710219599
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.965276054
Short name T378
Test name
Test status
Simulation time 41785601 ps
CPU time 0.71 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:02 PM PDT 24
Peak memory 205280 kb
Host smart-e0a9a8de-b29a-4aef-9e87-63f12afcf349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965276054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.965276054
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.676596783
Short name T707
Test name
Test status
Simulation time 621809619 ps
CPU time 3.11 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:05 PM PDT 24
Peak memory 225248 kb
Host smart-de3a1558-995c-47cc-be7d-b506ca79d600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676596783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.676596783
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1811687712
Short name T683
Test name
Test status
Simulation time 19691731 ps
CPU time 0.79 seconds
Started Aug 01 05:15:58 PM PDT 24
Finished Aug 01 05:15:59 PM PDT 24
Peak memory 207056 kb
Host smart-42840ba3-b272-4d82-a176-8938a1b50b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811687712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1811687712
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3056992388
Short name T412
Test name
Test status
Simulation time 28200694066 ps
CPU time 99.36 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:17:42 PM PDT 24
Peak memory 249992 kb
Host smart-f3654d68-b9f1-4ed4-85f6-c3ddbe00990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056992388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3056992388
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1997773451
Short name T644
Test name
Test status
Simulation time 2416727719 ps
CPU time 17.05 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:18 PM PDT 24
Peak memory 235280 kb
Host smart-6cd75f04-655f-4fae-a102-e81b3a4901c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997773451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1997773451
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2079235603
Short name T960
Test name
Test status
Simulation time 3231011009 ps
CPU time 22.16 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:23 PM PDT 24
Peak memory 225252 kb
Host smart-629f3d20-f7d7-476c-bcfa-f90a74195381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079235603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2079235603
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2053733560
Short name T946
Test name
Test status
Simulation time 3492269123 ps
CPU time 7.1 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:10 PM PDT 24
Peak memory 233496 kb
Host smart-8b4a7490-4d12-424b-a99c-aae09af747a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053733560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2053733560
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1989977501
Short name T483
Test name
Test status
Simulation time 2114395777 ps
CPU time 4.01 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:16:04 PM PDT 24
Peak memory 233396 kb
Host smart-4b7b853c-53bd-4e66-97f8-5b59e017697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989977501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1989977501
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1626184483
Short name T137
Test name
Test status
Simulation time 394009309 ps
CPU time 2.11 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:04 PM PDT 24
Peak memory 224424 kb
Host smart-4128ad76-ef18-431a-ad7e-cec69b580b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626184483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1626184483
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2935102641
Short name T24
Test name
Test status
Simulation time 14570085 ps
CPU time 1.12 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:03 PM PDT 24
Peak memory 217208 kb
Host smart-f84dd3b3-a405-4728-aab0-fc3e0e0f57c2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935102641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2935102641
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3844974399
Short name T27
Test name
Test status
Simulation time 2109596162 ps
CPU time 6.36 seconds
Started Aug 01 05:16:03 PM PDT 24
Finished Aug 01 05:16:09 PM PDT 24
Peak memory 225124 kb
Host smart-b435eeea-534a-47aa-9dac-e7d57d03d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844974399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3844974399
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.265275666
Short name T430
Test name
Test status
Simulation time 367800759 ps
CPU time 4.28 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:05 PM PDT 24
Peak memory 225240 kb
Host smart-77c3db29-b6b9-4090-b782-537b228a0695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265275666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.265275666
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2573083610
Short name T609
Test name
Test status
Simulation time 4316188108 ps
CPU time 6.87 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:10 PM PDT 24
Peak memory 220520 kb
Host smart-7d506824-a9ac-4328-8ef7-e75d32c6a914
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2573083610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2573083610
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.965988456
Short name T781
Test name
Test status
Simulation time 89815508 ps
CPU time 1.07 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:02 PM PDT 24
Peak memory 207220 kb
Host smart-353ec16b-603f-457c-8791-7b95540dae4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965988456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.965988456
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2874766968
Short name T924
Test name
Test status
Simulation time 8528016871 ps
CPU time 42.87 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:42 PM PDT 24
Peak memory 217000 kb
Host smart-521d912b-f23a-4c03-9035-305a4f1653bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874766968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2874766968
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2996772071
Short name T645
Test name
Test status
Simulation time 541954205 ps
CPU time 2.59 seconds
Started Aug 01 05:16:03 PM PDT 24
Finished Aug 01 05:16:05 PM PDT 24
Peak memory 208500 kb
Host smart-d65c34f5-e641-42a2-97de-eed30eea9568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996772071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2996772071
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.70913338
Short name T673
Test name
Test status
Simulation time 24059101 ps
CPU time 1.28 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:16:01 PM PDT 24
Peak memory 216908 kb
Host smart-fadf43a9-056b-4116-a522-c54de552160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70913338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.70913338
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1261320484
Short name T598
Test name
Test status
Simulation time 162294470 ps
CPU time 0.91 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:00 PM PDT 24
Peak memory 207460 kb
Host smart-b1afb826-2456-4f2c-9912-d80665f75d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261320484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1261320484
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1151249886
Short name T595
Test name
Test status
Simulation time 119395647731 ps
CPU time 21.22 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:24 PM PDT 24
Peak memory 233556 kb
Host smart-281b9db1-88e6-4e30-9fd0-da833a439da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151249886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1151249886
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2506305423
Short name T763
Test name
Test status
Simulation time 13373186 ps
CPU time 0.74 seconds
Started Aug 01 05:16:15 PM PDT 24
Finished Aug 01 05:16:16 PM PDT 24
Peak memory 205756 kb
Host smart-a811610a-3f67-4e76-b9ca-aa2e201d8926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506305423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
506305423
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3068711873
Short name T901
Test name
Test status
Simulation time 1473339251 ps
CPU time 5.12 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:07 PM PDT 24
Peak memory 225200 kb
Host smart-183c635e-9b8a-4388-89af-1f799128e71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068711873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3068711873
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.326984003
Short name T75
Test name
Test status
Simulation time 61755670 ps
CPU time 0.77 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:03 PM PDT 24
Peak memory 207068 kb
Host smart-2daab919-f736-4c13-a6c8-31e9d92a2e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326984003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.326984003
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2409988196
Short name T941
Test name
Test status
Simulation time 8576723606 ps
CPU time 61.65 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:17:03 PM PDT 24
Peak memory 249988 kb
Host smart-30bdbd2d-75eb-4e15-9db0-1cba534d1d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409988196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2409988196
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.962093870
Short name T292
Test name
Test status
Simulation time 61652631686 ps
CPU time 455.25 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:23:35 PM PDT 24
Peak memory 267240 kb
Host smart-82c62924-28f2-4b40-bbbe-ba134c0c6ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962093870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.962093870
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2163386488
Short name T435
Test name
Test status
Simulation time 41712735378 ps
CPU time 162.93 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:18:43 PM PDT 24
Peak memory 239136 kb
Host smart-51353726-0727-416f-a1ee-fdfa903e8325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163386488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2163386488
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.273344483
Short name T956
Test name
Test status
Simulation time 6849810017 ps
CPU time 29.68 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:32 PM PDT 24
Peak memory 233488 kb
Host smart-29576393-7524-41ae-879e-87640de0cbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273344483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.273344483
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3275610845
Short name T90
Test name
Test status
Simulation time 11539814783 ps
CPU time 96.82 seconds
Started Aug 01 05:16:04 PM PDT 24
Finished Aug 01 05:17:40 PM PDT 24
Peak memory 249888 kb
Host smart-f33baa74-fd88-49ef-a463-af0e46a45b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275610845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3275610845
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3378169807
Short name T618
Test name
Test status
Simulation time 5116615632 ps
CPU time 8.75 seconds
Started Aug 01 05:16:07 PM PDT 24
Finished Aug 01 05:16:15 PM PDT 24
Peak memory 233460 kb
Host smart-cab27cd2-fe73-4bd7-b82b-157f5fd0df3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378169807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3378169807
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.258279505
Short name T586
Test name
Test status
Simulation time 44247900601 ps
CPU time 93.39 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:17:36 PM PDT 24
Peak memory 238736 kb
Host smart-508839d7-8964-4e00-ad14-f49be71d2bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258279505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.258279505
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1105488377
Short name T381
Test name
Test status
Simulation time 17383799 ps
CPU time 1.05 seconds
Started Aug 01 05:16:00 PM PDT 24
Finished Aug 01 05:16:01 PM PDT 24
Peak memory 217184 kb
Host smart-73ff95b0-44b2-4aa5-b8dc-d5a1c293e7c2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105488377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1105488377
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.871782713
Short name T262
Test name
Test status
Simulation time 2067717954 ps
CPU time 9.08 seconds
Started Aug 01 05:16:03 PM PDT 24
Finished Aug 01 05:16:12 PM PDT 24
Peak memory 233392 kb
Host smart-7dde62da-c770-451a-a8a0-dc1f18644414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871782713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
871782713
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2210749586
Short name T206
Test name
Test status
Simulation time 1472708847 ps
CPU time 4.03 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:07 PM PDT 24
Peak memory 225176 kb
Host smart-b53e3fb9-3878-4520-beed-90f8067f8c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210749586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2210749586
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1615635256
Short name T52
Test name
Test status
Simulation time 322741710 ps
CPU time 3.72 seconds
Started Aug 01 05:16:01 PM PDT 24
Finished Aug 01 05:16:04 PM PDT 24
Peak memory 219840 kb
Host smart-8661f9ef-1210-4949-b933-d612b1028563
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1615635256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1615635256
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1379474968
Short name T729
Test name
Test status
Simulation time 1292872293 ps
CPU time 7.1 seconds
Started Aug 01 05:16:03 PM PDT 24
Finished Aug 01 05:16:10 PM PDT 24
Peak memory 216944 kb
Host smart-568a08c8-9c3d-467d-93df-1561337e0c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379474968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1379474968
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.325196610
Short name T556
Test name
Test status
Simulation time 7497142831 ps
CPU time 20.98 seconds
Started Aug 01 05:16:02 PM PDT 24
Finished Aug 01 05:16:23 PM PDT 24
Peak memory 216964 kb
Host smart-941be955-7f17-452b-81a4-e55edd165516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325196610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.325196610
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1529903290
Short name T77
Test name
Test status
Simulation time 36747185 ps
CPU time 0.8 seconds
Started Aug 01 05:15:59 PM PDT 24
Finished Aug 01 05:16:00 PM PDT 24
Peak memory 207076 kb
Host smart-488b4ff7-608a-4eaf-aab4-a19ea0a8d027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529903290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1529903290
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3983357850
Short name T443
Test name
Test status
Simulation time 237268072 ps
CPU time 0.87 seconds
Started Aug 01 05:16:04 PM PDT 24
Finished Aug 01 05:16:05 PM PDT 24
Peak memory 206524 kb
Host smart-9ae2654d-c2b4-4209-9261-4dafe9b4b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983357850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3983357850
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2511149781
Short name T184
Test name
Test status
Simulation time 260180891 ps
CPU time 5.32 seconds
Started Aug 01 05:16:05 PM PDT 24
Finished Aug 01 05:16:10 PM PDT 24
Peak memory 233420 kb
Host smart-1712f8a3-ec2b-4b14-a1a1-6233e364f318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511149781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2511149781
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3092436766
Short name T62
Test name
Test status
Simulation time 13252210 ps
CPU time 0.74 seconds
Started Aug 01 05:16:11 PM PDT 24
Finished Aug 01 05:16:11 PM PDT 24
Peak memory 205280 kb
Host smart-7db1b8aa-310d-44ea-8411-045b076269cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092436766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
092436766
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2475959005
Short name T938
Test name
Test status
Simulation time 295382740 ps
CPU time 3.97 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:16:20 PM PDT 24
Peak memory 225164 kb
Host smart-cba61501-66d6-475a-b8c6-067adab84721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475959005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2475959005
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3580585292
Short name T569
Test name
Test status
Simulation time 30489883 ps
CPU time 0.77 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:16:17 PM PDT 24
Peak memory 206284 kb
Host smart-878bd490-7243-4500-bbbb-0907050d9f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580585292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3580585292
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3000755906
Short name T302
Test name
Test status
Simulation time 82401448369 ps
CPU time 137.47 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:18:36 PM PDT 24
Peak memory 253796 kb
Host smart-e33c3c9e-80ee-417f-8e9d-0c02e518bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000755906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3000755906
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2366989030
Short name T46
Test name
Test status
Simulation time 108842544271 ps
CPU time 148.34 seconds
Started Aug 01 05:16:09 PM PDT 24
Finished Aug 01 05:18:38 PM PDT 24
Peak memory 249872 kb
Host smart-e69655ea-1fad-4fa0-b9c3-c06dad7ce12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366989030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2366989030
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3619442139
Short name T36
Test name
Test status
Simulation time 14336303911 ps
CPU time 180.42 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:19:18 PM PDT 24
Peak memory 267092 kb
Host smart-c95fa67b-dffe-4c5c-853a-e5d8098eb502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619442139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3619442139
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2943925326
Short name T314
Test name
Test status
Simulation time 993310152 ps
CPU time 9.17 seconds
Started Aug 01 05:16:09 PM PDT 24
Finished Aug 01 05:16:18 PM PDT 24
Peak memory 225144 kb
Host smart-9615aa1a-cddc-4981-8fd2-001463e8711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943925326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2943925326
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.905737878
Short name T193
Test name
Test status
Simulation time 67390024449 ps
CPU time 65.76 seconds
Started Aug 01 05:16:09 PM PDT 24
Finished Aug 01 05:17:15 PM PDT 24
Peak memory 253032 kb
Host smart-59b96fe6-5649-4198-9a68-329a53980af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905737878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
905737878
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.804692193
Short name T723
Test name
Test status
Simulation time 65039334 ps
CPU time 3.1 seconds
Started Aug 01 05:16:07 PM PDT 24
Finished Aug 01 05:16:10 PM PDT 24
Peak memory 233380 kb
Host smart-0d43ab33-5316-4a7e-b463-bebe51b7d36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804692193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.804692193
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.303406936
Short name T555
Test name
Test status
Simulation time 605150726 ps
CPU time 6.67 seconds
Started Aug 01 05:16:14 PM PDT 24
Finished Aug 01 05:16:20 PM PDT 24
Peak memory 225152 kb
Host smart-eb725351-5966-4c5e-975e-04ffd57d075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303406936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.303406936
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1017788803
Short name T450
Test name
Test status
Simulation time 96182130 ps
CPU time 0.99 seconds
Started Aug 01 05:16:10 PM PDT 24
Finished Aug 01 05:16:11 PM PDT 24
Peak memory 218324 kb
Host smart-381ed610-27f8-4ecd-9059-e81f35e14ba7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017788803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1017788803
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2946571714
Short name T1010
Test name
Test status
Simulation time 1475853958 ps
CPU time 10.71 seconds
Started Aug 01 05:16:16 PM PDT 24
Finished Aug 01 05:16:26 PM PDT 24
Peak memory 241552 kb
Host smart-28bd92bf-f041-4e7d-a2f8-4d5c3446b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946571714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2946571714
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2894163196
Short name T259
Test name
Test status
Simulation time 547182881 ps
CPU time 2.67 seconds
Started Aug 01 05:16:12 PM PDT 24
Finished Aug 01 05:16:14 PM PDT 24
Peak memory 225288 kb
Host smart-f567d5b4-e11d-44fa-bcfe-46d6520cdef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894163196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2894163196
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.87577307
Short name T461
Test name
Test status
Simulation time 2288291237 ps
CPU time 4.92 seconds
Started Aug 01 05:16:10 PM PDT 24
Finished Aug 01 05:16:15 PM PDT 24
Peak memory 220648 kb
Host smart-5a8e8a57-3cfd-475a-b1bd-f5c37547f352
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=87577307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct
.87577307
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1270464722
Short name T675
Test name
Test status
Simulation time 3297846377 ps
CPU time 14.72 seconds
Started Aug 01 05:16:06 PM PDT 24
Finished Aug 01 05:16:21 PM PDT 24
Peak memory 217072 kb
Host smart-6160bf2e-8edd-4bb2-827d-435c5093f1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270464722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1270464722
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.380079618
Short name T755
Test name
Test status
Simulation time 14867089 ps
CPU time 0.76 seconds
Started Aug 01 05:16:13 PM PDT 24
Finished Aug 01 05:16:14 PM PDT 24
Peak memory 206116 kb
Host smart-788296da-82eb-401e-85de-ce6a11304bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380079618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.380079618
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3038520644
Short name T352
Test name
Test status
Simulation time 111902230 ps
CPU time 2.61 seconds
Started Aug 01 05:16:12 PM PDT 24
Finished Aug 01 05:16:14 PM PDT 24
Peak memory 216884 kb
Host smart-6928732b-27f3-4b28-bddd-023adf4f8f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038520644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3038520644
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3156246461
Short name T366
Test name
Test status
Simulation time 27492754 ps
CPU time 0.74 seconds
Started Aug 01 05:16:18 PM PDT 24
Finished Aug 01 05:16:19 PM PDT 24
Peak memory 206520 kb
Host smart-33fc293c-4478-4cf6-b72d-6e2fba0eb0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156246461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3156246461
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.120278296
Short name T349
Test name
Test status
Simulation time 70113559 ps
CPU time 2.06 seconds
Started Aug 01 05:16:13 PM PDT 24
Finished Aug 01 05:16:15 PM PDT 24
Peak memory 223720 kb
Host smart-7befd654-9d95-4279-bbab-328c4372264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120278296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.120278296
Directory /workspace/9.spi_device_upload/latest
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