Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3087109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4094992

1

T1

1615

T2

3005

T3

505

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3816471	1			T1	1444		T2	3439		T3	1
values[0x0]	1682050	1			T1	465		T2	1526		T3	334
values[0x1]	1683580	1			T1	442		T2	1526		T3	310

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2202782	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4979319

1

T1

1764

T2

4065

T3

536

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27131	1			T1	5		T2	24		T3	3
valid_sources[0x01]	27411	1			T1	8		T2	20		T3	1
valid_sources[0x02]	27212	1			T1	9		T2	13		T3	1
valid_sources[0x03]	27563	1			T1	4		T2	26		T3	2
valid_sources[0x04]	26542	1			T1	13		T2	47		T3	3
valid_sources[0x05]	31737	1			T1	9		T2	35		T5	1
valid_sources[0x06]	28359	1			T1	15		T2	11		T5	2
valid_sources[0x07]	30065	1			T1	15		T2	26		T3	3
valid_sources[0x08]	27085	1			T1	4		T2	31		T3	2
valid_sources[0x09]	28155	1			T1	6		T2	26		T3	4
valid_sources[0x0a]	28209	1			T1	15		T2	9		T3	3
valid_sources[0x0b]	26646	1			T1	7		T2	11		T3	3
valid_sources[0x0c]	29270	1			T1	4		T2	21		T3	1
valid_sources[0x0d]	27465	1			T1	12		T2	10		T3	3
valid_sources[0x0e]	26036	1			T1	5		T2	20		T3	6
valid_sources[0x0f]	28506	1			T1	5		T2	15		T5	11
valid_sources[0x10]	26555	1			T1	6		T2	25		T3	5
valid_sources[0x11]	25732	1			T1	7		T2	22		T3	2
valid_sources[0x12]	27026	1			T1	12		T2	28		T3	1
valid_sources[0x13]	28647	1			T1	11		T2	32		T3	3
valid_sources[0x14]	26923	1			T1	14		T2	34		T3	1
valid_sources[0x15]	39288	1			T1	17		T2	25		T3	6
valid_sources[0x16]	30695	1			T1	10		T2	44		T3	1
valid_sources[0x17]	26787	1			T1	14		T2	33		T3	2
valid_sources[0x18]	30234	1			T1	10		T2	23		T3	1
valid_sources[0x19]	29614	1			T1	12		T2	27		T3	3
valid_sources[0x1a]	24733	1			T1	8		T2	11		T3	2
valid_sources[0x1b]	25872	1			T1	6		T2	11		T3	2
valid_sources[0x1c]	26392	1			T1	6		T2	23		T3	2
valid_sources[0x1d]	27650	1			T1	5		T2	17		T3	2
valid_sources[0x1e]	27447	1			T1	10		T2	31		T3	4
valid_sources[0x1f]	27153	1			T1	9		T2	32		T3	1
valid_sources[0x20]	25214	1			T1	5		T2	24		T3	5
valid_sources[0x21]	28476	1			T1	7		T2	30		T3	2
valid_sources[0x22]	25788	1			T1	10		T2	24		T3	6
valid_sources[0x23]	34088	1			T1	18		T2	27		T3	6
valid_sources[0x24]	27295	1			T1	10		T2	25		T3	1
valid_sources[0x25]	26457	1			T1	7		T2	25		T3	4
valid_sources[0x26]	28168	1			T1	8		T2	4		T3	2
valid_sources[0x27]	27350	1			T1	10		T2	29		T3	3
valid_sources[0x28]	28708	1			T1	6		T2	27		T3	4
valid_sources[0x29]	25803	1			T1	10		T2	29		T3	3
valid_sources[0x2a]	29015	1			T1	10		T2	30		T3	1
valid_sources[0x2b]	27868	1			T1	10		T2	23		T3	3
valid_sources[0x2c]	27349	1			T1	14		T2	12		T3	1
valid_sources[0x2d]	26271	1			T1	9		T2	27		T3	2
valid_sources[0x2e]	26001	1			T1	6		T2	11		T3	4
valid_sources[0x2f]	27628	1			T1	12		T2	50		T5	10
valid_sources[0x30]	26544	1			T1	7		T2	30		T3	4
valid_sources[0x31]	25199	1			T1	9		T2	32		T3	3
valid_sources[0x32]	27179	1			T1	9		T2	9		T3	3
valid_sources[0x33]	27923	1			T1	10		T2	20		T3	4
valid_sources[0x34]	28147	1			T1	10		T2	12		T3	1
valid_sources[0x35]	25824	1			T1	8		T2	20		T3	2
valid_sources[0x36]	29222	1			T1	13		T2	44		T3	2
valid_sources[0x37]	27055	1			T1	11		T2	16		T3	2
valid_sources[0x38]	27033	1			T1	8		T2	7		T3	3
valid_sources[0x39]	26193	1			T1	7		T2	14		T3	4
valid_sources[0x3a]	25575	1			T1	4		T2	21		T5	4
valid_sources[0x3b]	28421	1			T1	13		T2	12		T3	2
valid_sources[0x3c]	26841	1			T1	11		T2	24		T3	1
valid_sources[0x3d]	24874	1			T1	6		T2	47		T3	1
valid_sources[0x3e]	27251	1			T1	14		T2	34		T3	1
valid_sources[0x3f]	26509	1			T1	11		T2	21		T3	2
valid_sources[0x40]	27993	1			T1	7		T2	20		T3	4
valid_sources[0x41]	26861	1			T1	10		T2	41		T3	2
valid_sources[0x42]	26022	1			T1	13		T2	29		T3	2
valid_sources[0x43]	25850	1			T1	10		T2	9		T3	5
valid_sources[0x44]	29756	1			T1	8		T2	32		T5	4
valid_sources[0x45]	25480	1			T1	6		T2	35		T3	1
valid_sources[0x46]	27180	1			T1	5		T2	64		T3	3
valid_sources[0x47]	28407	1			T1	12		T2	21		T3	2
valid_sources[0x48]	25956	1			T1	6		T2	48		T3	3
valid_sources[0x49]	28403	1			T1	5		T2	29		T3	4
valid_sources[0x4a]	26730	1			T1	8		T2	36		T3	1
valid_sources[0x4b]	29637	1			T1	5		T2	18		T3	1
valid_sources[0x4c]	28590	1			T1	9		T2	11		T3	2
valid_sources[0x4d]	27667	1			T1	6		T2	10		T3	3
valid_sources[0x4e]	26450	1			T1	8		T2	10		T3	3
valid_sources[0x4f]	26738	1			T1	10		T2	14		T3	2
valid_sources[0x50]	27206	1			T1	13		T2	32		T3	4
valid_sources[0x51]	23715	1			T1	7		T2	6		T3	3
valid_sources[0x52]	30747	1			T1	4		T2	6		T3	2
valid_sources[0x53]	28283	1			T1	7		T2	54		T3	3
valid_sources[0x54]	29103	1			T1	8		T2	42		T3	4
valid_sources[0x55]	60773	1			T1	5		T2	13		T3	6
valid_sources[0x56]	30736	1			T1	7		T2	11		T3	3
valid_sources[0x57]	28874	1			T1	13		T2	23		T3	2
valid_sources[0x58]	25812	1			T1	6		T2	24		T3	5
valid_sources[0x59]	26931	1			T1	9		T2	73		T8	51
valid_sources[0x5a]	25676	1			T1	11		T2	22		T3	2
valid_sources[0x5b]	31361	1			T1	9		T2	42		T3	4
valid_sources[0x5c]	26140	1			T1	17		T2	19		T3	1
valid_sources[0x5d]	28968	1			T1	10		T2	20		T3	1
valid_sources[0x5e]	27671	1			T1	9		T2	33		T3	2
valid_sources[0x5f]	28921	1			T1	10		T2	24		T3	4
valid_sources[0x60]	28608	1			T1	10		T2	23		T3	2
valid_sources[0x61]	28614	1			T1	6		T2	20		T3	3
valid_sources[0x62]	28058	1			T1	6		T2	50		T3	3
valid_sources[0x63]	30039	1			T1	8		T2	21		T3	1
valid_sources[0x64]	29017	1			T1	7		T2	30		T3	3
valid_sources[0x65]	28300	1			T1	18		T2	8		T3	4
valid_sources[0x66]	28313	1			T1	10		T2	23		T3	3
valid_sources[0x67]	26807	1			T1	9		T2	27		T3	2
valid_sources[0x68]	32033	1			T1	11		T2	18		T3	6
valid_sources[0x69]	29424	1			T1	8		T2	27		T3	2
valid_sources[0x6a]	26196	1			T1	12		T2	35		T3	3
valid_sources[0x6b]	30637	1			T1	7		T2	36		T3	1
valid_sources[0x6c]	30605	1			T1	7		T2	31		T3	2
valid_sources[0x6d]	29340	1			T1	6		T2	26		T3	2
valid_sources[0x6e]	26111	1			T1	6		T2	12		T3	3
valid_sources[0x6f]	27246	1			T1	17		T2	24		T3	2
valid_sources[0x70]	27517	1			T1	8		T2	25		T3	2
valid_sources[0x71]	25413	1			T1	10		T2	11		T3	4
valid_sources[0x72]	26225	1			T1	8		T2	9		T3	4
valid_sources[0x73]	28101	1			T1	10		T2	17		T3	1
valid_sources[0x74]	26078	1			T1	8		T2	24		T3	2
valid_sources[0x75]	24819	1			T1	9		T2	19		T3	2
valid_sources[0x76]	32393	1			T1	15		T2	27		T3	8
valid_sources[0x77]	26724	1			T1	11		T2	22		T3	4
valid_sources[0x78]	25103	1			T1	9		T2	32		T3	1
valid_sources[0x79]	36613	1			T1	11		T2	17		T3	3
valid_sources[0x7a]	35485	1			T1	10		T2	51		T3	4
valid_sources[0x7b]	25546	1			T1	5		T2	21		T3	1
valid_sources[0x7c]	26020	1			T1	5		T2	30		T3	3
valid_sources[0x7d]	29067	1			T1	9		T2	34		T3	3
valid_sources[0x7e]	26764	1			T1	11		T2	27		T3	5
valid_sources[0x7f]	27405	1			T1	7		T2	44		T3	1
valid_sources[0x80]	28895	1			T1	6		T2	38		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1014317

1

T1

713

T2

482

T5

290

values[0x0]

all_enables

biggest_size

1551202

1

T1

464

T2

1309

T3

261

values[0x1]

all_enables

biggest_size

1529473

1

T1

438

T2

1214

T3

244