Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3109331

1

T1

736

T2

3486

T3

140

full_word

4094365

1

T1

1615

T2

3005

T3

505

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7203336	1			T1	2351		T2	6491		T3	645
auto[TlIntgErrCmd]	134	1			T94	6		T95	15		T99	3
auto[TlIntgErrData]	98	1			T94	5		T95	7		T99	9
auto[TlIntgErrBoth]	128	1			T94	9		T95	8		T99	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3819725

1

T1

1444

T2

3439

T3

1

auto[1]

3383971

1

T1

907

T2

3052

T3

644

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2805029	1			T1	731		T2	2957		T3	1
auto[TlIntgErrNone]	partial	auto[1]	303976	1			T1	5		T2	529		T3	139
auto[TlIntgErrNone]	full_word	auto[0]	1014549	1			T1	713		T2	482		T5	290
auto[TlIntgErrNone]	full_word	auto[1]	3079782	1			T1	902		T2	2523		T3	505
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T94	3		T95	6		T99	2
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T94	2		T95	7		T99	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T94	1		T95	2		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T178	1		T179	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T94	4		T95	4		T99	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T95	2		T99	3		T100	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T99	2		T181	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T94	1		T95	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T94	3		T95	4		T99	3
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T94	5		T95	3		T99	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T99	1		T100	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T94	1		T95	1		T116	2