Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428484138	3011151	0	0
DepthKnown_A	428484138	428354717	0	0
RvalidKnown_A	428484138	428354717	0	0
WreadyKnown_A	428484138	428354717	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	3011151	0	0
T1	32539	1663	0	0
T2	234336	832	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	1663	0	0
T6	7633	1663	0	0
T7	7697	0	0	0
T8	308079	2495	0	0
T9	105667	3327	0	0
T10	357583	9980	0	0
T11	0	1663	0	0
T12	0	1663	0	0
T13	0	9991	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428484138	3158522	0	0
DepthKnown_A	428484138	428354717	0	0
RvalidKnown_A	428484138	428354717	0	0
WreadyKnown_A	428484138	428354717	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	3158522	0	0
T1	32539	832	0	0
T2	234336	832	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	0	0	0
T8	308079	3370	0	0
T9	105667	8606	0	0
T10	357583	6656	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	25684	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428484138	187909	0	0
DepthKnown_A	428484138	428354717	0	0
RvalidKnown_A	428484138	428354717	0	0
WreadyKnown_A	428484138	428354717	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	187909	0	0
T2	234336	301	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	0	0	0
T6	7633	0	0	0
T7	7697	24	0	0
T8	308079	112	0	0
T9	105667	1193	0	0
T10	357583	450	0	0
T11	118830	0	0	0
T13	0	1322	0	0
T23	0	1283	0	0
T30	0	494	0	0
T31	0	130	0	0
T39	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428484138	394619	0	0
DepthKnown_A	428484138	428354717	0	0
RvalidKnown_A	428484138	428354717	0	0
WreadyKnown_A	428484138	428354717	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	394619	0	0
T2	234336	301	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	0	0	0
T6	7633	0	0	0
T7	7697	98	0	0
T8	308079	311	0	0
T9	105667	5224	0	0
T10	357583	450	0	0
T11	118830	0	0	0
T13	0	6150	0	0
T23	0	5929	0	0
T30	0	1454	0	0
T31	0	130	0	0
T39	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428484138	5401338	0	0
DepthKnown_A	428484138	428354717	0	0
RvalidKnown_A	428484138	428354717	0	0
WreadyKnown_A	428484138	428354717	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	5401338	0	0
T1	32539	1519	0	0
T2	234336	5430	0	0
T3	500560	645	0	0
T4	27544	69	0	0
T5	18468	659	0	0
T6	7633	158	0	0
T7	7697	137	0	0
T8	308079	4938	0	0
T9	105667	21481	0	0
T10	357583	5638	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428484138	10207967	0	0
DepthKnown_A	428484138	428354717	0	0
RvalidKnown_A	428484138	428354717	0	0
WreadyKnown_A	428484138	428354717	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	10207967	0	0
T1	32539	1519	0	0
T2	234336	5358	0	0
T3	500560	2797	0	0
T4	27544	319	0	0
T5	18468	659	0	0
T6	7633	158	0	0
T7	7697	629	0	0
T8	308079	13884	0	0
T9	105667	87073	0	0
T10	357583	5635	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428484138	428354717	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0