Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	726242405	574818007	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	726242405	3774093	0	0
GntImpliesValid_A	726242405	3774093	0	0
GrantKnown_A	726242405	574818007	0	0
IdxKnown_A	726242405	574818007	0	0
IndexIsCorrect_A	726242405	3774093	0	0
LockArbDecision_A	726242405	0	0	0
NoReadyValidNoGrant_A	726242405	0	0	0
ReadyAndValidImplyGrant_A	726242405	3774093	0	0
ReqAndReadyImplyGrant_A	726242405	3774093	0	0
ReqImpliesValid_A	726242405	3774093	0	0
ReqStaysHighUntilGranted0_M	726242405	0	0	0
RoundRobin_A	726242405	4	0	975
ValidKnown_A	726242405	574818007	0	0
gen_data_port_assertion.DataFlow_A	726242405	3774093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	574818007	0	0
T1	60779	60350	0	0
T2	458878	344622	0	0
T3	642192	568472	0	0
T4	42988	34759	0	0
T5	48396	33081	0	0
T6	15869	11675	0	0
T7	17833	12251	0	0
T8	614529	460502	0	0
T9	640001	363284	0	0
T10	1536979	945340	0	0
T11	23036	23036	0	0
T12	0	17245	0	0
T13	0	528647	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	3774093	0	0
T1	32539	832	0	0
T2	458878	3794	0	0
T3	642192	0	0	0
T4	42988	0	0	0
T5	48396	832	0	0
T6	15869	832	0	0
T7	17833	187	0	0
T8	614529	2623	0	0
T9	640001	12469	0	0
T10	1536979	12886	0	0
T11	46072	832	0	0
T12	0	832	0	0
T13	0	9461	0	0
T23	0	8638	0	0
T30	0	2670	0	0
T31	0	758	0	0
T33	0	1445	0	0
T39	0	270	0	0
T42	0	5693	0	0
T45	0	5064	0	0
T49	0	3189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	3774093	0	0
T1	32539	832	0	0
T2	458878	3794	0	0
T3	642192	0	0	0
T4	42988	0	0	0
T5	48396	832	0	0
T6	15869	832	0	0
T7	17833	187	0	0
T8	614529	2623	0	0
T9	640001	12469	0	0
T10	1536979	12886	0	0
T11	46072	832	0	0
T12	0	832	0	0
T13	0	9461	0	0
T23	0	8638	0	0
T30	0	2670	0	0
T31	0	758	0	0
T33	0	1445	0	0
T39	0	270	0	0
T42	0	5693	0	0
T45	0	5064	0	0
T49	0	3189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	574818007	0	0
T1	60779	60350	0	0
T2	458878	344622	0	0
T3	642192	568472	0	0
T4	42988	34759	0	0
T5	48396	33081	0	0
T6	15869	11675	0	0
T7	17833	12251	0	0
T8	614529	460502	0	0
T9	640001	363284	0	0
T10	1536979	945340	0	0
T11	23036	23036	0	0
T12	0	17245	0	0
T13	0	528647	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	574818007	0	0
T1	60779	60350	0	0
T2	458878	344622	0	0
T3	642192	568472	0	0
T4	42988	34759	0	0
T5	48396	33081	0	0
T6	15869	11675	0	0
T7	17833	12251	0	0
T8	614529	460502	0	0
T9	640001	363284	0	0
T10	1536979	945340	0	0
T11	23036	23036	0	0
T12	0	17245	0	0
T13	0	528647	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	3774093	0	0
T1	32539	832	0	0
T2	458878	3794	0	0
T3	642192	0	0	0
T4	42988	0	0	0
T5	48396	832	0	0
T6	15869	832	0	0
T7	17833	187	0	0
T8	614529	2623	0	0
T9	640001	12469	0	0
T10	1536979	12886	0	0
T11	46072	832	0	0
T12	0	832	0	0
T13	0	9461	0	0
T23	0	8638	0	0
T30	0	2670	0	0
T31	0	758	0	0
T33	0	1445	0	0
T39	0	270	0	0
T42	0	5693	0	0
T45	0	5064	0	0
T49	0	3189	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	3774093	0	0
T1	32539	832	0	0
T2	458878	3794	0	0
T3	642192	0	0	0
T4	42988	0	0	0
T5	48396	832	0	0
T6	15869	832	0	0
T7	17833	187	0	0
T8	614529	2623	0	0
T9	640001	12469	0	0
T10	1536979	12886	0	0
T11	46072	832	0	0
T12	0	832	0	0
T13	0	9461	0	0
T23	0	8638	0	0
T30	0	2670	0	0
T31	0	758	0	0
T33	0	1445	0	0
T39	0	270	0	0
T42	0	5693	0	0
T45	0	5064	0	0
T49	0	3189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	3774093	0	0
T1	32539	832	0	0
T2	458878	3794	0	0
T3	642192	0	0	0
T4	42988	0	0	0
T5	48396	832	0	0
T6	15869	832	0	0
T7	17833	187	0	0
T8	614529	2623	0	0
T9	640001	12469	0	0
T10	1536979	12886	0	0
T11	46072	832	0	0
T12	0	832	0	0
T13	0	9461	0	0
T23	0	8638	0	0
T30	0	2670	0	0
T31	0	758	0	0
T33	0	1445	0	0
T39	0	270	0	0
T42	0	5693	0	0
T45	0	5064	0	0
T49	0	3189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	3774093	0	0
T1	32539	832	0	0
T2	458878	3794	0	0
T3	642192	0	0	0
T4	42988	0	0	0
T5	48396	832	0	0
T6	15869	832	0	0
T7	17833	187	0	0
T8	614529	2623	0	0
T9	640001	12469	0	0
T10	1536979	12886	0	0
T11	46072	832	0	0
T12	0	832	0	0
T13	0	9461	0	0
T23	0	8638	0	0
T30	0	2670	0	0
T31	0	758	0	0
T33	0	1445	0	0
T39	0	270	0	0
T42	0	5693	0	0
T45	0	5064	0	0
T49	0	3189	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	4	0	975
T38	1260	0	0	1
T50	875725	1	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	61823	0	0	1
T55	21216	0	0	1
T56	11944	0	0	1
T57	964	0	0	1
T58	98956	0	0	1
T59	99415	0	0	1
T60	242997	0	0	1
T61	5409	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	574818007	0	0
T1	60779	60350	0	0
T2	458878	344622	0	0
T3	642192	568472	0	0
T4	42988	34759	0	0
T5	48396	33081	0	0
T6	15869	11675	0	0
T7	17833	12251	0	0
T8	614529	460502	0	0
T9	640001	363284	0	0
T10	1536979	945340	0	0
T11	23036	23036	0	0
T12	0	17245	0	0
T13	0	528647	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726242405	3774093	0	0
T1	32539	832	0	0
T2	458878	3794	0	0
T3	642192	0	0	0
T4	42988	0	0	0
T5	48396	832	0	0
T6	15869	832	0	0
T7	17833	187	0	0
T8	614529	2623	0	0
T9	640001	12469	0	0
T10	1536979	12886	0	0
T11	46072	832	0	0
T12	0	832	0	0
T13	0	9461	0	0
T23	0	8638	0	0
T30	0	2670	0	0
T31	0	758	0	0
T33	0	1445	0	0
T39	0	270	0	0
T42	0	5693	0	0
T45	0	5064	0	0
T49	0	3189	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150027088	27675888	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	150027088	566602	0	0
GntImpliesValid_A	150027088	566602	0	0
GrantKnown_A	150027088	27675888	0	0
IdxKnown_A	150027088	27675888	0	0
IndexIsCorrect_A	150027088	566602	0	0
LockArbDecision_A	150027088	0	0	0
NoReadyValidNoGrant_A	150027088	0	0	0
ReadyAndValidImplyGrant_A	150027088	566602	0	0
ReqAndReadyImplyGrant_A	150027088	566602	0	0
ReqImpliesValid_A	150027088	566602	0	0
ReqStaysHighUntilGranted0_M	150027088	0	0	0
RoundRobin_A	150027088	0	0	0
ValidKnown_A	150027088	27675888	0	0
gen_data_port_assertion.DataFlow_A	150027088	566602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	27675888	0	0
T2	112271	57456	0	0
T3	70816	68000	0	0
T4	7722	7312	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	4632	0	0
T8	153225	16480	0	0
T9	267167	152480	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	201672	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	566602	0	0
T2	112271	1944	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	129	0	0
T8	153225	392	0	0
T9	267167	6671	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	4878	0	0
T23	0	4995	0	0
T30	0	1187	0	0
T31	0	758	0	0
T33	0	1445	0	0
T45	0	5064	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	566602	0	0
T2	112271	1944	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	129	0	0
T8	153225	392	0	0
T9	267167	6671	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	4878	0	0
T23	0	4995	0	0
T30	0	1187	0	0
T31	0	758	0	0
T33	0	1445	0	0
T45	0	5064	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	27675888	0	0
T2	112271	57456	0	0
T3	70816	68000	0	0
T4	7722	7312	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	4632	0	0
T8	153225	16480	0	0
T9	267167	152480	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	201672	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	27675888	0	0
T2	112271	57456	0	0
T3	70816	68000	0	0
T4	7722	7312	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	4632	0	0
T8	153225	16480	0	0
T9	267167	152480	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	201672	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	566602	0	0
T2	112271	1944	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	129	0	0
T8	153225	392	0	0
T9	267167	6671	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	4878	0	0
T23	0	4995	0	0
T30	0	1187	0	0
T31	0	758	0	0
T33	0	1445	0	0
T45	0	5064	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	566602	0	0
T2	112271	1944	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	129	0	0
T8	153225	392	0	0
T9	267167	6671	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	4878	0	0
T23	0	4995	0	0
T30	0	1187	0	0
T31	0	758	0	0
T33	0	1445	0	0
T45	0	5064	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	566602	0	0
T2	112271	1944	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	129	0	0
T8	153225	392	0	0
T9	267167	6671	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	4878	0	0
T23	0	4995	0	0
T30	0	1187	0	0
T31	0	758	0	0
T33	0	1445	0	0
T45	0	5064	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	566602	0	0
T2	112271	1944	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	129	0	0
T8	153225	392	0	0
T9	267167	6671	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	4878	0	0
T23	0	4995	0	0
T30	0	1187	0	0
T31	0	758	0	0
T33	0	1445	0	0
T45	0	5064	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	27675888	0	0
T2	112271	57456	0	0
T3	70816	68000	0	0
T4	7722	7312	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	4632	0	0
T8	153225	16480	0	0
T9	267167	152480	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	201672	0	0
T23	0	117968	0	0
T30	0	28704	0	0
T31	0	31920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	566602	0	0
T2	112271	1944	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	129	0	0
T8	153225	392	0	0
T9	267167	6671	0	0
T10	589698	0	0	0
T11	23036	0	0	0
T13	0	4878	0	0
T23	0	4995	0	0
T30	0	1187	0	0
T31	0	758	0	0
T33	0	1445	0	0
T45	0	5064	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150027088	121041507	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	150027088	902926	0	0
GntImpliesValid_A	150027088	902926	0	0
GrantKnown_A	150027088	121041507	0	0
IdxKnown_A	150027088	121041507	0	0
IndexIsCorrect_A	150027088	902926	0	0
LockArbDecision_A	150027088	0	0	0
NoReadyValidNoGrant_A	150027088	0	0	0
ReadyAndValidImplyGrant_A	150027088	902926	0	0
ReqAndReadyImplyGrant_A	150027088	902926	0	0
ReqImpliesValid_A	150027088	902926	0	0
ReqStaysHighUntilGranted0_M	150027088	0	0	0
RoundRobin_A	150027088	0	0	0
ValidKnown_A	150027088	121041507	0	0
gen_data_port_assertion.DataFlow_A	150027088	902926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	121041507	0	0
T1	28240	27872	0	0
T2	112271	52890	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	14668	0	0
T6	4118	4112	0	0
T7	5068	0	0	0
T8	153225	135994	0	0
T9	267167	105146	0	0
T10	589698	587762	0	0
T11	0	23036	0	0
T12	0	17245	0	0
T13	0	326975	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	902926	0	0
T2	112271	2	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	0	0	0
T8	153225	262	0	0
T9	267167	141	0	0
T10	589698	5753	0	0
T11	23036	0	0	0
T13	0	4583	0	0
T23	0	3643	0	0
T30	0	1483	0	0
T39	0	270	0	0
T42	0	5693	0	0
T49	0	3189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	902926	0	0
T2	112271	2	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	0	0	0
T8	153225	262	0	0
T9	267167	141	0	0
T10	589698	5753	0	0
T11	23036	0	0	0
T13	0	4583	0	0
T23	0	3643	0	0
T30	0	1483	0	0
T39	0	270	0	0
T42	0	5693	0	0
T49	0	3189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	121041507	0	0
T1	28240	27872	0	0
T2	112271	52890	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	14668	0	0
T6	4118	4112	0	0
T7	5068	0	0	0
T8	153225	135994	0	0
T9	267167	105146	0	0
T10	589698	587762	0	0
T11	0	23036	0	0
T12	0	17245	0	0
T13	0	326975	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	121041507	0	0
T1	28240	27872	0	0
T2	112271	52890	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	14668	0	0
T6	4118	4112	0	0
T7	5068	0	0	0
T8	153225	135994	0	0
T9	267167	105146	0	0
T10	589698	587762	0	0
T11	0	23036	0	0
T12	0	17245	0	0
T13	0	326975	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	902926	0	0
T2	112271	2	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	0	0	0
T8	153225	262	0	0
T9	267167	141	0	0
T10	589698	5753	0	0
T11	23036	0	0	0
T13	0	4583	0	0
T23	0	3643	0	0
T30	0	1483	0	0
T39	0	270	0	0
T42	0	5693	0	0
T49	0	3189	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	902926	0	0
T2	112271	2	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	0	0	0
T8	153225	262	0	0
T9	267167	141	0	0
T10	589698	5753	0	0
T11	23036	0	0	0
T13	0	4583	0	0
T23	0	3643	0	0
T30	0	1483	0	0
T39	0	270	0	0
T42	0	5693	0	0
T49	0	3189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	902926	0	0
T2	112271	2	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	0	0	0
T8	153225	262	0	0
T9	267167	141	0	0
T10	589698	5753	0	0
T11	23036	0	0	0
T13	0	4583	0	0
T23	0	3643	0	0
T30	0	1483	0	0
T39	0	270	0	0
T42	0	5693	0	0
T49	0	3189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	902926	0	0
T2	112271	2	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	0	0	0
T8	153225	262	0	0
T9	267167	141	0	0
T10	589698	5753	0	0
T11	23036	0	0	0
T13	0	4583	0	0
T23	0	3643	0	0
T30	0	1483	0	0
T39	0	270	0	0
T42	0	5693	0	0
T49	0	3189	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	121041507	0	0
T1	28240	27872	0	0
T2	112271	52890	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	14668	0	0
T6	4118	4112	0	0
T7	5068	0	0	0
T8	153225	135994	0	0
T9	267167	105146	0	0
T10	589698	587762	0	0
T11	0	23036	0	0
T12	0	17245	0	0
T13	0	326975	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150027088	902926	0	0
T2	112271	2	0	0
T3	70816	0	0	0
T4	7722	0	0	0
T5	14964	0	0	0
T6	4118	0	0	0
T7	5068	0	0	0
T8	153225	262	0	0
T9	267167	141	0	0
T10	589698	5753	0	0
T11	23036	0	0	0
T13	0	4583	0	0
T23	0	3643	0	0
T30	0	1483	0	0
T39	0	270	0	0
T42	0	5693	0	0
T49	0	3189	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426188229	426100612	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	426188229	2304565	0	0
GntImpliesValid_A	426188229	2304565	0	0
GrantKnown_A	426188229	426100612	0	0
IdxKnown_A	426188229	426100612	0	0
IndexIsCorrect_A	426188229	2304565	0	0
LockArbDecision_A	426188229	0	0	0
NoReadyValidNoGrant_A	426188229	0	0	0
ReadyAndValidImplyGrant_A	426188229	2304565	0	0
ReqAndReadyImplyGrant_A	426188229	2304565	0	0
ReqImpliesValid_A	426188229	2304565	0	0
ReqStaysHighUntilGranted0_M	426188229	0	0	0
RoundRobin_A	426188229	4	0	975
ValidKnown_A	426188229	426100612	0	0
gen_data_port_assertion.DataFlow_A	426188229	2304565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	426100612	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	2304565	0	0
T1	32539	832	0	0
T2	234336	1848	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	58	0	0
T8	308079	1969	0	0
T9	105667	5657	0	0
T10	357583	7133	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	2304565	0	0
T1	32539	832	0	0
T2	234336	1848	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	58	0	0
T8	308079	1969	0	0
T9	105667	5657	0	0
T10	357583	7133	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	426100612	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	426100612	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	2304565	0	0
T1	32539	832	0	0
T2	234336	1848	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	58	0	0
T8	308079	1969	0	0
T9	105667	5657	0	0
T10	357583	7133	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	2304565	0	0
T1	32539	832	0	0
T2	234336	1848	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	58	0	0
T8	308079	1969	0	0
T9	105667	5657	0	0
T10	357583	7133	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	2304565	0	0
T1	32539	832	0	0
T2	234336	1848	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	58	0	0
T8	308079	1969	0	0
T9	105667	5657	0	0
T10	357583	7133	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	2304565	0	0
T1	32539	832	0	0
T2	234336	1848	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	58	0	0
T8	308079	1969	0	0
T9	105667	5657	0	0
T10	357583	7133	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	4	0	975
T38	1260	0	0	1
T50	875725	1	0	1
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	61823	0	0	1
T55	21216	0	0	1
T56	11944	0	0	1
T57	964	0	0	1
T58	98956	0	0	1
T59	99415	0	0	1
T60	242997	0	0	1
T61	5409	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	426100612	0	0
T1	32539	32478	0	0
T2	234336	234276	0	0
T3	500560	500472	0	0
T4	27544	27447	0	0
T5	18468	18413	0	0
T6	7633	7563	0	0
T7	7697	7619	0	0
T8	308079	308028	0	0
T9	105667	105658	0	0
T10	357583	357578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426188229	2304565	0	0
T1	32539	832	0	0
T2	234336	1848	0	0
T3	500560	0	0	0
T4	27544	0	0	0
T5	18468	832	0	0
T6	7633	832	0	0
T7	7697	58	0	0
T8	308079	1969	0	0
T9	105667	5657	0	0
T10	357583	7133	0	0
T11	0	832	0	0
T12	0	832	0	0