Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
3568 | 
0 | 
0 | 
| T94 | 
68583 | 
3 | 
0 | 
0 | 
| T95 | 
93542 | 
1 | 
0 | 
0 | 
| T96 | 
17208 | 
8 | 
0 | 
0 | 
| T97 | 
4201 | 
2 | 
0 | 
0 | 
| T98 | 
22025 | 
351 | 
0 | 
0 | 
| T99 | 
19460 | 
4 | 
0 | 
0 | 
| T100 | 
54793 | 
3 | 
0 | 
0 | 
| T101 | 
4291 | 
109 | 
0 | 
0 | 
| T102 | 
4635 | 
201 | 
0 | 
0 | 
| T114 | 
21048 | 
2 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2374 | 
0 | 
0 | 
| T94 | 
68583 | 
84 | 
0 | 
0 | 
| T95 | 
93542 | 
100 | 
0 | 
0 | 
| T96 | 
17208 | 
23 | 
0 | 
0 | 
| T115 | 
5772 | 
8 | 
0 | 
0 | 
| T126 | 
269809 | 
718 | 
0 | 
0 | 
| T156 | 
20439 | 
66 | 
0 | 
0 | 
| T157 | 
13724 | 
27 | 
0 | 
0 | 
| T158 | 
104154 | 
444 | 
0 | 
0 | 
| T159 | 
9702 | 
6 | 
0 | 
0 | 
| T160 | 
4426 | 
2 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2247 | 
0 | 
0 | 
| T94 | 
68583 | 
81 | 
0 | 
0 | 
| T95 | 
93542 | 
63 | 
0 | 
0 | 
| T96 | 
17208 | 
16 | 
0 | 
0 | 
| T115 | 
5772 | 
6 | 
0 | 
0 | 
| T126 | 
269809 | 
668 | 
0 | 
0 | 
| T156 | 
20439 | 
51 | 
0 | 
0 | 
| T157 | 
13724 | 
21 | 
0 | 
0 | 
| T158 | 
104154 | 
532 | 
0 | 
0 | 
| T159 | 
9702 | 
7 | 
0 | 
0 | 
| T160 | 
4426 | 
1 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2597 | 
0 | 
0 | 
| T94 | 
68583 | 
159 | 
0 | 
0 | 
| T95 | 
93542 | 
135 | 
0 | 
0 | 
| T96 | 
17208 | 
34 | 
0 | 
0 | 
| T109 | 
7452 | 
3 | 
0 | 
0 | 
| T115 | 
5772 | 
10 | 
0 | 
0 | 
| T126 | 
269809 | 
671 | 
0 | 
0 | 
| T156 | 
20439 | 
57 | 
0 | 
0 | 
| T157 | 
13724 | 
41 | 
0 | 
0 | 
| T158 | 
104154 | 
439 | 
0 | 
0 | 
| T159 | 
9702 | 
19 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
7487 | 
0 | 
0 | 
| T94 | 
68583 | 
1700 | 
0 | 
0 | 
| T95 | 
93542 | 
956 | 
0 | 
0 | 
| T96 | 
17208 | 
368 | 
0 | 
0 | 
| T115 | 
5772 | 
2 | 
0 | 
0 | 
| T126 | 
269809 | 
701 | 
0 | 
0 | 
| T156 | 
20439 | 
16 | 
0 | 
0 | 
| T157 | 
13724 | 
107 | 
0 | 
0 | 
| T158 | 
104154 | 
466 | 
0 | 
0 | 
| T159 | 
9702 | 
127 | 
0 | 
0 | 
| T160 | 
4426 | 
106 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
8166 | 
0 | 
0 | 
| T94 | 
68583 | 
1325 | 
0 | 
0 | 
| T95 | 
93542 | 
1181 | 
0 | 
0 | 
| T96 | 
17208 | 
392 | 
0 | 
0 | 
| T103 | 
8346 | 
2 | 
0 | 
0 | 
| T115 | 
5772 | 
120 | 
0 | 
0 | 
| T126 | 
269809 | 
684 | 
0 | 
0 | 
| T156 | 
20439 | 
49 | 
0 | 
0 | 
| T157 | 
13724 | 
221 | 
0 | 
0 | 
| T158 | 
104154 | 
452 | 
0 | 
0 | 
| T159 | 
9702 | 
7 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
6967 | 
0 | 
0 | 
| T94 | 
68583 | 
1551 | 
0 | 
0 | 
| T95 | 
93542 | 
842 | 
0 | 
0 | 
| T96 | 
17208 | 
217 | 
0 | 
0 | 
| T115 | 
5772 | 
132 | 
0 | 
0 | 
| T126 | 
269809 | 
628 | 
0 | 
0 | 
| T156 | 
20439 | 
148 | 
0 | 
0 | 
| T157 | 
13724 | 
93 | 
0 | 
0 | 
| T158 | 
104154 | 
462 | 
0 | 
0 | 
| T159 | 
9702 | 
8 | 
0 | 
0 | 
| T160 | 
4426 | 
5 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
6562 | 
0 | 
0 | 
| T94 | 
68583 | 
1288 | 
0 | 
0 | 
| T95 | 
93542 | 
713 | 
0 | 
0 | 
| T96 | 
17208 | 
283 | 
0 | 
0 | 
| T115 | 
5772 | 
7 | 
0 | 
0 | 
| T126 | 
269809 | 
692 | 
0 | 
0 | 
| T156 | 
20439 | 
29 | 
0 | 
0 | 
| T157 | 
13724 | 
23 | 
0 | 
0 | 
| T158 | 
104154 | 
448 | 
0 | 
0 | 
| T159 | 
9702 | 
65 | 
0 | 
0 | 
| T160 | 
4426 | 
7 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
6799 | 
0 | 
0 | 
| T94 | 
68583 | 
1297 | 
0 | 
0 | 
| T95 | 
93542 | 
840 | 
0 | 
0 | 
| T96 | 
17208 | 
116 | 
0 | 
0 | 
| T115 | 
5772 | 
121 | 
0 | 
0 | 
| T126 | 
269809 | 
641 | 
0 | 
0 | 
| T156 | 
20439 | 
33 | 
0 | 
0 | 
| T157 | 
13724 | 
22 | 
0 | 
0 | 
| T158 | 
104154 | 
469 | 
0 | 
0 | 
| T159 | 
9702 | 
39 | 
0 | 
0 | 
| T161 | 
15036 | 
125 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
8271 | 
0 | 
0 | 
| T94 | 
68583 | 
891 | 
0 | 
0 | 
| T95 | 
93542 | 
1418 | 
0 | 
0 | 
| T96 | 
17208 | 
281 | 
0 | 
0 | 
| T115 | 
5772 | 
9 | 
0 | 
0 | 
| T126 | 
269809 | 
636 | 
0 | 
0 | 
| T156 | 
20439 | 
60 | 
0 | 
0 | 
| T157 | 
13724 | 
211 | 
0 | 
0 | 
| T158 | 
104154 | 
467 | 
0 | 
0 | 
| T159 | 
9702 | 
161 | 
0 | 
0 | 
| T160 | 
4426 | 
135 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
7860 | 
0 | 
0 | 
| T94 | 
68583 | 
1571 | 
0 | 
0 | 
| T95 | 
93542 | 
1260 | 
0 | 
0 | 
| T96 | 
17208 | 
158 | 
0 | 
0 | 
| T109 | 
7452 | 
8 | 
0 | 
0 | 
| T115 | 
5772 | 
116 | 
0 | 
0 | 
| T126 | 
269809 | 
693 | 
0 | 
0 | 
| T156 | 
20439 | 
50 | 
0 | 
0 | 
| T157 | 
13724 | 
20 | 
0 | 
0 | 
| T158 | 
104154 | 
445 | 
0 | 
0 | 
| T159 | 
9702 | 
80 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
7571 | 
0 | 
0 | 
| T94 | 
68583 | 
1592 | 
0 | 
0 | 
| T95 | 
93542 | 
555 | 
0 | 
0 | 
| T96 | 
17208 | 
139 | 
0 | 
0 | 
| T115 | 
5772 | 
13 | 
0 | 
0 | 
| T126 | 
269809 | 
682 | 
0 | 
0 | 
| T156 | 
20439 | 
91 | 
0 | 
0 | 
| T157 | 
13724 | 
234 | 
0 | 
0 | 
| T158 | 
104154 | 
409 | 
0 | 
0 | 
| T159 | 
9702 | 
37 | 
0 | 
0 | 
| T160 | 
4426 | 
155 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4067 | 
0 | 
0 | 
| T94 | 
68583 | 
531 | 
0 | 
0 | 
| T95 | 
93542 | 
407 | 
0 | 
0 | 
| T96 | 
17208 | 
132 | 
0 | 
0 | 
| T115 | 
5772 | 
47 | 
0 | 
0 | 
| T126 | 
269809 | 
692 | 
0 | 
0 | 
| T156 | 
20439 | 
19 | 
0 | 
0 | 
| T157 | 
13724 | 
67 | 
0 | 
0 | 
| T158 | 
104154 | 
480 | 
0 | 
0 | 
| T159 | 
9702 | 
41 | 
0 | 
0 | 
| T160 | 
4426 | 
2 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
3917 | 
0 | 
0 | 
| T94 | 
68583 | 
316 | 
0 | 
0 | 
| T95 | 
93542 | 
373 | 
0 | 
0 | 
| T96 | 
17208 | 
78 | 
0 | 
0 | 
| T115 | 
5772 | 
12 | 
0 | 
0 | 
| T126 | 
269809 | 
619 | 
0 | 
0 | 
| T156 | 
20439 | 
66 | 
0 | 
0 | 
| T157 | 
13724 | 
100 | 
0 | 
0 | 
| T158 | 
104154 | 
450 | 
0 | 
0 | 
| T159 | 
9702 | 
31 | 
0 | 
0 | 
| T160 | 
4426 | 
49 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4224 | 
0 | 
0 | 
| T94 | 
68583 | 
370 | 
0 | 
0 | 
| T95 | 
93542 | 
496 | 
0 | 
0 | 
| T96 | 
17208 | 
128 | 
0 | 
0 | 
| T115 | 
5772 | 
3 | 
0 | 
0 | 
| T126 | 
269809 | 
625 | 
0 | 
0 | 
| T156 | 
20439 | 
70 | 
0 | 
0 | 
| T157 | 
13724 | 
127 | 
0 | 
0 | 
| T158 | 
104154 | 
435 | 
0 | 
0 | 
| T159 | 
9702 | 
45 | 
0 | 
0 | 
| T160 | 
4426 | 
55 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4786 | 
0 | 
0 | 
| T94 | 
68583 | 
749 | 
0 | 
0 | 
| T95 | 
93542 | 
482 | 
0 | 
0 | 
| T96 | 
17208 | 
100 | 
0 | 
0 | 
| T115 | 
5772 | 
56 | 
0 | 
0 | 
| T126 | 
269809 | 
644 | 
0 | 
0 | 
| T156 | 
20439 | 
34 | 
0 | 
0 | 
| T157 | 
13724 | 
109 | 
0 | 
0 | 
| T158 | 
104154 | 
435 | 
0 | 
0 | 
| T159 | 
9702 | 
49 | 
0 | 
0 | 
| T160 | 
4426 | 
48 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4389 | 
0 | 
0 | 
| T94 | 
68583 | 
539 | 
0 | 
0 | 
| T95 | 
93542 | 
342 | 
0 | 
0 | 
| T96 | 
17208 | 
151 | 
0 | 
0 | 
| T115 | 
5772 | 
54 | 
0 | 
0 | 
| T126 | 
269809 | 
677 | 
0 | 
0 | 
| T156 | 
20439 | 
41 | 
0 | 
0 | 
| T157 | 
13724 | 
41 | 
0 | 
0 | 
| T158 | 
104154 | 
445 | 
0 | 
0 | 
| T159 | 
9702 | 
24 | 
0 | 
0 | 
| T160 | 
4426 | 
40 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4259 | 
0 | 
0 | 
| T94 | 
68583 | 
423 | 
0 | 
0 | 
| T95 | 
93542 | 
372 | 
0 | 
0 | 
| T96 | 
17208 | 
168 | 
0 | 
0 | 
| T115 | 
5772 | 
43 | 
0 | 
0 | 
| T126 | 
269809 | 
636 | 
0 | 
0 | 
| T156 | 
20439 | 
36 | 
0 | 
0 | 
| T157 | 
13724 | 
83 | 
0 | 
0 | 
| T158 | 
104154 | 
458 | 
0 | 
0 | 
| T159 | 
9702 | 
45 | 
0 | 
0 | 
| T160 | 
4426 | 
6 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4482 | 
0 | 
0 | 
| T94 | 
68583 | 
570 | 
0 | 
0 | 
| T95 | 
93542 | 
297 | 
0 | 
0 | 
| T96 | 
17208 | 
109 | 
0 | 
0 | 
| T115 | 
5772 | 
43 | 
0 | 
0 | 
| T126 | 
269809 | 
689 | 
0 | 
0 | 
| T156 | 
20439 | 
42 | 
0 | 
0 | 
| T157 | 
13724 | 
125 | 
0 | 
0 | 
| T158 | 
104154 | 
520 | 
0 | 
0 | 
| T159 | 
9702 | 
5 | 
0 | 
0 | 
| T160 | 
4426 | 
4 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4792 | 
0 | 
0 | 
| T94 | 
68583 | 
664 | 
0 | 
0 | 
| T95 | 
93542 | 
392 | 
0 | 
0 | 
| T96 | 
17208 | 
146 | 
0 | 
0 | 
| T126 | 
269809 | 
630 | 
0 | 
0 | 
| T156 | 
20439 | 
43 | 
0 | 
0 | 
| T157 | 
13724 | 
108 | 
0 | 
0 | 
| T158 | 
104154 | 
464 | 
0 | 
0 | 
| T159 | 
9702 | 
26 | 
0 | 
0 | 
| T160 | 
4426 | 
57 | 
0 | 
0 | 
| T161 | 
15036 | 
99 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4279 | 
0 | 
0 | 
| T94 | 
68583 | 
620 | 
0 | 
0 | 
| T95 | 
93542 | 
394 | 
0 | 
0 | 
| T96 | 
17208 | 
185 | 
0 | 
0 | 
| T109 | 
7452 | 
3 | 
0 | 
0 | 
| T115 | 
5772 | 
1 | 
0 | 
0 | 
| T126 | 
269809 | 
703 | 
0 | 
0 | 
| T156 | 
20439 | 
64 | 
0 | 
0 | 
| T157 | 
13724 | 
24 | 
0 | 
0 | 
| T158 | 
104154 | 
427 | 
0 | 
0 | 
| T159 | 
9702 | 
41 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4398 | 
0 | 
0 | 
| T94 | 
68583 | 
556 | 
0 | 
0 | 
| T95 | 
93542 | 
471 | 
0 | 
0 | 
| T96 | 
17208 | 
127 | 
0 | 
0 | 
| T115 | 
5772 | 
13 | 
0 | 
0 | 
| T126 | 
269809 | 
636 | 
0 | 
0 | 
| T156 | 
20439 | 
50 | 
0 | 
0 | 
| T157 | 
13724 | 
109 | 
0 | 
0 | 
| T158 | 
104154 | 
398 | 
0 | 
0 | 
| T159 | 
9702 | 
1 | 
0 | 
0 | 
| T160 | 
4426 | 
36 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4259 | 
0 | 
0 | 
| T94 | 
68583 | 
646 | 
0 | 
0 | 
| T95 | 
93542 | 
348 | 
0 | 
0 | 
| T96 | 
17208 | 
110 | 
0 | 
0 | 
| T115 | 
5772 | 
42 | 
0 | 
0 | 
| T126 | 
269809 | 
704 | 
0 | 
0 | 
| T156 | 
20439 | 
126 | 
0 | 
0 | 
| T157 | 
13724 | 
56 | 
0 | 
0 | 
| T158 | 
104154 | 
441 | 
0 | 
0 | 
| T159 | 
9702 | 
43 | 
0 | 
0 | 
| T160 | 
4426 | 
56 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4251 | 
0 | 
0 | 
| T94 | 
68583 | 
527 | 
0 | 
0 | 
| T95 | 
93542 | 
339 | 
0 | 
0 | 
| T96 | 
17208 | 
127 | 
0 | 
0 | 
| T115 | 
5772 | 
6 | 
0 | 
0 | 
| T126 | 
269809 | 
623 | 
0 | 
0 | 
| T156 | 
20439 | 
117 | 
0 | 
0 | 
| T157 | 
13724 | 
109 | 
0 | 
0 | 
| T158 | 
104154 | 
463 | 
0 | 
0 | 
| T159 | 
9702 | 
24 | 
0 | 
0 | 
| T160 | 
4426 | 
8 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4564 | 
0 | 
0 | 
| T94 | 
68583 | 
568 | 
0 | 
0 | 
| T95 | 
93542 | 
358 | 
0 | 
0 | 
| T96 | 
17208 | 
145 | 
0 | 
0 | 
| T115 | 
5772 | 
6 | 
0 | 
0 | 
| T126 | 
269809 | 
650 | 
0 | 
0 | 
| T156 | 
20439 | 
92 | 
0 | 
0 | 
| T157 | 
13724 | 
119 | 
0 | 
0 | 
| T158 | 
104154 | 
467 | 
0 | 
0 | 
| T159 | 
9702 | 
72 | 
0 | 
0 | 
| T160 | 
4426 | 
66 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4329 | 
0 | 
0 | 
| T94 | 
68583 | 
525 | 
0 | 
0 | 
| T95 | 
93542 | 
399 | 
0 | 
0 | 
| T96 | 
17208 | 
64 | 
0 | 
0 | 
| T115 | 
5772 | 
10 | 
0 | 
0 | 
| T126 | 
269809 | 
622 | 
0 | 
0 | 
| T156 | 
20439 | 
22 | 
0 | 
0 | 
| T157 | 
13724 | 
48 | 
0 | 
0 | 
| T158 | 
104154 | 
438 | 
0 | 
0 | 
| T159 | 
9702 | 
14 | 
0 | 
0 | 
| T160 | 
4426 | 
48 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
3972 | 
0 | 
0 | 
| T94 | 
68583 | 
484 | 
0 | 
0 | 
| T95 | 
93542 | 
419 | 
0 | 
0 | 
| T96 | 
17208 | 
78 | 
0 | 
0 | 
| T115 | 
5772 | 
55 | 
0 | 
0 | 
| T126 | 
269809 | 
743 | 
0 | 
0 | 
| T156 | 
20439 | 
109 | 
0 | 
0 | 
| T157 | 
13724 | 
17 | 
0 | 
0 | 
| T158 | 
104154 | 
417 | 
0 | 
0 | 
| T159 | 
9702 | 
32 | 
0 | 
0 | 
| T160 | 
4426 | 
1 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4347 | 
0 | 
0 | 
| T94 | 
68583 | 
538 | 
0 | 
0 | 
| T95 | 
93542 | 
471 | 
0 | 
0 | 
| T96 | 
17208 | 
98 | 
0 | 
0 | 
| T115 | 
5772 | 
30 | 
0 | 
0 | 
| T126 | 
269809 | 
700 | 
0 | 
0 | 
| T156 | 
20439 | 
19 | 
0 | 
0 | 
| T157 | 
13724 | 
100 | 
0 | 
0 | 
| T158 | 
104154 | 
422 | 
0 | 
0 | 
| T159 | 
9702 | 
32 | 
0 | 
0 | 
| T160 | 
4426 | 
3 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4427 | 
0 | 
0 | 
| T94 | 
68583 | 
533 | 
0 | 
0 | 
| T95 | 
93542 | 
402 | 
0 | 
0 | 
| T96 | 
17208 | 
159 | 
0 | 
0 | 
| T103 | 
8346 | 
1 | 
0 | 
0 | 
| T115 | 
5772 | 
42 | 
0 | 
0 | 
| T126 | 
269809 | 
650 | 
0 | 
0 | 
| T156 | 
20439 | 
68 | 
0 | 
0 | 
| T157 | 
13724 | 
59 | 
0 | 
0 | 
| T158 | 
104154 | 
437 | 
0 | 
0 | 
| T159 | 
9702 | 
9 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4446 | 
0 | 
0 | 
| T94 | 
68583 | 
621 | 
0 | 
0 | 
| T95 | 
93542 | 
430 | 
0 | 
0 | 
| T96 | 
17208 | 
53 | 
0 | 
0 | 
| T115 | 
5772 | 
68 | 
0 | 
0 | 
| T126 | 
269809 | 
685 | 
0 | 
0 | 
| T156 | 
20439 | 
50 | 
0 | 
0 | 
| T157 | 
13724 | 
104 | 
0 | 
0 | 
| T158 | 
104154 | 
447 | 
0 | 
0 | 
| T159 | 
9702 | 
67 | 
0 | 
0 | 
| T160 | 
4426 | 
65 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4727 | 
0 | 
0 | 
| T94 | 
68583 | 
657 | 
0 | 
0 | 
| T95 | 
93542 | 
516 | 
0 | 
0 | 
| T96 | 
17208 | 
58 | 
0 | 
0 | 
| T115 | 
5772 | 
7 | 
0 | 
0 | 
| T126 | 
269809 | 
664 | 
0 | 
0 | 
| T156 | 
20439 | 
120 | 
0 | 
0 | 
| T157 | 
13724 | 
52 | 
0 | 
0 | 
| T158 | 
104154 | 
458 | 
0 | 
0 | 
| T159 | 
9702 | 
26 | 
0 | 
0 | 
| T160 | 
4426 | 
47 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4248 | 
0 | 
0 | 
| T94 | 
68583 | 
490 | 
0 | 
0 | 
| T95 | 
93542 | 
376 | 
0 | 
0 | 
| T96 | 
17208 | 
175 | 
0 | 
0 | 
| T115 | 
5772 | 
55 | 
0 | 
0 | 
| T126 | 
269809 | 
610 | 
0 | 
0 | 
| T156 | 
20439 | 
100 | 
0 | 
0 | 
| T157 | 
13724 | 
12 | 
0 | 
0 | 
| T158 | 
104154 | 
454 | 
0 | 
0 | 
| T159 | 
9702 | 
83 | 
0 | 
0 | 
| T160 | 
4426 | 
51 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4498 | 
0 | 
0 | 
| T94 | 
68583 | 
607 | 
0 | 
0 | 
| T95 | 
93542 | 
415 | 
0 | 
0 | 
| T96 | 
17208 | 
131 | 
0 | 
0 | 
| T115 | 
5772 | 
4 | 
0 | 
0 | 
| T126 | 
269809 | 
692 | 
0 | 
0 | 
| T156 | 
20439 | 
19 | 
0 | 
0 | 
| T157 | 
13724 | 
136 | 
0 | 
0 | 
| T158 | 
104154 | 
455 | 
0 | 
0 | 
| T159 | 
9702 | 
36 | 
0 | 
0 | 
| T160 | 
4426 | 
54 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4279 | 
0 | 
0 | 
| T94 | 
68583 | 
418 | 
0 | 
0 | 
| T95 | 
93542 | 
412 | 
0 | 
0 | 
| T96 | 
17208 | 
106 | 
0 | 
0 | 
| T115 | 
5772 | 
43 | 
0 | 
0 | 
| T126 | 
269809 | 
617 | 
0 | 
0 | 
| T156 | 
20439 | 
47 | 
0 | 
0 | 
| T157 | 
13724 | 
66 | 
0 | 
0 | 
| T158 | 
104154 | 
416 | 
0 | 
0 | 
| T159 | 
9702 | 
35 | 
0 | 
0 | 
| T160 | 
4426 | 
6 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4424 | 
0 | 
0 | 
| T94 | 
68583 | 
627 | 
0 | 
0 | 
| T95 | 
93542 | 
406 | 
0 | 
0 | 
| T96 | 
17208 | 
147 | 
0 | 
0 | 
| T115 | 
5772 | 
6 | 
0 | 
0 | 
| T126 | 
269809 | 
640 | 
0 | 
0 | 
| T156 | 
20439 | 
78 | 
0 | 
0 | 
| T157 | 
13724 | 
109 | 
0 | 
0 | 
| T158 | 
104154 | 
401 | 
0 | 
0 | 
| T159 | 
9702 | 
44 | 
0 | 
0 | 
| T160 | 
4426 | 
49 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
4348 | 
0 | 
0 | 
| T94 | 
68583 | 
607 | 
0 | 
0 | 
| T95 | 
93542 | 
596 | 
0 | 
0 | 
| T96 | 
17208 | 
64 | 
0 | 
0 | 
| T115 | 
5772 | 
49 | 
0 | 
0 | 
| T126 | 
269809 | 
696 | 
0 | 
0 | 
| T156 | 
20439 | 
51 | 
0 | 
0 | 
| T157 | 
13724 | 
95 | 
0 | 
0 | 
| T158 | 
104154 | 
437 | 
0 | 
0 | 
| T159 | 
9702 | 
79 | 
0 | 
0 | 
| T160 | 
4426 | 
1 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2488 | 
0 | 
0 | 
| T94 | 
68583 | 
96 | 
0 | 
0 | 
| T95 | 
93542 | 
103 | 
0 | 
0 | 
| T96 | 
17208 | 
12 | 
0 | 
0 | 
| T115 | 
5772 | 
14 | 
0 | 
0 | 
| T126 | 
269809 | 
708 | 
0 | 
0 | 
| T156 | 
20439 | 
76 | 
0 | 
0 | 
| T157 | 
13724 | 
27 | 
0 | 
0 | 
| T158 | 
104154 | 
461 | 
0 | 
0 | 
| T159 | 
9702 | 
9 | 
0 | 
0 | 
| T160 | 
4426 | 
5 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2460 | 
0 | 
0 | 
| T94 | 
68583 | 
120 | 
0 | 
0 | 
| T95 | 
93542 | 
132 | 
0 | 
0 | 
| T96 | 
17208 | 
22 | 
0 | 
0 | 
| T115 | 
5772 | 
8 | 
0 | 
0 | 
| T126 | 
269809 | 
664 | 
0 | 
0 | 
| T156 | 
20439 | 
61 | 
0 | 
0 | 
| T157 | 
13724 | 
32 | 
0 | 
0 | 
| T158 | 
104154 | 
461 | 
0 | 
0 | 
| T159 | 
9702 | 
4 | 
0 | 
0 | 
| T160 | 
4426 | 
3 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2420 | 
0 | 
0 | 
| T94 | 
68583 | 
75 | 
0 | 
0 | 
| T95 | 
93542 | 
136 | 
0 | 
0 | 
| T96 | 
17208 | 
32 | 
0 | 
0 | 
| T109 | 
7452 | 
10 | 
0 | 
0 | 
| T115 | 
5772 | 
6 | 
0 | 
0 | 
| T126 | 
269809 | 
708 | 
0 | 
0 | 
| T156 | 
20439 | 
60 | 
0 | 
0 | 
| T157 | 
13724 | 
21 | 
0 | 
0 | 
| T158 | 
104154 | 
411 | 
0 | 
0 | 
| T159 | 
9702 | 
16 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2503 | 
0 | 
0 | 
| T94 | 
68583 | 
70 | 
0 | 
0 | 
| T95 | 
93542 | 
92 | 
0 | 
0 | 
| T96 | 
17208 | 
38 | 
0 | 
0 | 
| T115 | 
5772 | 
11 | 
0 | 
0 | 
| T126 | 
269809 | 
654 | 
0 | 
0 | 
| T156 | 
20439 | 
94 | 
0 | 
0 | 
| T157 | 
13724 | 
30 | 
0 | 
0 | 
| T158 | 
104154 | 
491 | 
0 | 
0 | 
| T159 | 
9702 | 
10 | 
0 | 
0 | 
| T160 | 
4426 | 
1 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2782 | 
0 | 
0 | 
| T94 | 
68583 | 
214 | 
0 | 
0 | 
| T95 | 
93542 | 
146 | 
0 | 
0 | 
| T96 | 
17208 | 
30 | 
0 | 
0 | 
| T115 | 
5772 | 
3 | 
0 | 
0 | 
| T126 | 
269809 | 
699 | 
0 | 
0 | 
| T156 | 
20439 | 
50 | 
0 | 
0 | 
| T157 | 
13724 | 
36 | 
0 | 
0 | 
| T158 | 
104154 | 
427 | 
0 | 
0 | 
| T159 | 
9702 | 
9 | 
0 | 
0 | 
| T160 | 
4426 | 
3 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
3949 | 
0 | 
0 | 
| T13 | 
557357 | 
11 | 
0 | 
0 | 
| T21 | 
0 | 
51 | 
0 | 
0 | 
| T22 | 
75693 | 
0 | 
0 | 
0 | 
| T23 | 
250479 | 
0 | 
0 | 
0 | 
| T24 | 
278065 | 
0 | 
0 | 
0 | 
| T25 | 
13089 | 
0 | 
0 | 
0 | 
| T26 | 
1263 | 
0 | 
0 | 
0 | 
| T27 | 
24129 | 
0 | 
0 | 
0 | 
| T28 | 
126440 | 
0 | 
0 | 
0 | 
| T29 | 
640 | 
0 | 
0 | 
0 | 
| T30 | 
205697 | 
0 | 
0 | 
0 | 
| T146 | 
0 | 
16 | 
0 | 
0 | 
| T162 | 
0 | 
23 | 
0 | 
0 | 
| T163 | 
0 | 
6 | 
0 | 
0 | 
| T164 | 
0 | 
36 | 
0 | 
0 | 
| T165 | 
0 | 
24 | 
0 | 
0 | 
| T166 | 
0 | 
37 | 
0 | 
0 | 
| T167 | 
0 | 
29 | 
0 | 
0 | 
| T168 | 
0 | 
40 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2300 | 
0 | 
0 | 
| T94 | 
68583 | 
108 | 
0 | 
0 | 
| T95 | 
93542 | 
95 | 
0 | 
0 | 
| T96 | 
17208 | 
49 | 
0 | 
0 | 
| T115 | 
5772 | 
10 | 
0 | 
0 | 
| T126 | 
269809 | 
644 | 
0 | 
0 | 
| T156 | 
20439 | 
71 | 
0 | 
0 | 
| T157 | 
13724 | 
12 | 
0 | 
0 | 
| T158 | 
104154 | 
456 | 
0 | 
0 | 
| T159 | 
9702 | 
6 | 
0 | 
0 | 
| T160 | 
4426 | 
9 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2461 | 
0 | 
0 | 
| T94 | 
68583 | 
134 | 
0 | 
0 | 
| T95 | 
93542 | 
92 | 
0 | 
0 | 
| T96 | 
17208 | 
40 | 
0 | 
0 | 
| T115 | 
5772 | 
12 | 
0 | 
0 | 
| T126 | 
269809 | 
666 | 
0 | 
0 | 
| T156 | 
20439 | 
38 | 
0 | 
0 | 
| T157 | 
13724 | 
33 | 
0 | 
0 | 
| T158 | 
104154 | 
456 | 
0 | 
0 | 
| T159 | 
9702 | 
5 | 
0 | 
0 | 
| T160 | 
4426 | 
5 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2336 | 
0 | 
0 | 
| T94 | 
68583 | 
76 | 
0 | 
0 | 
| T95 | 
93542 | 
48 | 
0 | 
0 | 
| T96 | 
17208 | 
21 | 
0 | 
0 | 
| T115 | 
5772 | 
11 | 
0 | 
0 | 
| T126 | 
269809 | 
679 | 
0 | 
0 | 
| T156 | 
20439 | 
99 | 
0 | 
0 | 
| T157 | 
13724 | 
14 | 
0 | 
0 | 
| T158 | 
104154 | 
454 | 
0 | 
0 | 
| T159 | 
9702 | 
5 | 
0 | 
0 | 
| T160 | 
4426 | 
5 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2440 | 
0 | 
0 | 
| T94 | 
68583 | 
70 | 
0 | 
0 | 
| T95 | 
93542 | 
71 | 
0 | 
0 | 
| T96 | 
17208 | 
26 | 
0 | 
0 | 
| T115 | 
5772 | 
7 | 
0 | 
0 | 
| T126 | 
269809 | 
701 | 
0 | 
0 | 
| T156 | 
20439 | 
121 | 
0 | 
0 | 
| T157 | 
13724 | 
16 | 
0 | 
0 | 
| T158 | 
104154 | 
499 | 
0 | 
0 | 
| T159 | 
9702 | 
8 | 
0 | 
0 | 
| T160 | 
4426 | 
8 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2244 | 
0 | 
0 | 
| T94 | 
68583 | 
73 | 
0 | 
0 | 
| T95 | 
93542 | 
74 | 
0 | 
0 | 
| T96 | 
17208 | 
28 | 
0 | 
0 | 
| T115 | 
5772 | 
4 | 
0 | 
0 | 
| T126 | 
269809 | 
665 | 
0 | 
0 | 
| T156 | 
20439 | 
48 | 
0 | 
0 | 
| T157 | 
13724 | 
27 | 
0 | 
0 | 
| T158 | 
104154 | 
474 | 
0 | 
0 | 
| T159 | 
9702 | 
8 | 
0 | 
0 | 
| T160 | 
4426 | 
3 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2411 | 
0 | 
0 | 
| T94 | 
68583 | 
86 | 
0 | 
0 | 
| T95 | 
93542 | 
44 | 
0 | 
0 | 
| T96 | 
17208 | 
24 | 
0 | 
0 | 
| T115 | 
5772 | 
7 | 
0 | 
0 | 
| T126 | 
269809 | 
685 | 
0 | 
0 | 
| T156 | 
20439 | 
62 | 
0 | 
0 | 
| T157 | 
13724 | 
30 | 
0 | 
0 | 
| T158 | 
104154 | 
518 | 
0 | 
0 | 
| T159 | 
9702 | 
4 | 
0 | 
0 | 
| T160 | 
4426 | 
2 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2784 | 
0 | 
0 | 
| T94 | 
68583 | 
193 | 
0 | 
0 | 
| T95 | 
93542 | 
160 | 
0 | 
0 | 
| T96 | 
17208 | 
52 | 
0 | 
0 | 
| T115 | 
5772 | 
36 | 
0 | 
0 | 
| T126 | 
269809 | 
696 | 
0 | 
0 | 
| T156 | 
20439 | 
63 | 
0 | 
0 | 
| T157 | 
13724 | 
68 | 
0 | 
0 | 
| T158 | 
104154 | 
383 | 
0 | 
0 | 
| T159 | 
9702 | 
5 | 
0 | 
0 | 
| T160 | 
4426 | 
7 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2234 | 
0 | 
0 | 
| T94 | 
68583 | 
60 | 
0 | 
0 | 
| T95 | 
93542 | 
89 | 
0 | 
0 | 
| T96 | 
17208 | 
21 | 
0 | 
0 | 
| T109 | 
7452 | 
6 | 
0 | 
0 | 
| T115 | 
5772 | 
8 | 
0 | 
0 | 
| T126 | 
269809 | 
689 | 
0 | 
0 | 
| T156 | 
20439 | 
108 | 
0 | 
0 | 
| T157 | 
13724 | 
31 | 
0 | 
0 | 
| T158 | 
104154 | 
411 | 
0 | 
0 | 
| T159 | 
9702 | 
7 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
3186 | 
0 | 
0 | 
| T94 | 
68583 | 
263 | 
0 | 
0 | 
| T95 | 
93542 | 
181 | 
0 | 
0 | 
| T96 | 
17208 | 
78 | 
0 | 
0 | 
| T115 | 
5772 | 
7 | 
0 | 
0 | 
| T126 | 
269809 | 
673 | 
0 | 
0 | 
| T156 | 
20439 | 
58 | 
0 | 
0 | 
| T157 | 
13724 | 
54 | 
0 | 
0 | 
| T158 | 
104154 | 
471 | 
0 | 
0 | 
| T159 | 
9702 | 
23 | 
0 | 
0 | 
| T160 | 
4426 | 
10 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2386 | 
0 | 
0 | 
| T94 | 
68583 | 
109 | 
0 | 
0 | 
| T95 | 
93542 | 
104 | 
0 | 
0 | 
| T96 | 
17208 | 
31 | 
0 | 
0 | 
| T115 | 
5772 | 
10 | 
0 | 
0 | 
| T126 | 
269809 | 
656 | 
0 | 
0 | 
| T156 | 
20439 | 
36 | 
0 | 
0 | 
| T157 | 
13724 | 
26 | 
0 | 
0 | 
| T158 | 
104154 | 
401 | 
0 | 
0 | 
| T159 | 
9702 | 
14 | 
0 | 
0 | 
| T161 | 
15036 | 
24 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2325 | 
0 | 
0 | 
| T94 | 
68583 | 
58 | 
0 | 
0 | 
| T95 | 
93542 | 
52 | 
0 | 
0 | 
| T96 | 
17208 | 
34 | 
0 | 
0 | 
| T115 | 
5772 | 
10 | 
0 | 
0 | 
| T126 | 
269809 | 
714 | 
0 | 
0 | 
| T156 | 
20439 | 
60 | 
0 | 
0 | 
| T157 | 
13724 | 
16 | 
0 | 
0 | 
| T158 | 
104154 | 
471 | 
0 | 
0 | 
| T159 | 
9702 | 
6 | 
0 | 
0 | 
| T160 | 
4426 | 
9 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2311 | 
0 | 
0 | 
| T94 | 
68583 | 
102 | 
0 | 
0 | 
| T95 | 
93542 | 
57 | 
0 | 
0 | 
| T96 | 
17208 | 
16 | 
0 | 
0 | 
| T115 | 
5772 | 
12 | 
0 | 
0 | 
| T126 | 
269809 | 
656 | 
0 | 
0 | 
| T156 | 
20439 | 
97 | 
0 | 
0 | 
| T157 | 
13724 | 
19 | 
0 | 
0 | 
| T158 | 
104154 | 
457 | 
0 | 
0 | 
| T159 | 
9702 | 
11 | 
0 | 
0 | 
| T160 | 
4426 | 
1 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2261 | 
0 | 
0 | 
| T94 | 
68583 | 
82 | 
0 | 
0 | 
| T95 | 
93542 | 
65 | 
0 | 
0 | 
| T96 | 
17208 | 
24 | 
0 | 
0 | 
| T115 | 
5772 | 
8 | 
0 | 
0 | 
| T126 | 
269809 | 
673 | 
0 | 
0 | 
| T156 | 
20439 | 
72 | 
0 | 
0 | 
| T157 | 
13724 | 
35 | 
0 | 
0 | 
| T158 | 
104154 | 
431 | 
0 | 
0 | 
| T159 | 
9702 | 
20 | 
0 | 
0 | 
| T160 | 
4426 | 
5 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2182 | 
0 | 
0 | 
| T94 | 
68583 | 
62 | 
0 | 
0 | 
| T95 | 
93542 | 
69 | 
0 | 
0 | 
| T96 | 
17208 | 
30 | 
0 | 
0 | 
| T115 | 
5772 | 
8 | 
0 | 
0 | 
| T126 | 
269809 | 
682 | 
0 | 
0 | 
| T156 | 
20439 | 
49 | 
0 | 
0 | 
| T157 | 
13724 | 
17 | 
0 | 
0 | 
| T158 | 
104154 | 
370 | 
0 | 
0 | 
| T159 | 
9702 | 
13 | 
0 | 
0 | 
| T160 | 
4426 | 
5 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2238 | 
0 | 
0 | 
| T94 | 
68583 | 
67 | 
0 | 
0 | 
| T95 | 
93542 | 
55 | 
0 | 
0 | 
| T96 | 
17208 | 
19 | 
0 | 
0 | 
| T115 | 
5772 | 
3 | 
0 | 
0 | 
| T126 | 
269809 | 
701 | 
0 | 
0 | 
| T156 | 
20439 | 
65 | 
0 | 
0 | 
| T157 | 
13724 | 
15 | 
0 | 
0 | 
| T158 | 
104154 | 
408 | 
0 | 
0 | 
| T159 | 
9702 | 
6 | 
0 | 
0 | 
| T160 | 
4426 | 
6 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
428484138 | 
2149 | 
0 | 
0 | 
| T94 | 
68583 | 
91 | 
0 | 
0 | 
| T95 | 
93542 | 
31 | 
0 | 
0 | 
| T96 | 
17208 | 
7 | 
0 | 
0 | 
| T115 | 
5772 | 
8 | 
0 | 
0 | 
| T126 | 
269809 | 
707 | 
0 | 
0 | 
| T156 | 
20439 | 
53 | 
0 | 
0 | 
| T157 | 
13724 | 
8 | 
0 | 
0 | 
| T158 | 
104154 | 
358 | 
0 | 
0 | 
| T159 | 
9702 | 
10 | 
0 | 
0 | 
| T160 | 
4426 | 
4 | 
0 | 
0 |