Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3730292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4354424

1

T1

872

T2

893

T3

2836

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4453715	1			T1	2		T2	5		T3	2377
values[0x0]	1816041	1			T1	461		T2	446		T3	834
values[0x1]	1814960	1			T1	413		T2	445		T3	818

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2641328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5443388

1

T1

872

T2

894

T3

3070

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30723	1			T1	5		T2	3		T3	16
valid_sources[0x01]	32184	1			T1	3		T2	3		T3	15
valid_sources[0x02]	30021	1			T1	7		T2	6		T3	6
valid_sources[0x03]	30349	1			T1	2		T2	13		T3	16
valid_sources[0x04]	29392	1			T2	1		T3	16		T4	254
valid_sources[0x05]	29040	1			T2	4		T3	23		T6	13
valid_sources[0x06]	30188	1			T1	2		T2	1		T3	17
valid_sources[0x07]	29825	1			T1	3		T2	10		T3	13
valid_sources[0x08]	37569	1			T3	27		T6	8		T8	9
valid_sources[0x09]	31138	1			T2	7		T3	23		T6	7
valid_sources[0x0a]	29651	1			T1	9		T2	1		T3	17
valid_sources[0x0b]	34341	1			T1	4		T2	8		T3	20
valid_sources[0x0c]	31288	1			T1	2		T2	5		T3	17
valid_sources[0x0d]	30549	1			T1	7		T2	2		T3	23
valid_sources[0x0e]	33707	1			T3	13		T6	12		T7	1
valid_sources[0x0f]	28716	1			T1	1		T3	25		T6	22
valid_sources[0x10]	31781	1			T1	4		T3	17		T6	15
valid_sources[0x11]	31305	1			T1	3		T2	5		T3	13
valid_sources[0x12]	28346	1			T1	5		T2	2		T3	8
valid_sources[0x13]	29046	1			T1	9		T2	4		T3	14
valid_sources[0x14]	29894	1			T1	12		T2	5		T3	16
valid_sources[0x15]	43849	1			T1	1		T3	17		T4	255
valid_sources[0x16]	27360	1			T1	4		T2	3		T3	19
valid_sources[0x17]	28588	1			T1	1		T2	1		T3	6
valid_sources[0x18]	30706	1			T2	7		T3	20		T6	7
valid_sources[0x19]	29850	1			T1	3		T2	2		T3	19
valid_sources[0x1a]	31539	1			T1	3		T2	3		T3	20
valid_sources[0x1b]	30826	1			T1	3		T2	6		T3	10
valid_sources[0x1c]	34540	1			T1	2		T2	4		T3	10
valid_sources[0x1d]	28729	1			T1	7		T2	9		T3	9
valid_sources[0x1e]	30783	1			T1	13		T3	22		T6	7
valid_sources[0x1f]	33263	1			T1	1		T2	5		T3	9
valid_sources[0x20]	33577	1			T1	1		T2	9		T3	10
valid_sources[0x21]	31981	1			T1	3		T2	3		T3	25
valid_sources[0x22]	32224	1			T1	6		T2	1		T3	20
valid_sources[0x23]	34092	1			T1	7		T2	3		T3	12
valid_sources[0x24]	30054	1			T1	1		T2	4		T3	19
valid_sources[0x25]	29045	1			T1	4		T2	2		T3	25
valid_sources[0x26]	29074	1			T1	1		T2	3		T3	14
valid_sources[0x27]	38291	1			T1	3		T2	2		T3	13
valid_sources[0x28]	27823	1			T1	5		T2	3		T3	21
valid_sources[0x29]	34565	1			T1	4		T2	9		T3	11
valid_sources[0x2a]	46320	1			T1	4		T2	1		T3	13
valid_sources[0x2b]	28966	1			T2	2		T3	15		T6	8
valid_sources[0x2c]	31123	1			T1	9		T2	4		T3	9
valid_sources[0x2d]	29332	1			T1	2		T2	6		T3	23
valid_sources[0x2e]	32291	1			T1	5		T2	1		T3	9
valid_sources[0x2f]	30283	1			T1	2		T2	2		T3	14
valid_sources[0x30]	29836	1			T1	1		T2	5		T3	27
valid_sources[0x31]	33695	1			T2	2		T3	14		T6	11
valid_sources[0x32]	31770	1			T1	1		T2	8		T3	18
valid_sources[0x33]	30718	1			T1	3		T2	4		T3	14
valid_sources[0x34]	33789	1			T1	5		T2	7		T3	24
valid_sources[0x35]	31825	1			T1	5		T2	4		T3	10
valid_sources[0x36]	31033	1			T1	2		T2	3		T3	12
valid_sources[0x37]	29170	1			T2	4		T3	14		T4	271
valid_sources[0x38]	33637	1			T1	3		T3	12		T6	14
valid_sources[0x39]	29847	1			T1	3		T2	8		T3	18
valid_sources[0x3a]	32530	1			T2	4		T3	8		T4	3
valid_sources[0x3b]	30439	1			T1	6		T2	8		T3	14
valid_sources[0x3c]	32027	1			T1	3		T3	8		T4	65
valid_sources[0x3d]	31679	1			T1	2		T2	2		T3	17
valid_sources[0x3e]	29644	1			T2	1		T3	14		T6	7
valid_sources[0x3f]	36641	1			T1	2		T2	3		T3	21
valid_sources[0x40]	30449	1			T1	1		T2	4		T3	13
valid_sources[0x41]	28393	1			T1	1		T2	4		T3	24
valid_sources[0x42]	29593	1			T2	5		T3	4		T6	10
valid_sources[0x43]	31920	1			T1	5		T2	8		T3	10
valid_sources[0x44]	28920	1			T1	2		T2	2		T3	24
valid_sources[0x45]	32415	1			T1	1		T2	4		T3	39
valid_sources[0x46]	28955	1			T1	3		T2	3		T3	10
valid_sources[0x47]	36686	1			T1	4		T2	2		T3	12
valid_sources[0x48]	28775	1			T1	3		T3	12		T4	148
valid_sources[0x49]	33635	1			T1	7		T2	6		T3	10
valid_sources[0x4a]	32953	1			T1	5		T2	4		T3	18
valid_sources[0x4b]	31077	1			T1	5		T2	5		T3	8
valid_sources[0x4c]	30688	1			T1	6		T2	7		T3	11
valid_sources[0x4d]	29267	1			T1	6		T2	2		T3	5
valid_sources[0x4e]	27439	1			T1	1		T2	2		T3	10
valid_sources[0x4f]	30292	1			T1	11		T2	1		T3	19
valid_sources[0x50]	30864	1			T1	2		T2	7		T3	12
valid_sources[0x51]	31034	1			T2	3		T3	19		T6	7
valid_sources[0x52]	36040	1			T2	8		T3	6		T6	17
valid_sources[0x53]	27886	1			T2	2		T3	37		T6	12
valid_sources[0x54]	30509	1			T1	8		T3	24		T6	7
valid_sources[0x55]	30880	1			T1	2		T2	6		T3	9
valid_sources[0x56]	29536	1			T1	8		T2	3		T3	28
valid_sources[0x57]	33892	1			T1	9		T2	4		T3	14
valid_sources[0x58]	31443	1			T1	1		T2	1		T3	9
valid_sources[0x59]	32039	1			T1	11		T2	3		T3	7
valid_sources[0x5a]	31277	1			T1	4		T2	4		T3	13
valid_sources[0x5b]	34152	1			T1	5		T2	1		T3	18
valid_sources[0x5c]	31428	1			T1	3		T2	5		T3	12
valid_sources[0x5d]	30456	1			T1	1		T2	7		T3	11
valid_sources[0x5e]	28865	1			T1	3		T2	1		T3	12
valid_sources[0x5f]	31696	1			T1	1		T2	2		T3	12
valid_sources[0x60]	28376	1			T1	6		T3	26		T6	7
valid_sources[0x61]	30626	1			T1	8		T2	8		T3	13
valid_sources[0x62]	30855	1			T1	2		T3	9		T6	11
valid_sources[0x63]	30908	1			T2	3		T3	25		T6	11
valid_sources[0x64]	30756	1			T1	3		T2	6		T3	10
valid_sources[0x65]	30582	1			T1	6		T2	1		T3	15
valid_sources[0x66]	29925	1			T1	9		T3	21		T6	6
valid_sources[0x67]	37158	1			T1	2		T2	7		T3	13
valid_sources[0x68]	29164	1			T1	4		T2	3		T3	20
valid_sources[0x69]	29829	1			T1	2		T2	5		T3	5
valid_sources[0x6a]	32287	1			T1	2		T2	2		T3	27
valid_sources[0x6b]	29517	1			T1	1		T2	5		T3	21
valid_sources[0x6c]	29231	1			T2	2		T3	3		T6	11
valid_sources[0x6d]	34174	1			T2	7		T3	17		T6	11
valid_sources[0x6e]	31207	1			T1	5		T2	5		T3	14
valid_sources[0x6f]	33901	1			T1	5		T2	7		T3	12
valid_sources[0x70]	31338	1			T1	4		T2	2		T3	14
valid_sources[0x71]	35796	1			T1	6		T2	2		T3	17
valid_sources[0x72]	31224	1			T1	8		T2	3		T3	25
valid_sources[0x73]	31401	1			T1	2		T2	1		T3	16
valid_sources[0x74]	35377	1			T1	3		T2	4		T3	19
valid_sources[0x75]	29360	1			T2	6		T3	18		T6	7
valid_sources[0x76]	31511	1			T2	4		T3	12		T6	14
valid_sources[0x77]	31707	1			T1	9		T2	1		T3	25
valid_sources[0x78]	31550	1			T1	5		T2	8		T3	11
valid_sources[0x79]	30035	1			T1	1		T2	6		T3	20
valid_sources[0x7a]	29394	1			T2	1		T3	19		T6	14
valid_sources[0x7b]	30356	1			T1	1		T2	11		T3	23
valid_sources[0x7c]	30214	1			T1	6		T2	6		T3	10
valid_sources[0x7d]	31897	1			T3	12		T6	15		T8	9
valid_sources[0x7e]	29899	1			T1	8		T3	5		T4	1
valid_sources[0x7f]	29898	1			T1	2		T2	1		T3	15
valid_sources[0x80]	33644	1			T1	3		T2	1		T3	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1066554

1

T1

1

T2

3

T3

1191

values[0x0]

all_enables

biggest_size

1656895

1

T1

459

T2

445

T3

832

values[0x1]

all_enables

biggest_size

1630975

1

T1

412

T2

445

T3

813