Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3748041

1

T1

4

T2

3

T3

1193

full_word

4353536

1

T1

872

T2

893

T3

2836

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8101157	1			T1	876		T2	896		T3	4029
auto[TlIntgErrCmd]	143	1			T102	11		T106	8		T107	7
auto[TlIntgErrData]	140	1			T102	9		T106	7		T107	7
auto[TlIntgErrBoth]	137	1			T102	10		T106	5		T107	16

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4455841

1

T1

2

T2

5

T3

2377

auto[1]

3645736

1

T1

874

T2

891

T3

1652

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3388937	1			T1	1		T2	2		T3	1186
auto[TlIntgErrNone]	partial	auto[1]	358724	1			T1	3		T2	1		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	1066696	1			T1	1		T2	3		T3	1191
auto[TlIntgErrNone]	full_word	auto[1]	3286800	1			T1	871		T2	890		T3	1645
auto[TlIntgErrCmd]	partial	auto[0]	69	1			T102	4		T106	3		T107	6
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T102	6		T106	2		T107	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T102	1		T124	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T106	3		T124	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T102	5		T106	5		T107	3
auto[TlIntgErrData]	partial	auto[1]	63	1			T102	1		T107	3		T123	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T102	2		T106	1		T160	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T102	1		T106	1		T107	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T102	6		T106	2		T107	7
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T102	3		T106	2		T107	9
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T102	1		T106	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T123	1		T186	1		T190	1