Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T10,T14
1	0	Covered	T3,T10,T14
1	1	Covered	T3,T10,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T14
1	0	Covered	T3,T10,T14
1	1	Covered	T3,T10,T14

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1394873385	2638	0	0
SrcPulseCheck_M	464687040	2638	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394873385	2638	0	0
T3	141552	6	0	0
T4	1541914	0	0	0
T5	13926	0	0	0
T6	85038	0	0	0
T7	77986	0	0	0
T8	125090	0	0	0
T9	627156	0	0	0
T10	847986	15	0	0
T11	28200	0	0	0
T12	205150	0	0	0
T13	675891	0	0	0
T14	363568	9	0	0
T15	0	10	0	0
T23	1463	0	0	0
T26	0	3	0	0
T27	0	14	0	0
T30	29733	0	0	0
T31	70509	0	0	0
T32	0	2	0	0
T33	0	12	0	0
T37	0	19	0	0
T42	0	7	0	0
T43	0	1	0	0
T44	0	4	0	0
T45	0	4	0	0
T46	0	5	0	0
T64	0	7	0	0
T85	1355	0	0	0
T86	1757	0	0	0
T93	0	5	0	0
T154	0	2	0	0
T155	0	7	0	0
T156	0	7	0	0
T157	0	7	0	0
T158	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	464687040	2638	0	0
T3	32222	6	0	0
T4	262958	0	0	0
T5	1662	0	0	0
T6	26368	0	0	0
T7	69216	0	0	0
T8	29144	0	0	0
T9	103456	0	0	0
T10	1187505	15	0	0
T11	6474	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	9	0	0
T15	789119	10	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	3	0	0
T27	0	14	0	0
T30	3576	0	0	0
T31	124457	0	0	0
T32	0	2	0	0
T33	0	12	0	0
T37	0	19	0	0
T42	0	7	0	0
T43	0	1	0	0
T44	0	4	0	0
T45	0	4	0	0
T46	0	5	0	0
T64	0	7	0	0
T93	0	5	0	0
T154	0	2	0	0
T155	0	7	0	0
T156	0	7	0	0
T157	0	7	0	0
T158	0	5	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T43,T44
1	0	Covered	T3,T43,T44
1	1	Covered	T3,T44,T45

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T43,T44
1	0	Covered	T3,T44,T45
1	1	Covered	T3,T43,T44

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	464957795	151	0	0
SrcPulseCheck_M	154895680	151	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	151	0	0
T3	70776	3	0	0
T4	770957	0	0	0
T5	6963	0	0	0
T6	42519	0	0	0
T7	38993	0	0	0
T8	62545	0	0	0
T9	313578	0	0	0
T10	282662	0	0	0
T11	9400	0	0	0
T30	9911	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T64	0	2	0	0
T93	0	3	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	151	0	0
T3	16111	3	0	0
T4	131479	0	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	0	0	0
T30	1192	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T64	0	2	0	0
T93	0	3	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T44,T45
1	0	Covered	T3,T44,T45
1	1	Covered	T3,T44,T45

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T44,T45
1	0	Covered	T3,T44,T45
1	1	Covered	T3,T44,T45

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	464957795	288	0	0
SrcPulseCheck_M	154895680	288	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	288	0	0
T3	70776	3	0	0
T4	770957	0	0	0
T5	6963	0	0	0
T6	42519	0	0	0
T7	38993	0	0	0
T8	62545	0	0	0
T9	313578	0	0	0
T10	282662	0	0	0
T11	9400	0	0	0
T30	9911	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T64	0	5	0	0
T93	0	2	0	0
T154	0	1	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	5	0	0
T158	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	288	0	0
T3	16111	3	0	0
T4	131479	0	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	0	0	0
T30	1192	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T64	0	5	0	0
T93	0	2	0	0
T154	0	1	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	5	0	0
T158	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T14,T15
1	1	Covered	T10,T14,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T14,T15
1	1	Covered	T10,T14,T15

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	464957795	2199	0	0
SrcPulseCheck_M	154895680	2199	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2199	0	0
T10	282662	15	0	0
T11	9400	0	0	0
T12	205150	0	0	0
T13	675891	0	0	0
T14	363568	9	0	0
T15	0	10	0	0
T23	1463	0	0	0
T26	0	3	0	0
T27	0	14	0	0
T30	9911	0	0	0
T31	70509	0	0	0
T32	0	2	0	0
T33	0	12	0	0
T37	0	19	0	0
T42	0	7	0	0
T46	0	5	0	0
T85	1355	0	0	0
T86	1757	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	2199	0	0
T10	395835	15	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	9	0	0
T15	789119	10	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	3	0	0
T27	0	14	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	2	0	0
T33	0	12	0	0
T37	0	19	0	0
T42	0	7	0	0
T46	0	5	0	0