Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467351143	2950737	0	0
DepthKnown_A	467351143	467214626	0	0
RvalidKnown_A	467351143	467214626	0	0
WreadyKnown_A	467351143	467214626	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	2950737	0	0
T1	2853	1664	0	0
T2	477269	1663	0	0
T3	70776	3196	0	0
T4	770957	0	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	1668	0	0
T9	313578	1663	0	0
T10	282662	12485	0	0
T12	0	832	0	0
T13	0	1669	0	0
T14	0	14145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467351143	3223610	0	0
DepthKnown_A	467351143	467214626	0	0
RvalidKnown_A	467351143	467214626	0	0
WreadyKnown_A	467351143	467214626	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	3223610	0	0
T1	2853	834	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	0	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	837	0	0
T9	313578	832	0	0
T10	282662	13435	0	0
T12	0	832	0	0
T13	0	838	0	0
T14	0	24240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467351143	188359	0	0
DepthKnown_A	467351143	467214626	0	0
RvalidKnown_A	467351143	467214626	0	0
WreadyKnown_A	467351143	467214626	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	188359	0	0
T4	770957	912	0	0
T5	6963	0	0	0
T6	42519	0	0	0
T7	38993	0	0	0
T8	62545	0	0	0
T9	313578	0	0	0
T10	282662	225	0	0
T11	9400	30	0	0
T12	205150	0	0	0
T14	0	1516	0	0
T15	0	320	0	0
T23	0	100	0	0
T26	0	84	0	0
T27	0	400	0	0
T30	9911	0	0	0
T32	0	673	0	0
T33	0	1055	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467351143	418314	0	0
DepthKnown_A	467351143	467214626	0	0
RvalidKnown_A	467351143	467214626	0	0
WreadyKnown_A	467351143	467214626	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	418314	0	0
T4	770957	912	0	0
T5	6963	0	0	0
T6	42519	0	0	0
T7	38993	0	0	0
T8	62545	0	0	0
T9	313578	0	0	0
T10	282662	754	0	0
T11	9400	30	0	0
T12	205150	0	0	0
T14	0	6900	0	0
T15	0	320	0	0
T23	0	100	0	0
T26	0	417	0	0
T27	0	1897	0	0
T30	9911	0	0	0
T32	0	3069	0	0
T33	0	2347	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467351143	6344267	0	0
DepthKnown_A	467351143	467214626	0	0
RvalidKnown_A	467351143	467214626	0	0
WreadyKnown_A	467351143	467214626	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	6344267	0	0
T1	2853	44	0	0
T2	477269	64	0	0
T3	70776	2429	0	0
T4	770957	13680	0	0
T5	6963	29	0	0
T6	42519	1840	0	0
T7	38993	202	0	0
T8	62545	2158	0	0
T9	313578	50	0	0
T10	282662	4849	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467351143	13453993	0	0
DepthKnown_A	467351143	467214626	0	0
RvalidKnown_A	467351143	467214626	0	0
WreadyKnown_A	467351143	467214626	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	13453993	0	0
T1	2853	212	0	0
T2	477269	64	0	0
T3	70776	2429	0	0
T4	770957	13661	0	0
T5	6963	94	0	0
T6	42519	1840	0	0
T7	38993	202	0	0
T8	62545	6580	0	0
T9	313578	118	0	0
T10	282662	13030	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467351143	467214626	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0