Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T14
1	0	Covered	T4,T11,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Unreachable
1	1	Covered	T4,T11,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T10,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T11
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	774749155	618367310	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	774749155	3732890	0	0
GntImpliesValid_A	774749155	3732890	0	0
GrantKnown_A	774749155	618367310	0	0
IdxKnown_A	774749155	618367310	0	0
IndexIsCorrect_A	774749155	3732890	0	0
LockArbDecision_A	774749155	0	0	0
NoReadyValidNoGrant_A	774749155	0	0	0
ReadyAndValidImplyGrant_A	774749155	3732890	0	0
ReqAndReadyImplyGrant_A	774749155	3732890	0	0
ReqImpliesValid_A	774749155	3732890	0	0
ReqStaysHighUntilGranted0_M	774749155	0	0	0
RoundRobin_A	774749155	3	0	976
ValidKnown_A	774749155	618367310	0	0
gen_data_port_assertion.DataFlow_A	774749155	3732890	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	618367310	0	0
T1	2853	2753	0	0
T2	572109	572012	0	0
T3	86887	86328	0	0
T4	1033915	894939	0	0
T5	8625	7519	0	0
T6	68887	55613	0	0
T7	108209	71605	0	0
T8	91689	77043	0	0
T9	417034	365232	0	0
T10	1074332	676634	0	0
T11	4316	1728	0	0
T12	99734	99040	0	0
T13	0	111706	0	0
T14	0	572715	0	0
T15	0	786993	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3732890	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	902436	8234	0	0
T5	7794	0	0	0
T6	55703	832	0	0
T7	73601	0	0	0
T8	77117	832	0	0
T9	365306	832	0	0
T10	1074332	9759	0	0
T11	4316	164	0	0
T12	199468	832	0	0
T13	111706	0	0	0
T14	584160	9376	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	4771	0	0
T30	2384	0	0	0
T31	124457	0	0	0
T32	0	3412	0	0
T33	0	7617	0	0
T37	0	9968	0	0
T42	0	9211	0	0
T46	0	649	0	0
T52	0	126	0	0
T53	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3732890	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	902436	8234	0	0
T5	7794	0	0	0
T6	55703	832	0	0
T7	73601	0	0	0
T8	77117	832	0	0
T9	365306	832	0	0
T10	1074332	9759	0	0
T11	4316	164	0	0
T12	199468	832	0	0
T13	111706	0	0	0
T14	584160	9376	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	4771	0	0
T30	2384	0	0	0
T31	124457	0	0	0
T32	0	3412	0	0
T33	0	7617	0	0
T37	0	9968	0	0
T42	0	9211	0	0
T46	0	649	0	0
T52	0	126	0	0
T53	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	618367310	0	0
T1	2853	2753	0	0
T2	572109	572012	0	0
T3	86887	86328	0	0
T4	1033915	894939	0	0
T5	8625	7519	0	0
T6	68887	55613	0	0
T7	108209	71605	0	0
T8	91689	77043	0	0
T9	417034	365232	0	0
T10	1074332	676634	0	0
T11	4316	1728	0	0
T12	99734	99040	0	0
T13	0	111706	0	0
T14	0	572715	0	0
T15	0	786993	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	618367310	0	0
T1	2853	2753	0	0
T2	572109	572012	0	0
T3	86887	86328	0	0
T4	1033915	894939	0	0
T5	8625	7519	0	0
T6	68887	55613	0	0
T7	108209	71605	0	0
T8	91689	77043	0	0
T9	417034	365232	0	0
T10	1074332	676634	0	0
T11	4316	1728	0	0
T12	99734	99040	0	0
T13	0	111706	0	0
T14	0	572715	0	0
T15	0	786993	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3732890	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	902436	8234	0	0
T5	7794	0	0	0
T6	55703	832	0	0
T7	73601	0	0	0
T8	77117	832	0	0
T9	365306	832	0	0
T10	1074332	9759	0	0
T11	4316	164	0	0
T12	199468	832	0	0
T13	111706	0	0	0
T14	584160	9376	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	4771	0	0
T30	2384	0	0	0
T31	124457	0	0	0
T32	0	3412	0	0
T33	0	7617	0	0
T37	0	9968	0	0
T42	0	9211	0	0
T46	0	649	0	0
T52	0	126	0	0
T53	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3732890	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	902436	8234	0	0
T5	7794	0	0	0
T6	55703	832	0	0
T7	73601	0	0	0
T8	77117	832	0	0
T9	365306	832	0	0
T10	1074332	9759	0	0
T11	4316	164	0	0
T12	199468	832	0	0
T13	111706	0	0	0
T14	584160	9376	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	4771	0	0
T30	2384	0	0	0
T31	124457	0	0	0
T32	0	3412	0	0
T33	0	7617	0	0
T37	0	9968	0	0
T42	0	9211	0	0
T46	0	649	0	0
T52	0	126	0	0
T53	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3732890	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	902436	8234	0	0
T5	7794	0	0	0
T6	55703	832	0	0
T7	73601	0	0	0
T8	77117	832	0	0
T9	365306	832	0	0
T10	1074332	9759	0	0
T11	4316	164	0	0
T12	199468	832	0	0
T13	111706	0	0	0
T14	584160	9376	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	4771	0	0
T30	2384	0	0	0
T31	124457	0	0	0
T32	0	3412	0	0
T33	0	7617	0	0
T37	0	9968	0	0
T42	0	9211	0	0
T46	0	649	0	0
T52	0	126	0	0
T53	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3732890	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	902436	8234	0	0
T5	7794	0	0	0
T6	55703	832	0	0
T7	73601	0	0	0
T8	77117	832	0	0
T9	365306	832	0	0
T10	1074332	9759	0	0
T11	4316	164	0	0
T12	199468	832	0	0
T13	111706	0	0	0
T14	584160	9376	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	4771	0	0
T30	2384	0	0	0
T31	124457	0	0	0
T32	0	3412	0	0
T33	0	7617	0	0
T37	0	9968	0	0
T42	0	9211	0	0
T46	0	649	0	0
T52	0	126	0	0
T53	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3	0	976
T38	274581	2	0	1
T54	0	1	0	0
T55	279990	0	0	1
T56	117690	0	0	1
T57	3147	0	0	1
T58	119604	0	0	1
T59	1595	0	0	1
T60	26410	0	0	1
T61	80462	0	0	1
T62	68127	0	0	1
T63	8244	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	618367310	0	0
T1	2853	2753	0	0
T2	572109	572012	0	0
T3	86887	86328	0	0
T4	1033915	894939	0	0
T5	8625	7519	0	0
T6	68887	55613	0	0
T7	108209	71605	0	0
T8	91689	77043	0	0
T9	417034	365232	0	0
T10	1074332	676634	0	0
T11	4316	1728	0	0
T12	99734	99040	0	0
T13	0	111706	0	0
T14	0	572715	0	0
T15	0	786993	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774749155	3732890	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	902436	8234	0	0
T5	7794	0	0	0
T6	55703	832	0	0
T7	73601	0	0	0
T8	77117	832	0	0
T9	365306	832	0	0
T10	1074332	9759	0	0
T11	4316	164	0	0
T12	199468	832	0	0
T13	111706	0	0	0
T14	584160	9376	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	4771	0	0
T30	2384	0	0	0
T31	124457	0	0	0
T32	0	3412	0	0
T33	0	7617	0	0
T37	0	9968	0	0
T42	0	9211	0	0
T46	0	649	0	0
T52	0	126	0	0
T53	0	14	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T14
1	0	Covered	T4,T11,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Unreachable
1	1	Covered	T4,T11,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T11,T14
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154895680	29251165	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	154895680	641690	0	0
GntImpliesValid_A	154895680	641690	0	0
GrantKnown_A	154895680	29251165	0	0
IdxKnown_A	154895680	29251165	0	0
IndexIsCorrect_A	154895680	641690	0	0
LockArbDecision_A	154895680	0	0	0
NoReadyValidNoGrant_A	154895680	0	0	0
ReadyAndValidImplyGrant_A	154895680	641690	0	0
ReqAndReadyImplyGrant_A	154895680	641690	0	0
ReqImpliesValid_A	154895680	641690	0	0
ReqStaysHighUntilGranted0_M	154895680	0	0	0
RoundRobin_A	154895680	0	0	0
ValidKnown_A	154895680	29251165	0	0
gen_data_port_assertion.DataFlow_A	154895680	641690	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	29251165	0	0
T4	131479	124072	0	0
T5	831	648	0	0
T6	13184	0	0	0
T7	34608	32704	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	1728	0	0
T12	99734	0	0	0
T14	0	161752	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	641690	0	0
T4	131479	5488	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	128	0	0
T12	99734	0	0	0
T14	0	7155	0	0
T27	0	805	0	0
T30	1192	0	0	0
T32	0	3152	0	0
T33	0	4037	0	0
T37	0	5830	0	0
T42	0	3165	0	0
T52	0	126	0	0
T53	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	641690	0	0
T4	131479	5488	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	128	0	0
T12	99734	0	0	0
T14	0	7155	0	0
T27	0	805	0	0
T30	1192	0	0	0
T32	0	3152	0	0
T33	0	4037	0	0
T37	0	5830	0	0
T42	0	3165	0	0
T52	0	126	0	0
T53	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	29251165	0	0
T4	131479	124072	0	0
T5	831	648	0	0
T6	13184	0	0	0
T7	34608	32704	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	1728	0	0
T12	99734	0	0	0
T14	0	161752	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	29251165	0	0
T4	131479	124072	0	0
T5	831	648	0	0
T6	13184	0	0	0
T7	34608	32704	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	1728	0	0
T12	99734	0	0	0
T14	0	161752	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	641690	0	0
T4	131479	5488	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	128	0	0
T12	99734	0	0	0
T14	0	7155	0	0
T27	0	805	0	0
T30	1192	0	0	0
T32	0	3152	0	0
T33	0	4037	0	0
T37	0	5830	0	0
T42	0	3165	0	0
T52	0	126	0	0
T53	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	641690	0	0
T4	131479	5488	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	128	0	0
T12	99734	0	0	0
T14	0	7155	0	0
T27	0	805	0	0
T30	1192	0	0	0
T32	0	3152	0	0
T33	0	4037	0	0
T37	0	5830	0	0
T42	0	3165	0	0
T52	0	126	0	0
T53	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	641690	0	0
T4	131479	5488	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	128	0	0
T12	99734	0	0	0
T14	0	7155	0	0
T27	0	805	0	0
T30	1192	0	0	0
T32	0	3152	0	0
T33	0	4037	0	0
T37	0	5830	0	0
T42	0	3165	0	0
T52	0	126	0	0
T53	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	641690	0	0
T4	131479	5488	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	128	0	0
T12	99734	0	0	0
T14	0	7155	0	0
T27	0	805	0	0
T30	1192	0	0	0
T32	0	3152	0	0
T33	0	4037	0	0
T37	0	5830	0	0
T42	0	3165	0	0
T52	0	126	0	0
T53	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	29251165	0	0
T4	131479	124072	0	0
T5	831	648	0	0
T6	13184	0	0	0
T7	34608	32704	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	1728	0	0
T12	99734	0	0	0
T14	0	161752	0	0
T27	0	22456	0	0
T30	1192	792	0	0
T31	0	117856	0	0
T32	0	66840	0	0
T33	0	157104	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	641690	0	0
T4	131479	5488	0	0
T5	831	0	0	0
T6	13184	0	0	0
T7	34608	0	0	0
T8	14572	0	0	0
T9	51728	0	0	0
T10	395835	0	0	0
T11	2158	128	0	0
T12	99734	0	0	0
T14	0	7155	0	0
T27	0	805	0	0
T30	1192	0	0	0
T32	0	3152	0	0
T33	0	4037	0	0
T37	0	5830	0	0
T42	0	3165	0	0
T52	0	126	0	0
T53	0	14	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T15
1	0	Covered	T10,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T10,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T14,T15
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154895680	124247852	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	154895680	787375	0	0
GntImpliesValid_A	154895680	787375	0	0
GrantKnown_A	154895680	124247852	0	0
IdxKnown_A	154895680	124247852	0	0
IndexIsCorrect_A	154895680	787375	0	0
LockArbDecision_A	154895680	0	0	0
NoReadyValidNoGrant_A	154895680	0	0	0
ReadyAndValidImplyGrant_A	154895680	787375	0	0
ReqAndReadyImplyGrant_A	154895680	787375	0	0
ReqImpliesValid_A	154895680	787375	0	0
ReqStaysHighUntilGranted0_M	154895680	0	0	0
RoundRobin_A	154895680	0	0	0
ValidKnown_A	154895680	124247852	0	0
gen_data_port_assertion.DataFlow_A	154895680	787375	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	124247852	0	0
T2	94840	94840	0	0
T3	16111	15648	0	0
T4	131479	0	0	0
T5	831	0	0	0
T6	13184	13184	0	0
T7	34608	0	0	0
T8	14572	14572	0	0
T9	51728	51728	0	0
T10	395835	393981	0	0
T11	2158	0	0	0
T12	0	99040	0	0
T13	0	111706	0	0
T14	0	410963	0	0
T15	0	786993	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	787375	0	0
T10	395835	1188	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	2221	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	3966	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	260	0	0
T33	0	3580	0	0
T37	0	4138	0	0
T42	0	6046	0	0
T46	0	649	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	787375	0	0
T10	395835	1188	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	2221	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	3966	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	260	0	0
T33	0	3580	0	0
T37	0	4138	0	0
T42	0	6046	0	0
T46	0	649	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	124247852	0	0
T2	94840	94840	0	0
T3	16111	15648	0	0
T4	131479	0	0	0
T5	831	0	0	0
T6	13184	13184	0	0
T7	34608	0	0	0
T8	14572	14572	0	0
T9	51728	51728	0	0
T10	395835	393981	0	0
T11	2158	0	0	0
T12	0	99040	0	0
T13	0	111706	0	0
T14	0	410963	0	0
T15	0	786993	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	124247852	0	0
T2	94840	94840	0	0
T3	16111	15648	0	0
T4	131479	0	0	0
T5	831	0	0	0
T6	13184	13184	0	0
T7	34608	0	0	0
T8	14572	14572	0	0
T9	51728	51728	0	0
T10	395835	393981	0	0
T11	2158	0	0	0
T12	0	99040	0	0
T13	0	111706	0	0
T14	0	410963	0	0
T15	0	786993	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	787375	0	0
T10	395835	1188	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	2221	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	3966	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	260	0	0
T33	0	3580	0	0
T37	0	4138	0	0
T42	0	6046	0	0
T46	0	649	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	787375	0	0
T10	395835	1188	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	2221	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	3966	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	260	0	0
T33	0	3580	0	0
T37	0	4138	0	0
T42	0	6046	0	0
T46	0	649	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	787375	0	0
T10	395835	1188	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	2221	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	3966	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	260	0	0
T33	0	3580	0	0
T37	0	4138	0	0
T42	0	6046	0	0
T46	0	649	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	787375	0	0
T10	395835	1188	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	2221	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	3966	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	260	0	0
T33	0	3580	0	0
T37	0	4138	0	0
T42	0	6046	0	0
T46	0	649	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	124247852	0	0
T2	94840	94840	0	0
T3	16111	15648	0	0
T4	131479	0	0	0
T5	831	0	0	0
T6	13184	13184	0	0
T7	34608	0	0	0
T8	14572	14572	0	0
T9	51728	51728	0	0
T10	395835	393981	0	0
T11	2158	0	0	0
T12	0	99040	0	0
T13	0	111706	0	0
T14	0	410963	0	0
T15	0	786993	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154895680	787375	0	0
T10	395835	1188	0	0
T11	2158	0	0	0
T12	99734	0	0	0
T13	111706	0	0	0
T14	584160	2221	0	0
T15	789119	1814	0	0
T24	100578	0	0	0
T25	499	0	0	0
T26	0	342	0	0
T27	0	3966	0	0
T30	1192	0	0	0
T31	124457	0	0	0
T32	0	260	0	0
T33	0	3580	0	0
T37	0	4138	0	0
T42	0	6046	0	0
T46	0	649	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T11
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	464957795	464868293	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	464957795	2303825	0	0
GntImpliesValid_A	464957795	2303825	0	0
GrantKnown_A	464957795	464868293	0	0
IdxKnown_A	464957795	464868293	0	0
IndexIsCorrect_A	464957795	2303825	0	0
LockArbDecision_A	464957795	0	0	0
NoReadyValidNoGrant_A	464957795	0	0	0
ReadyAndValidImplyGrant_A	464957795	2303825	0	0
ReqAndReadyImplyGrant_A	464957795	2303825	0	0
ReqImpliesValid_A	464957795	2303825	0	0
ReqStaysHighUntilGranted0_M	464957795	0	0	0
RoundRobin_A	464957795	3	0	976
ValidKnown_A	464957795	464868293	0	0
gen_data_port_assertion.DataFlow_A	464957795	2303825	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	464868293	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2303825	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	2746	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	832	0	0
T9	313578	832	0	0
T10	282662	8571	0	0
T11	0	36	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2303825	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	2746	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	832	0	0
T9	313578	832	0	0
T10	282662	8571	0	0
T11	0	36	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	464868293	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	464868293	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2303825	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	2746	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	832	0	0
T9	313578	832	0	0
T10	282662	8571	0	0
T11	0	36	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2303825	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	2746	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	832	0	0
T9	313578	832	0	0
T10	282662	8571	0	0
T11	0	36	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2303825	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	2746	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	832	0	0
T9	313578	832	0	0
T10	282662	8571	0	0
T11	0	36	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2303825	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	2746	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	832	0	0
T9	313578	832	0	0
T10	282662	8571	0	0
T11	0	36	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	3	0	976
T38	274581	2	0	1
T54	0	1	0	0
T55	279990	0	0	1
T56	117690	0	0	1
T57	3147	0	0	1
T58	119604	0	0	1
T59	1595	0	0	1
T60	26410	0	0	1
T61	80462	0	0	1
T62	68127	0	0	1
T63	8244	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	464868293	0	0
T1	2853	2753	0	0
T2	477269	477172	0	0
T3	70776	70680	0	0
T4	770957	770867	0	0
T5	6963	6871	0	0
T6	42519	42429	0	0
T7	38993	38901	0	0
T8	62545	62471	0	0
T9	313578	313504	0	0
T10	282662	282653	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464957795	2303825	0	0
T1	2853	832	0	0
T2	477269	832	0	0
T3	70776	1600	0	0
T4	770957	2746	0	0
T5	6963	0	0	0
T6	42519	832	0	0
T7	38993	0	0	0
T8	62545	832	0	0
T9	313578	832	0	0
T10	282662	8571	0	0
T11	0	36	0	0
T12	0	832	0	0