Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2855 | 
0 | 
0 | 
| T102 | 
29043 | 
8 | 
0 | 
0 | 
| T103 | 
5099 | 
62 | 
0 | 
0 | 
| T104 | 
5304 | 
177 | 
0 | 
0 | 
| T105 | 
2355 | 
54 | 
0 | 
0 | 
| T107 | 
79543 | 
4 | 
0 | 
0 | 
| T108 | 
5007 | 
108 | 
0 | 
0 | 
| T121 | 
4085 | 
6 | 
0 | 
0 | 
| T122 | 
7749 | 
5 | 
0 | 
0 | 
| T124 | 
80161 | 
2 | 
0 | 
0 | 
| T125 | 
10442 | 
3 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2050 | 
0 | 
0 | 
| T125 | 
10442 | 
15 | 
0 | 
0 | 
| T132 | 
9690 | 
4 | 
0 | 
0 | 
| T150 | 
8836 | 
5 | 
0 | 
0 | 
| T151 | 
4417 | 
1 | 
0 | 
0 | 
| T159 | 
90341 | 
230 | 
0 | 
0 | 
| T160 | 
68519 | 
89 | 
0 | 
0 | 
| T161 | 
31053 | 
17 | 
0 | 
0 | 
| T162 | 
99615 | 
113 | 
0 | 
0 | 
| T163 | 
2617 | 
1 | 
0 | 
0 | 
| T164 | 
6906 | 
26 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1869 | 
0 | 
0 | 
| T125 | 
10442 | 
7 | 
0 | 
0 | 
| T132 | 
9690 | 
2 | 
0 | 
0 | 
| T150 | 
8836 | 
1 | 
0 | 
0 | 
| T151 | 
4417 | 
4 | 
0 | 
0 | 
| T159 | 
90341 | 
194 | 
0 | 
0 | 
| T160 | 
68519 | 
64 | 
0 | 
0 | 
| T161 | 
31053 | 
24 | 
0 | 
0 | 
| T162 | 
99615 | 
132 | 
0 | 
0 | 
| T163 | 
2617 | 
7 | 
0 | 
0 | 
| T164 | 
6906 | 
1 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2237 | 
0 | 
0 | 
| T125 | 
10442 | 
27 | 
0 | 
0 | 
| T132 | 
9690 | 
12 | 
0 | 
0 | 
| T150 | 
8836 | 
30 | 
0 | 
0 | 
| T151 | 
4417 | 
4 | 
0 | 
0 | 
| T159 | 
90341 | 
221 | 
0 | 
0 | 
| T160 | 
68519 | 
134 | 
0 | 
0 | 
| T161 | 
31053 | 
16 | 
0 | 
0 | 
| T162 | 
99615 | 
195 | 
0 | 
0 | 
| T163 | 
2617 | 
8 | 
0 | 
0 | 
| T164 | 
6906 | 
25 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
6759 | 
0 | 
0 | 
| T110 | 
13111 | 
7 | 
0 | 
0 | 
| T125 | 
10442 | 
95 | 
0 | 
0 | 
| T132 | 
9690 | 
81 | 
0 | 
0 | 
| T150 | 
8836 | 
139 | 
0 | 
0 | 
| T151 | 
4417 | 
101 | 
0 | 
0 | 
| T159 | 
90341 | 
223 | 
0 | 
0 | 
| T160 | 
68519 | 
950 | 
0 | 
0 | 
| T161 | 
31053 | 
222 | 
0 | 
0 | 
| T162 | 
99615 | 
2362 | 
0 | 
0 | 
| T163 | 
2617 | 
7 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
6675 | 
0 | 
0 | 
| T125 | 
10442 | 
12 | 
0 | 
0 | 
| T132 | 
9690 | 
211 | 
0 | 
0 | 
| T150 | 
8836 | 
9 | 
0 | 
0 | 
| T151 | 
4417 | 
3 | 
0 | 
0 | 
| T159 | 
90341 | 
197 | 
0 | 
0 | 
| T160 | 
68519 | 
1324 | 
0 | 
0 | 
| T161 | 
31053 | 
264 | 
0 | 
0 | 
| T162 | 
99615 | 
2022 | 
0 | 
0 | 
| T163 | 
2617 | 
5 | 
0 | 
0 | 
| T164 | 
6906 | 
6 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
6367 | 
0 | 
0 | 
| T125 | 
10442 | 
140 | 
0 | 
0 | 
| T132 | 
9690 | 
185 | 
0 | 
0 | 
| T150 | 
8836 | 
153 | 
0 | 
0 | 
| T151 | 
4417 | 
6 | 
0 | 
0 | 
| T159 | 
90341 | 
200 | 
0 | 
0 | 
| T160 | 
68519 | 
891 | 
0 | 
0 | 
| T161 | 
31053 | 
371 | 
0 | 
0 | 
| T162 | 
99615 | 
2085 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
5 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
7493 | 
0 | 
0 | 
| T125 | 
10442 | 
102 | 
0 | 
0 | 
| T132 | 
9690 | 
32 | 
0 | 
0 | 
| T150 | 
8836 | 
278 | 
0 | 
0 | 
| T151 | 
4417 | 
123 | 
0 | 
0 | 
| T159 | 
90341 | 
207 | 
0 | 
0 | 
| T160 | 
68519 | 
1989 | 
0 | 
0 | 
| T161 | 
31053 | 
233 | 
0 | 
0 | 
| T162 | 
99615 | 
2095 | 
0 | 
0 | 
| T163 | 
2617 | 
3 | 
0 | 
0 | 
| T164 | 
6906 | 
13 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
6626 | 
0 | 
0 | 
| T125 | 
10442 | 
217 | 
0 | 
0 | 
| T132 | 
9690 | 
98 | 
0 | 
0 | 
| T150 | 
8836 | 
125 | 
0 | 
0 | 
| T151 | 
4417 | 
135 | 
0 | 
0 | 
| T159 | 
90341 | 
214 | 
0 | 
0 | 
| T160 | 
68519 | 
1286 | 
0 | 
0 | 
| T161 | 
31053 | 
389 | 
0 | 
0 | 
| T162 | 
99615 | 
1591 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
11 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
7299 | 
0 | 
0 | 
| T125 | 
10442 | 
255 | 
0 | 
0 | 
| T132 | 
9690 | 
103 | 
0 | 
0 | 
| T135 | 
180340 | 
411 | 
0 | 
0 | 
| T150 | 
8836 | 
257 | 
0 | 
0 | 
| T151 | 
4417 | 
136 | 
0 | 
0 | 
| T159 | 
90341 | 
229 | 
0 | 
0 | 
| T160 | 
68519 | 
1627 | 
0 | 
0 | 
| T161 | 
31053 | 
333 | 
0 | 
0 | 
| T162 | 
99615 | 
1743 | 
0 | 
0 | 
| T163 | 
2617 | 
10 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
6222 | 
0 | 
0 | 
| T125 | 
10442 | 
121 | 
0 | 
0 | 
| T132 | 
9690 | 
43 | 
0 | 
0 | 
| T135 | 
180340 | 
453 | 
0 | 
0 | 
| T150 | 
8836 | 
99 | 
0 | 
0 | 
| T151 | 
4417 | 
1 | 
0 | 
0 | 
| T159 | 
90341 | 
231 | 
0 | 
0 | 
| T160 | 
68519 | 
1397 | 
0 | 
0 | 
| T161 | 
31053 | 
240 | 
0 | 
0 | 
| T162 | 
99615 | 
1457 | 
0 | 
0 | 
| T165 | 
18570 | 
52 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
6633 | 
0 | 
0 | 
| T125 | 
10442 | 
135 | 
0 | 
0 | 
| T132 | 
9690 | 
20 | 
0 | 
0 | 
| T150 | 
8836 | 
8 | 
0 | 
0 | 
| T151 | 
4417 | 
6 | 
0 | 
0 | 
| T159 | 
90341 | 
217 | 
0 | 
0 | 
| T160 | 
68519 | 
1250 | 
0 | 
0 | 
| T161 | 
31053 | 
169 | 
0 | 
0 | 
| T162 | 
99615 | 
1969 | 
0 | 
0 | 
| T163 | 
2617 | 
5 | 
0 | 
0 | 
| T164 | 
6906 | 
47 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3590 | 
0 | 
0 | 
| T125 | 
10442 | 
76 | 
0 | 
0 | 
| T132 | 
9690 | 
9 | 
0 | 
0 | 
| T150 | 
8836 | 
46 | 
0 | 
0 | 
| T151 | 
4417 | 
50 | 
0 | 
0 | 
| T159 | 
90341 | 
209 | 
0 | 
0 | 
| T160 | 
68519 | 
570 | 
0 | 
0 | 
| T161 | 
31053 | 
103 | 
0 | 
0 | 
| T162 | 
99615 | 
810 | 
0 | 
0 | 
| T163 | 
2617 | 
4 | 
0 | 
0 | 
| T164 | 
6906 | 
10 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3881 | 
0 | 
0 | 
| T125 | 
10442 | 
53 | 
0 | 
0 | 
| T132 | 
9690 | 
19 | 
0 | 
0 | 
| T150 | 
8836 | 
69 | 
0 | 
0 | 
| T151 | 
4417 | 
64 | 
0 | 
0 | 
| T159 | 
90341 | 
258 | 
0 | 
0 | 
| T160 | 
68519 | 
564 | 
0 | 
0 | 
| T161 | 
31053 | 
97 | 
0 | 
0 | 
| T162 | 
99615 | 
962 | 
0 | 
0 | 
| T163 | 
2617 | 
8 | 
0 | 
0 | 
| T164 | 
6906 | 
30 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3825 | 
0 | 
0 | 
| T125 | 
10442 | 
75 | 
0 | 
0 | 
| T132 | 
9690 | 
64 | 
0 | 
0 | 
| T135 | 
180340 | 
471 | 
0 | 
0 | 
| T150 | 
8836 | 
104 | 
0 | 
0 | 
| T151 | 
4417 | 
55 | 
0 | 
0 | 
| T159 | 
90341 | 
207 | 
0 | 
0 | 
| T160 | 
68519 | 
532 | 
0 | 
0 | 
| T161 | 
31053 | 
178 | 
0 | 
0 | 
| T162 | 
99615 | 
728 | 
0 | 
0 | 
| T163 | 
2617 | 
7 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3751 | 
0 | 
0 | 
| T125 | 
10442 | 
114 | 
0 | 
0 | 
| T132 | 
9690 | 
46 | 
0 | 
0 | 
| T150 | 
8836 | 
54 | 
0 | 
0 | 
| T151 | 
4417 | 
54 | 
0 | 
0 | 
| T159 | 
90341 | 
239 | 
0 | 
0 | 
| T160 | 
68519 | 
623 | 
0 | 
0 | 
| T161 | 
31053 | 
145 | 
0 | 
0 | 
| T162 | 
99615 | 
529 | 
0 | 
0 | 
| T163 | 
2617 | 
3 | 
0 | 
0 | 
| T164 | 
6906 | 
14 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3893 | 
0 | 
0 | 
| T125 | 
10442 | 
53 | 
0 | 
0 | 
| T132 | 
9690 | 
66 | 
0 | 
0 | 
| T150 | 
8836 | 
138 | 
0 | 
0 | 
| T151 | 
4417 | 
8 | 
0 | 
0 | 
| T159 | 
90341 | 
180 | 
0 | 
0 | 
| T160 | 
68519 | 
572 | 
0 | 
0 | 
| T161 | 
31053 | 
191 | 
0 | 
0 | 
| T162 | 
99615 | 
794 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
14 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3861 | 
0 | 
0 | 
| T125 | 
10442 | 
20 | 
0 | 
0 | 
| T132 | 
9690 | 
81 | 
0 | 
0 | 
| T150 | 
8836 | 
77 | 
0 | 
0 | 
| T151 | 
4417 | 
65 | 
0 | 
0 | 
| T159 | 
90341 | 
224 | 
0 | 
0 | 
| T160 | 
68519 | 
574 | 
0 | 
0 | 
| T161 | 
31053 | 
153 | 
0 | 
0 | 
| T162 | 
99615 | 
743 | 
0 | 
0 | 
| T163 | 
2617 | 
2 | 
0 | 
0 | 
| T164 | 
6906 | 
30 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3767 | 
0 | 
0 | 
| T125 | 
10442 | 
52 | 
0 | 
0 | 
| T132 | 
9690 | 
59 | 
0 | 
0 | 
| T150 | 
8836 | 
89 | 
0 | 
0 | 
| T151 | 
4417 | 
6 | 
0 | 
0 | 
| T159 | 
90341 | 
222 | 
0 | 
0 | 
| T160 | 
68519 | 
805 | 
0 | 
0 | 
| T161 | 
31053 | 
131 | 
0 | 
0 | 
| T162 | 
99615 | 
680 | 
0 | 
0 | 
| T163 | 
2617 | 
5 | 
0 | 
0 | 
| T164 | 
6906 | 
24 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3620 | 
0 | 
0 | 
| T110 | 
13111 | 
3 | 
0 | 
0 | 
| T125 | 
10442 | 
63 | 
0 | 
0 | 
| T132 | 
9690 | 
42 | 
0 | 
0 | 
| T150 | 
8836 | 
117 | 
0 | 
0 | 
| T151 | 
4417 | 
46 | 
0 | 
0 | 
| T159 | 
90341 | 
206 | 
0 | 
0 | 
| T160 | 
68519 | 
520 | 
0 | 
0 | 
| T161 | 
31053 | 
184 | 
0 | 
0 | 
| T162 | 
99615 | 
810 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3754 | 
0 | 
0 | 
| T125 | 
10442 | 
15 | 
0 | 
0 | 
| T132 | 
9690 | 
40 | 
0 | 
0 | 
| T150 | 
8836 | 
105 | 
0 | 
0 | 
| T151 | 
4417 | 
35 | 
0 | 
0 | 
| T159 | 
90341 | 
244 | 
0 | 
0 | 
| T160 | 
68519 | 
511 | 
0 | 
0 | 
| T161 | 
31053 | 
207 | 
0 | 
0 | 
| T162 | 
99615 | 
702 | 
0 | 
0 | 
| T163 | 
2617 | 
2 | 
0 | 
0 | 
| T164 | 
6906 | 
24 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
4010 | 
0 | 
0 | 
| T125 | 
10442 | 
76 | 
0 | 
0 | 
| T132 | 
9690 | 
61 | 
0 | 
0 | 
| T150 | 
8836 | 
40 | 
0 | 
0 | 
| T151 | 
4417 | 
47 | 
0 | 
0 | 
| T159 | 
90341 | 
281 | 
0 | 
0 | 
| T160 | 
68519 | 
522 | 
0 | 
0 | 
| T161 | 
31053 | 
144 | 
0 | 
0 | 
| T162 | 
99615 | 
784 | 
0 | 
0 | 
| T163 | 
2617 | 
8 | 
0 | 
0 | 
| T164 | 
6906 | 
3 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
4072 | 
0 | 
0 | 
| T110 | 
13111 | 
5 | 
0 | 
0 | 
| T125 | 
10442 | 
7 | 
0 | 
0 | 
| T132 | 
9690 | 
65 | 
0 | 
0 | 
| T150 | 
8836 | 
88 | 
0 | 
0 | 
| T151 | 
4417 | 
64 | 
0 | 
0 | 
| T159 | 
90341 | 
214 | 
0 | 
0 | 
| T160 | 
68519 | 
408 | 
0 | 
0 | 
| T161 | 
31053 | 
104 | 
0 | 
0 | 
| T162 | 
99615 | 
1046 | 
0 | 
0 | 
| T163 | 
2617 | 
4 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3913 | 
0 | 
0 | 
| T125 | 
10442 | 
73 | 
0 | 
0 | 
| T132 | 
9690 | 
65 | 
0 | 
0 | 
| T150 | 
8836 | 
57 | 
0 | 
0 | 
| T151 | 
4417 | 
51 | 
0 | 
0 | 
| T159 | 
90341 | 
252 | 
0 | 
0 | 
| T160 | 
68519 | 
617 | 
0 | 
0 | 
| T161 | 
31053 | 
175 | 
0 | 
0 | 
| T162 | 
99615 | 
760 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
9 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3942 | 
0 | 
0 | 
| T125 | 
10442 | 
39 | 
0 | 
0 | 
| T132 | 
9690 | 
49 | 
0 | 
0 | 
| T150 | 
8836 | 
79 | 
0 | 
0 | 
| T151 | 
4417 | 
2 | 
0 | 
0 | 
| T159 | 
90341 | 
223 | 
0 | 
0 | 
| T160 | 
68519 | 
575 | 
0 | 
0 | 
| T161 | 
31053 | 
162 | 
0 | 
0 | 
| T162 | 
99615 | 
1015 | 
0 | 
0 | 
| T163 | 
2617 | 
7 | 
0 | 
0 | 
| T164 | 
6906 | 
11 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
4263 | 
0 | 
0 | 
| T125 | 
10442 | 
108 | 
0 | 
0 | 
| T132 | 
9690 | 
57 | 
0 | 
0 | 
| T150 | 
8836 | 
81 | 
0 | 
0 | 
| T151 | 
4417 | 
29 | 
0 | 
0 | 
| T159 | 
90341 | 
258 | 
0 | 
0 | 
| T160 | 
68519 | 
717 | 
0 | 
0 | 
| T161 | 
31053 | 
150 | 
0 | 
0 | 
| T162 | 
99615 | 
807 | 
0 | 
0 | 
| T163 | 
2617 | 
2 | 
0 | 
0 | 
| T164 | 
6906 | 
8 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3986 | 
0 | 
0 | 
| T125 | 
10442 | 
51 | 
0 | 
0 | 
| T132 | 
9690 | 
82 | 
0 | 
0 | 
| T150 | 
8836 | 
8 | 
0 | 
0 | 
| T151 | 
4417 | 
49 | 
0 | 
0 | 
| T159 | 
90341 | 
232 | 
0 | 
0 | 
| T160 | 
68519 | 
514 | 
0 | 
0 | 
| T161 | 
31053 | 
191 | 
0 | 
0 | 
| T162 | 
99615 | 
908 | 
0 | 
0 | 
| T163 | 
2617 | 
5 | 
0 | 
0 | 
| T164 | 
6906 | 
3 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3498 | 
0 | 
0 | 
| T125 | 
10442 | 
25 | 
0 | 
0 | 
| T132 | 
9690 | 
17 | 
0 | 
0 | 
| T135 | 
180340 | 
425 | 
0 | 
0 | 
| T150 | 
8836 | 
64 | 
0 | 
0 | 
| T151 | 
4417 | 
61 | 
0 | 
0 | 
| T159 | 
90341 | 
187 | 
0 | 
0 | 
| T160 | 
68519 | 
683 | 
0 | 
0 | 
| T161 | 
31053 | 
107 | 
0 | 
0 | 
| T162 | 
99615 | 
710 | 
0 | 
0 | 
| T163 | 
2617 | 
8 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3965 | 
0 | 
0 | 
| T125 | 
10442 | 
8 | 
0 | 
0 | 
| T132 | 
9690 | 
47 | 
0 | 
0 | 
| T135 | 
180340 | 
429 | 
0 | 
0 | 
| T150 | 
8836 | 
118 | 
0 | 
0 | 
| T151 | 
4417 | 
61 | 
0 | 
0 | 
| T159 | 
90341 | 
203 | 
0 | 
0 | 
| T160 | 
68519 | 
541 | 
0 | 
0 | 
| T161 | 
31053 | 
145 | 
0 | 
0 | 
| T162 | 
99615 | 
810 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3888 | 
0 | 
0 | 
| T125 | 
10442 | 
40 | 
0 | 
0 | 
| T132 | 
9690 | 
43 | 
0 | 
0 | 
| T150 | 
8836 | 
107 | 
0 | 
0 | 
| T151 | 
4417 | 
1 | 
0 | 
0 | 
| T159 | 
90341 | 
297 | 
0 | 
0 | 
| T160 | 
68519 | 
509 | 
0 | 
0 | 
| T161 | 
31053 | 
193 | 
0 | 
0 | 
| T162 | 
99615 | 
913 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
5 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3648 | 
0 | 
0 | 
| T125 | 
10442 | 
100 | 
0 | 
0 | 
| T132 | 
9690 | 
39 | 
0 | 
0 | 
| T150 | 
8836 | 
85 | 
0 | 
0 | 
| T151 | 
4417 | 
9 | 
0 | 
0 | 
| T159 | 
90341 | 
177 | 
0 | 
0 | 
| T160 | 
68519 | 
471 | 
0 | 
0 | 
| T161 | 
31053 | 
129 | 
0 | 
0 | 
| T162 | 
99615 | 
738 | 
0 | 
0 | 
| T163 | 
2617 | 
4 | 
0 | 
0 | 
| T164 | 
6906 | 
3 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3781 | 
0 | 
0 | 
| T125 | 
10442 | 
50 | 
0 | 
0 | 
| T132 | 
9690 | 
10 | 
0 | 
0 | 
| T135 | 
180340 | 
430 | 
0 | 
0 | 
| T150 | 
8836 | 
48 | 
0 | 
0 | 
| T151 | 
4417 | 
59 | 
0 | 
0 | 
| T159 | 
90341 | 
197 | 
0 | 
0 | 
| T160 | 
68519 | 
704 | 
0 | 
0 | 
| T161 | 
31053 | 
157 | 
0 | 
0 | 
| T162 | 
99615 | 
726 | 
0 | 
0 | 
| T164 | 
6906 | 
1 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3601 | 
0 | 
0 | 
| T125 | 
10442 | 
69 | 
0 | 
0 | 
| T132 | 
9690 | 
38 | 
0 | 
0 | 
| T135 | 
180340 | 
432 | 
0 | 
0 | 
| T150 | 
8836 | 
108 | 
0 | 
0 | 
| T151 | 
4417 | 
27 | 
0 | 
0 | 
| T159 | 
90341 | 
252 | 
0 | 
0 | 
| T160 | 
68519 | 
375 | 
0 | 
0 | 
| T161 | 
31053 | 
64 | 
0 | 
0 | 
| T162 | 
99615 | 
884 | 
0 | 
0 | 
| T163 | 
2617 | 
2 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3556 | 
0 | 
0 | 
| T110 | 
13111 | 
2 | 
0 | 
0 | 
| T125 | 
10442 | 
58 | 
0 | 
0 | 
| T132 | 
9690 | 
52 | 
0 | 
0 | 
| T150 | 
8836 | 
47 | 
0 | 
0 | 
| T151 | 
4417 | 
54 | 
0 | 
0 | 
| T159 | 
90341 | 
235 | 
0 | 
0 | 
| T160 | 
68519 | 
420 | 
0 | 
0 | 
| T161 | 
31053 | 
152 | 
0 | 
0 | 
| T162 | 
99615 | 
519 | 
0 | 
0 | 
| T163 | 
2617 | 
3 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3797 | 
0 | 
0 | 
| T125 | 
10442 | 
73 | 
0 | 
0 | 
| T132 | 
9690 | 
62 | 
0 | 
0 | 
| T150 | 
8836 | 
34 | 
0 | 
0 | 
| T151 | 
4417 | 
6 | 
0 | 
0 | 
| T159 | 
90341 | 
217 | 
0 | 
0 | 
| T160 | 
68519 | 
449 | 
0 | 
0 | 
| T161 | 
31053 | 
118 | 
0 | 
0 | 
| T162 | 
99615 | 
896 | 
0 | 
0 | 
| T163 | 
2617 | 
2 | 
0 | 
0 | 
| T164 | 
6906 | 
1 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
4219 | 
0 | 
0 | 
| T125 | 
10442 | 
8 | 
0 | 
0 | 
| T132 | 
9690 | 
53 | 
0 | 
0 | 
| T135 | 
180340 | 
450 | 
0 | 
0 | 
| T150 | 
8836 | 
59 | 
0 | 
0 | 
| T159 | 
90341 | 
233 | 
0 | 
0 | 
| T160 | 
68519 | 
718 | 
0 | 
0 | 
| T161 | 
31053 | 
224 | 
0 | 
0 | 
| T162 | 
99615 | 
994 | 
0 | 
0 | 
| T163 | 
2617 | 
7 | 
0 | 
0 | 
| T164 | 
6906 | 
18 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2120 | 
0 | 
0 | 
| T125 | 
10442 | 
11 | 
0 | 
0 | 
| T132 | 
9690 | 
17 | 
0 | 
0 | 
| T150 | 
8836 | 
24 | 
0 | 
0 | 
| T151 | 
4417 | 
2 | 
0 | 
0 | 
| T159 | 
90341 | 
247 | 
0 | 
0 | 
| T160 | 
68519 | 
111 | 
0 | 
0 | 
| T161 | 
31053 | 
34 | 
0 | 
0 | 
| T162 | 
99615 | 
184 | 
0 | 
0 | 
| T163 | 
2617 | 
7 | 
0 | 
0 | 
| T164 | 
6906 | 
17 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2101 | 
0 | 
0 | 
| T125 | 
10442 | 
15 | 
0 | 
0 | 
| T132 | 
9690 | 
7 | 
0 | 
0 | 
| T150 | 
8836 | 
12 | 
0 | 
0 | 
| T151 | 
4417 | 
9 | 
0 | 
0 | 
| T159 | 
90341 | 
215 | 
0 | 
0 | 
| T160 | 
68519 | 
133 | 
0 | 
0 | 
| T161 | 
31053 | 
33 | 
0 | 
0 | 
| T162 | 
99615 | 
140 | 
0 | 
0 | 
| T163 | 
2617 | 
4 | 
0 | 
0 | 
| T164 | 
6906 | 
15 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2108 | 
0 | 
0 | 
| T125 | 
10442 | 
14 | 
0 | 
0 | 
| T132 | 
9690 | 
15 | 
0 | 
0 | 
| T150 | 
8836 | 
13 | 
0 | 
0 | 
| T151 | 
4417 | 
5 | 
0 | 
0 | 
| T159 | 
90341 | 
210 | 
0 | 
0 | 
| T160 | 
68519 | 
122 | 
0 | 
0 | 
| T161 | 
31053 | 
47 | 
0 | 
0 | 
| T162 | 
99615 | 
208 | 
0 | 
0 | 
| T163 | 
2617 | 
5 | 
0 | 
0 | 
| T164 | 
6906 | 
9 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1937 | 
0 | 
0 | 
| T125 | 
10442 | 
14 | 
0 | 
0 | 
| T132 | 
9690 | 
7 | 
0 | 
0 | 
| T150 | 
8836 | 
8 | 
0 | 
0 | 
| T151 | 
4417 | 
8 | 
0 | 
0 | 
| T159 | 
90341 | 
202 | 
0 | 
0 | 
| T160 | 
68519 | 
109 | 
0 | 
0 | 
| T161 | 
31053 | 
20 | 
0 | 
0 | 
| T162 | 
99615 | 
169 | 
0 | 
0 | 
| T163 | 
2617 | 
2 | 
0 | 
0 | 
| T164 | 
6906 | 
9 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2551 | 
0 | 
0 | 
| T125 | 
10442 | 
42 | 
0 | 
0 | 
| T132 | 
9690 | 
1 | 
0 | 
0 | 
| T135 | 
180340 | 
456 | 
0 | 
0 | 
| T150 | 
8836 | 
28 | 
0 | 
0 | 
| T159 | 
90341 | 
259 | 
0 | 
0 | 
| T160 | 
68519 | 
221 | 
0 | 
0 | 
| T161 | 
31053 | 
46 | 
0 | 
0 | 
| T162 | 
99615 | 
312 | 
0 | 
0 | 
| T163 | 
2617 | 
8 | 
0 | 
0 | 
| T164 | 
6906 | 
4 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
3819 | 
0 | 
0 | 
| T16 | 
263062 | 
33 | 
0 | 
0 | 
| T20 | 
0 | 
40 | 
0 | 
0 | 
| T35 | 
0 | 
23 | 
0 | 
0 | 
| T69 | 
1199 | 
0 | 
0 | 
0 | 
| T166 | 
0 | 
43 | 
0 | 
0 | 
| T167 | 
0 | 
27 | 
0 | 
0 | 
| T168 | 
0 | 
29 | 
0 | 
0 | 
| T169 | 
0 | 
19 | 
0 | 
0 | 
| T170 | 
0 | 
18 | 
0 | 
0 | 
| T171 | 
0 | 
71 | 
0 | 
0 | 
| T172 | 
0 | 
26 | 
0 | 
0 | 
| T173 | 
72765 | 
0 | 
0 | 
0 | 
| T174 | 
18344 | 
0 | 
0 | 
0 | 
| T175 | 
969 | 
0 | 
0 | 
0 | 
| T176 | 
88387 | 
0 | 
0 | 
0 | 
| T177 | 
247985 | 
0 | 
0 | 
0 | 
| T178 | 
677859 | 
0 | 
0 | 
0 | 
| T179 | 
52317 | 
0 | 
0 | 
0 | 
| T180 | 
1240 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2112 | 
0 | 
0 | 
| T125 | 
10442 | 
25 | 
0 | 
0 | 
| T132 | 
9690 | 
11 | 
0 | 
0 | 
| T150 | 
8836 | 
23 | 
0 | 
0 | 
| T151 | 
4417 | 
6 | 
0 | 
0 | 
| T159 | 
90341 | 
271 | 
0 | 
0 | 
| T160 | 
68519 | 
91 | 
0 | 
0 | 
| T161 | 
31053 | 
35 | 
0 | 
0 | 
| T162 | 
99615 | 
176 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
25 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2074 | 
0 | 
0 | 
| T125 | 
10442 | 
15 | 
0 | 
0 | 
| T132 | 
9690 | 
5 | 
0 | 
0 | 
| T135 | 
180340 | 
477 | 
0 | 
0 | 
| T150 | 
8836 | 
14 | 
0 | 
0 | 
| T159 | 
90341 | 
226 | 
0 | 
0 | 
| T160 | 
68519 | 
117 | 
0 | 
0 | 
| T161 | 
31053 | 
27 | 
0 | 
0 | 
| T162 | 
99615 | 
181 | 
0 | 
0 | 
| T163 | 
2617 | 
3 | 
0 | 
0 | 
| T164 | 
6906 | 
7 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2012 | 
0 | 
0 | 
| T125 | 
10442 | 
13 | 
0 | 
0 | 
| T132 | 
9690 | 
4 | 
0 | 
0 | 
| T150 | 
8836 | 
1 | 
0 | 
0 | 
| T151 | 
4417 | 
3 | 
0 | 
0 | 
| T159 | 
90341 | 
248 | 
0 | 
0 | 
| T160 | 
68519 | 
79 | 
0 | 
0 | 
| T161 | 
31053 | 
27 | 
0 | 
0 | 
| T162 | 
99615 | 
124 | 
0 | 
0 | 
| T163 | 
2617 | 
4 | 
0 | 
0 | 
| T164 | 
6906 | 
6 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1843 | 
0 | 
0 | 
| T125 | 
10442 | 
13 | 
0 | 
0 | 
| T132 | 
9690 | 
9 | 
0 | 
0 | 
| T150 | 
8836 | 
15 | 
0 | 
0 | 
| T151 | 
4417 | 
7 | 
0 | 
0 | 
| T159 | 
90341 | 
229 | 
0 | 
0 | 
| T160 | 
68519 | 
83 | 
0 | 
0 | 
| T161 | 
31053 | 
14 | 
0 | 
0 | 
| T162 | 
99615 | 
104 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
22 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1906 | 
0 | 
0 | 
| T125 | 
10442 | 
20 | 
0 | 
0 | 
| T132 | 
9690 | 
3 | 
0 | 
0 | 
| T150 | 
8836 | 
8 | 
0 | 
0 | 
| T151 | 
4417 | 
5 | 
0 | 
0 | 
| T159 | 
90341 | 
248 | 
0 | 
0 | 
| T160 | 
68519 | 
69 | 
0 | 
0 | 
| T161 | 
31053 | 
26 | 
0 | 
0 | 
| T162 | 
99615 | 
87 | 
0 | 
0 | 
| T163 | 
2617 | 
9 | 
0 | 
0 | 
| T164 | 
6906 | 
5 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1931 | 
0 | 
0 | 
| T125 | 
10442 | 
13 | 
0 | 
0 | 
| T132 | 
9690 | 
15 | 
0 | 
0 | 
| T150 | 
8836 | 
5 | 
0 | 
0 | 
| T151 | 
4417 | 
1 | 
0 | 
0 | 
| T159 | 
90341 | 
237 | 
0 | 
0 | 
| T160 | 
68519 | 
94 | 
0 | 
0 | 
| T161 | 
31053 | 
25 | 
0 | 
0 | 
| T162 | 
99615 | 
126 | 
0 | 
0 | 
| T163 | 
2617 | 
4 | 
0 | 
0 | 
| T164 | 
6906 | 
5 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2191 | 
0 | 
0 | 
| T125 | 
10442 | 
30 | 
0 | 
0 | 
| T132 | 
9690 | 
20 | 
0 | 
0 | 
| T150 | 
8836 | 
21 | 
0 | 
0 | 
| T151 | 
4417 | 
18 | 
0 | 
0 | 
| T159 | 
90341 | 
209 | 
0 | 
0 | 
| T160 | 
68519 | 
172 | 
0 | 
0 | 
| T161 | 
31053 | 
44 | 
0 | 
0 | 
| T162 | 
99615 | 
252 | 
0 | 
0 | 
| T163 | 
2617 | 
7 | 
0 | 
0 | 
| T164 | 
6906 | 
25 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1846 | 
0 | 
0 | 
| T125 | 
10442 | 
16 | 
0 | 
0 | 
| T132 | 
9690 | 
1 | 
0 | 
0 | 
| T150 | 
8836 | 
9 | 
0 | 
0 | 
| T151 | 
4417 | 
4 | 
0 | 
0 | 
| T159 | 
90341 | 
213 | 
0 | 
0 | 
| T160 | 
68519 | 
77 | 
0 | 
0 | 
| T161 | 
31053 | 
33 | 
0 | 
0 | 
| T162 | 
99615 | 
117 | 
0 | 
0 | 
| T163 | 
2617 | 
3 | 
0 | 
0 | 
| T164 | 
6906 | 
18 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2642 | 
0 | 
0 | 
| T125 | 
10442 | 
18 | 
0 | 
0 | 
| T132 | 
9690 | 
20 | 
0 | 
0 | 
| T150 | 
8836 | 
21 | 
0 | 
0 | 
| T151 | 
4417 | 
19 | 
0 | 
0 | 
| T159 | 
90341 | 
268 | 
0 | 
0 | 
| T160 | 
68519 | 
253 | 
0 | 
0 | 
| T161 | 
31053 | 
50 | 
0 | 
0 | 
| T162 | 
99615 | 
402 | 
0 | 
0 | 
| T163 | 
2617 | 
9 | 
0 | 
0 | 
| T164 | 
6906 | 
7 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2051 | 
0 | 
0 | 
| T125 | 
10442 | 
10 | 
0 | 
0 | 
| T132 | 
9690 | 
4 | 
0 | 
0 | 
| T135 | 
180340 | 
413 | 
0 | 
0 | 
| T150 | 
8836 | 
18 | 
0 | 
0 | 
| T151 | 
4417 | 
10 | 
0 | 
0 | 
| T159 | 
90341 | 
196 | 
0 | 
0 | 
| T160 | 
68519 | 
94 | 
0 | 
0 | 
| T161 | 
31053 | 
18 | 
0 | 
0 | 
| T162 | 
99615 | 
164 | 
0 | 
0 | 
| T164 | 
6906 | 
2 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1960 | 
0 | 
0 | 
| T125 | 
10442 | 
21 | 
0 | 
0 | 
| T132 | 
9690 | 
6 | 
0 | 
0 | 
| T150 | 
8836 | 
7 | 
0 | 
0 | 
| T151 | 
4417 | 
4 | 
0 | 
0 | 
| T159 | 
90341 | 
210 | 
0 | 
0 | 
| T160 | 
68519 | 
86 | 
0 | 
0 | 
| T161 | 
31053 | 
24 | 
0 | 
0 | 
| T162 | 
99615 | 
108 | 
0 | 
0 | 
| T163 | 
2617 | 
6 | 
0 | 
0 | 
| T164 | 
6906 | 
7 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
2023 | 
0 | 
0 | 
| T125 | 
10442 | 
17 | 
0 | 
0 | 
| T132 | 
9690 | 
13 | 
0 | 
0 | 
| T135 | 
180340 | 
436 | 
0 | 
0 | 
| T150 | 
8836 | 
2 | 
0 | 
0 | 
| T159 | 
90341 | 
223 | 
0 | 
0 | 
| T160 | 
68519 | 
83 | 
0 | 
0 | 
| T161 | 
31053 | 
30 | 
0 | 
0 | 
| T162 | 
99615 | 
83 | 
0 | 
0 | 
| T163 | 
2617 | 
5 | 
0 | 
0 | 
| T164 | 
6906 | 
12 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1960 | 
0 | 
0 | 
| T110 | 
13111 | 
1 | 
0 | 
0 | 
| T125 | 
10442 | 
8 | 
0 | 
0 | 
| T132 | 
9690 | 
7 | 
0 | 
0 | 
| T150 | 
8836 | 
5 | 
0 | 
0 | 
| T151 | 
4417 | 
5 | 
0 | 
0 | 
| T159 | 
90341 | 
198 | 
0 | 
0 | 
| T160 | 
68519 | 
61 | 
0 | 
0 | 
| T161 | 
31053 | 
11 | 
0 | 
0 | 
| T162 | 
99615 | 
120 | 
0 | 
0 | 
| T163 | 
2617 | 
1 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1886 | 
0 | 
0 | 
| T125 | 
10442 | 
25 | 
0 | 
0 | 
| T132 | 
9690 | 
2 | 
0 | 
0 | 
| T150 | 
8836 | 
8 | 
0 | 
0 | 
| T151 | 
4417 | 
1 | 
0 | 
0 | 
| T159 | 
90341 | 
248 | 
0 | 
0 | 
| T160 | 
68519 | 
62 | 
0 | 
0 | 
| T161 | 
31053 | 
25 | 
0 | 
0 | 
| T162 | 
99615 | 
107 | 
0 | 
0 | 
| T163 | 
2617 | 
3 | 
0 | 
0 | 
| T164 | 
6906 | 
27 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1962 | 
0 | 
0 | 
| T125 | 
10442 | 
10 | 
0 | 
0 | 
| T132 | 
9690 | 
10 | 
0 | 
0 | 
| T135 | 
180340 | 
502 | 
0 | 
0 | 
| T150 | 
8836 | 
9 | 
0 | 
0 | 
| T151 | 
4417 | 
6 | 
0 | 
0 | 
| T159 | 
90341 | 
193 | 
0 | 
0 | 
| T160 | 
68519 | 
78 | 
0 | 
0 | 
| T161 | 
31053 | 
15 | 
0 | 
0 | 
| T162 | 
99615 | 
128 | 
0 | 
0 | 
| T163 | 
2617 | 
9 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
467351143 | 
1983 | 
0 | 
0 | 
| T125 | 
10442 | 
20 | 
0 | 
0 | 
| T135 | 
180340 | 
479 | 
0 | 
0 | 
| T150 | 
8836 | 
11 | 
0 | 
0 | 
| T151 | 
4417 | 
7 | 
0 | 
0 | 
| T159 | 
90341 | 
189 | 
0 | 
0 | 
| T160 | 
68519 | 
75 | 
0 | 
0 | 
| T161 | 
31053 | 
28 | 
0 | 
0 | 
| T162 | 
99615 | 
105 | 
0 | 
0 | 
| T163 | 
2617 | 
4 | 
0 | 
0 | 
| T164 | 
6906 | 
6 | 
0 | 
0 |