Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3579202	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4129402

1

T1

2117

T2

1

T3

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4298355	1			T1	2414		T2	1		T3	1
values[0x0]	1705775	1			T1	439		T2	2		T3	38
values[0x1]	1704474	1			T1	447		T2	4		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2541707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5166897

1

T1

2365

T2

2

T3

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29977	1			T1	13		T4	5		T6	7
valid_sources[0x01]	28176	1			T1	4		T4	5		T8	50
valid_sources[0x02]	28288	1			T1	22		T4	2		T6	10
valid_sources[0x03]	27178	1			T1	19		T4	3		T8	45
valid_sources[0x04]	27027	1			T1	11		T4	3		T6	10
valid_sources[0x05]	27988	1			T1	15		T3	1		T4	6
valid_sources[0x06]	34945	1			T1	8		T4	4		T6	10
valid_sources[0x07]	31252	1			T1	12		T4	2		T8	32
valid_sources[0x08]	26564	1			T1	14		T3	1		T4	2
valid_sources[0x09]	28396	1			T1	19		T4	3		T6	3
valid_sources[0x0a]	39531	1			T1	7		T4	2		T8	37
valid_sources[0x0b]	41449	1			T1	11		T4	3		T6	4
valid_sources[0x0c]	29206	1			T1	18		T4	1		T5	7
valid_sources[0x0d]	28802	1			T1	17		T4	5		T6	3
valid_sources[0x0e]	31528	1			T1	22		T4	4		T5	416
valid_sources[0x0f]	28831	1			T1	5		T4	4		T7	2
valid_sources[0x10]	38622	1			T1	15		T4	1		T5	416
valid_sources[0x11]	38203	1			T1	12		T4	1		T8	41
valid_sources[0x12]	37375	1			T1	15		T4	5		T5	2
valid_sources[0x13]	28026	1			T1	13		T4	3		T5	471
valid_sources[0x14]	27529	1			T1	8		T4	3		T6	7
valid_sources[0x15]	27751	1			T1	18		T4	1		T8	48
valid_sources[0x16]	31014	1			T1	13		T4	4		T5	87
valid_sources[0x17]	27689	1			T1	2		T4	3		T5	1
valid_sources[0x18]	30504	1			T1	25		T4	1		T8	31
valid_sources[0x19]	28557	1			T1	3		T4	1		T6	13
valid_sources[0x1a]	118656	1			T1	21		T3	1		T4	2
valid_sources[0x1b]	29050	1			T1	29		T3	1		T4	2
valid_sources[0x1c]	30504	1			T1	17		T3	3		T4	8
valid_sources[0x1d]	32092	1			T2	1		T4	1		T6	1
valid_sources[0x1e]	30319	1			T1	24		T4	2		T6	13
valid_sources[0x1f]	29081	1			T1	13		T4	9		T8	38
valid_sources[0x20]	26967	1			T1	16		T3	1		T4	3
valid_sources[0x21]	27618	1			T1	8		T3	2		T4	1
valid_sources[0x22]	38541	1			T1	26		T4	2		T6	22
valid_sources[0x23]	30064	1			T1	7		T4	5		T8	44
valid_sources[0x24]	26720	1			T1	23		T4	2		T6	7
valid_sources[0x25]	27987	1			T1	19		T4	3		T5	1
valid_sources[0x26]	29402	1			T1	12		T4	2		T6	5
valid_sources[0x27]	29759	1			T1	12		T4	3		T6	19
valid_sources[0x28]	28499	1			T1	10		T4	3		T6	21
valid_sources[0x29]	27796	1			T1	30		T3	6		T4	8
valid_sources[0x2a]	28662	1			T1	6		T4	1		T6	8
valid_sources[0x2b]	29173	1			T1	12		T4	4		T5	4
valid_sources[0x2c]	30695	1			T1	9		T4	4		T6	10
valid_sources[0x2d]	27198	1			T1	12		T4	7		T8	56
valid_sources[0x2e]	27533	1			T1	21		T4	2		T6	3
valid_sources[0x2f]	26720	1			T1	18		T4	3		T8	44
valid_sources[0x30]	33103	1			T1	5		T4	4		T6	1
valid_sources[0x31]	37326	1			T1	17		T4	3		T6	4
valid_sources[0x32]	28940	1			T1	16		T3	1		T4	3
valid_sources[0x33]	30421	1			T1	5		T4	4		T6	13
valid_sources[0x34]	32853	1			T1	3		T4	2		T6	2
valid_sources[0x35]	29822	1			T1	11		T3	3		T4	1
valid_sources[0x36]	29322	1			T1	9		T4	6		T6	1
valid_sources[0x37]	32981	1			T1	14		T4	6		T6	9
valid_sources[0x38]	31028	1			T1	3		T4	2		T6	1
valid_sources[0x39]	29081	1			T1	4		T4	4		T6	11
valid_sources[0x3a]	29647	1			T1	2		T4	4		T6	4
valid_sources[0x3b]	26446	1			T1	14		T4	3		T6	5
valid_sources[0x3c]	25239	1			T1	16		T4	4		T6	31
valid_sources[0x3d]	28798	1			T1	18		T4	3		T6	2
valid_sources[0x3e]	27897	1			T1	8		T4	3		T6	1
valid_sources[0x3f]	26553	1			T1	17		T4	3		T6	3
valid_sources[0x40]	27801	1			T1	11		T4	3		T6	12
valid_sources[0x41]	33752	1			T1	9		T4	5		T6	6
valid_sources[0x42]	27734	1			T1	13		T3	2		T4	3
valid_sources[0x43]	27183	1			T1	12		T4	3		T6	4
valid_sources[0x44]	30059	1			T1	16		T4	2		T6	22
valid_sources[0x45]	32439	1			T1	11		T3	2		T4	2
valid_sources[0x46]	29790	1			T1	4		T4	6		T5	1
valid_sources[0x47]	29430	1			T1	16		T4	6		T6	6
valid_sources[0x48]	27120	1			T1	6		T4	2		T6	4
valid_sources[0x49]	27597	1			T1	6		T4	7		T6	11
valid_sources[0x4a]	30699	1			T1	18		T4	3		T5	1
valid_sources[0x4b]	35461	1			T1	12		T4	4		T6	1
valid_sources[0x4c]	26923	1			T1	18		T4	2		T6	1
valid_sources[0x4d]	28425	1			T1	5		T3	2		T4	6
valid_sources[0x4e]	29884	1			T1	12		T4	5		T5	179
valid_sources[0x4f]	28344	1			T1	18		T4	4		T6	21
valid_sources[0x50]	30140	1			T1	19		T4	4		T6	2
valid_sources[0x51]	27662	1			T1	29		T4	4		T6	16
valid_sources[0x52]	26522	1			T1	20		T4	6		T8	21
valid_sources[0x53]	31612	1			T1	20		T4	4		T6	8
valid_sources[0x54]	30500	1			T1	15		T3	3		T4	1
valid_sources[0x55]	32857	1			T1	16		T4	8		T6	7
valid_sources[0x56]	32003	1			T1	8		T4	2		T6	18
valid_sources[0x57]	28166	1			T1	11		T4	4		T6	18
valid_sources[0x58]	31649	1			T1	20		T4	4		T6	1
valid_sources[0x59]	31570	1			T1	14		T4	3		T8	37
valid_sources[0x5a]	27946	1			T1	9		T4	5		T6	3
valid_sources[0x5b]	26324	1			T1	16		T4	4		T6	25
valid_sources[0x5c]	29470	1			T1	8		T4	1		T6	9
valid_sources[0x5d]	32167	1			T1	13		T4	6		T6	1
valid_sources[0x5e]	28062	1			T1	8		T4	5		T6	12
valid_sources[0x5f]	28479	1			T1	19		T4	5		T6	22
valid_sources[0x60]	28839	1			T1	12		T4	3		T6	2
valid_sources[0x61]	33878	1			T1	12		T3	3		T4	3
valid_sources[0x62]	29582	1			T1	30		T3	5		T4	1
valid_sources[0x63]	33218	1			T1	14		T3	1		T4	2
valid_sources[0x64]	29402	1			T1	7		T4	3		T5	336
valid_sources[0x65]	38052	1			T1	11		T2	1		T5	1997
valid_sources[0x66]	27951	1			T1	26		T4	3		T7	1
valid_sources[0x67]	39811	1			T1	10		T4	5		T6	4
valid_sources[0x68]	29710	1			T1	10		T6	15		T8	49
valid_sources[0x69]	28633	1			T1	11		T4	5		T6	11
valid_sources[0x6a]	36602	1			T1	13		T3	2		T4	3
valid_sources[0x6b]	29312	1			T1	8		T3	1		T4	5
valid_sources[0x6c]	28827	1			T1	17		T4	3		T6	1
valid_sources[0x6d]	30191	1			T1	8		T4	3		T6	23
valid_sources[0x6e]	28552	1			T1	8		T4	8		T6	1
valid_sources[0x6f]	32256	1			T1	14		T4	5		T6	14
valid_sources[0x70]	28250	1			T1	29		T4	1		T6	4
valid_sources[0x71]	28153	1			T1	19		T4	6		T8	30
valid_sources[0x72]	28307	1			T1	10		T4	1		T5	1
valid_sources[0x73]	27759	1			T1	7		T4	1		T6	9
valid_sources[0x74]	28838	1			T1	15		T4	9		T6	3
valid_sources[0x75]	26968	1			T1	9		T3	2		T4	1
valid_sources[0x76]	25448	1			T1	20		T3	1		T4	7
valid_sources[0x77]	28862	1			T1	24		T4	3		T6	3
valid_sources[0x78]	28571	1			T1	14		T4	7		T6	12
valid_sources[0x79]	30838	1			T1	11		T4	2		T5	1
valid_sources[0x7a]	29009	1			T1	20		T3	2		T4	5
valid_sources[0x7b]	28741	1			T1	9		T3	1		T4	1
valid_sources[0x7c]	27391	1			T1	11		T4	2		T8	60
valid_sources[0x7d]	28150	1			T1	17		T4	2		T6	23
valid_sources[0x7e]	28124	1			T1	21		T4	5		T5	497
valid_sources[0x7f]	29019	1			T1	9		T4	1		T6	4
valid_sources[0x80]	28174	1			T1	17		T4	8		T6	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049410

1

T1

1237

T3

1

T4

4

values[0x0]

all_enables

biggest_size

1552392

1

T1

437

T2

1

T3

34

values[0x1]

all_enables

biggest_size

1527600

1

T1

443

T3

25

T4

439