Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3600079

1

T1

1183

T2

6

T3

10

full_word

4128646

1

T1

2117

T2

1

T3

60

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7728285	1			T1	3300		T2	7		T3	70
auto[TlIntgErrCmd]	160	1			T99	4		T100	9		T103	10
auto[TlIntgErrData]	131	1			T99	3		T100	11		T103	7
auto[TlIntgErrBoth]	149	1			T99	3		T100	10		T103	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4301618

1

T1

2414

T2

1

T3

1

auto[1]

3427107

1

T1

886

T2

6

T3

69

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3251799	1			T1	1177		T2	1		T4	4
auto[TlIntgErrNone]	partial	auto[1]	347871	1			T1	6		T2	5		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	1049626	1			T1	1237		T3	1		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	3078989	1			T1	880		T2	1		T3	59
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T100	3		T103	4		T125	1
auto[TlIntgErrCmd]	partial	auto[1]	90	1			T99	4		T100	6		T103	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T185	1		T186	2		T187	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T103	3		T125	2		T185	1
auto[TlIntgErrData]	partial	auto[0]	69	1			T99	2		T100	7		T103	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T99	1		T100	4		T103	5
auto[TlIntgErrData]	full_word	auto[0]	9	1			T125	1		T185	2		T188	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T188	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T99	1		T100	1		T103	7
auto[TlIntgErrBoth]	partial	auto[1]	92	1			T99	2		T100	9		T103	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T127	1		T189	1		T190	2
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T191	1		-	-		-	-