Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	100.00	86.11		100.00	97.87	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8
1	1	Covered	T5,T8,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T5,T8,T10
1	1	Covered	T1,T5,T8

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1357192434	2526	0	0
SrcPulseCheck_M	433960887	2526	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1357192434	2526	0	0
T1	63935	1	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	0	0	0
T5	649122	4	0	0
T6	124436	0	0	0
T7	2972	0	0	0
T8	291858	14	0	0
T9	42096	0	0	0
T10	35514	7	0	0
T11	1429330	0	0	0
T12	1026762	3	0	0
T13	258809	11	0	0
T14	43059	0	0	0
T15	0	18	0	0
T25	0	7	0	0
T26	0	1	0	0
T29	116194	0	0	0
T30	2396	0	0	0
T31	1043	0	0	0
T32	390270	6	0	0
T33	0	8	0	0
T47	0	2	0	0
T48	0	6	0	0
T49	2442	0	0	0
T50	0	6	0	0
T75	0	7	0	0
T153	0	7	0	0
T154	0	7	0	0
T155	0	7	0	0
T156	0	7	0	0
T157	0	7	0	0
T158	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433960887	2526	0	0
T1	59910	1	0	0
T3	11137	0	0	0
T4	159824	0	0	0
T5	300584	4	0	0
T6	56768	0	0	0
T8	1375614	14	0	0
T9	146000	0	0	0
T10	50706	7	0	0
T11	304914	0	0	0
T12	2520264	3	0	0
T13	1704430	11	0	0
T14	10024	0	0	0
T15	0	18	0	0
T25	0	7	0	0
T26	0	1	0	0
T29	234764	0	0	0
T30	2480	0	0	0
T32	367858	6	0	0
T33	710298	8	0	0
T47	0	2	0	0
T48	0	6	0	0
T50	0	6	0	0
T75	0	7	0	0
T97	65082	0	0	0
T153	0	7	0	0
T154	0	7	0	0
T155	0	7	0	0
T156	0	7	0	0
T157	0	7	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T10,T50
1	0	Covered	T1,T10,T50
1	1	Covered	T10,T50,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T50
1	0	Covered	T10,T50,T25
1	1	Covered	T1,T10,T50

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	452397478	171	0	0
SrcPulseCheck_M	144653629	171	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	171	0	0
T1	63935	1	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	0	0	0
T5	324561	0	0	0
T6	62218	0	0	0
T7	1486	0	0	0
T8	145929	0	0	0
T9	21048	0	0	0
T10	11838	2	0	0
T25	0	2	0	0
T50	0	3	0	0
T75	0	2	0	0
T153	0	2	0	0
T154	0	4	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	171	0	0
T1	59910	1	0	0
T3	11137	0	0	0
T4	159824	0	0	0
T5	150292	0	0	0
T6	28384	0	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	2	0	0
T11	101638	0	0	0
T12	840088	0	0	0
T25	0	2	0	0
T50	0	3	0	0
T75	0	2	0	0
T153	0	2	0	0
T154	0	4	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T10,T50,T25
1	0	Covered	T10,T50,T25
1	1	Covered	T10,T50,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T50,T25
1	0	Covered	T10,T50,T25
1	1	Covered	T10,T50,T25

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	452397478	324	0	0
SrcPulseCheck_M	144653629	324	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	324	0	0
T10	11838	5	0	0
T11	714665	0	0	0
T12	513381	0	0	0
T13	258809	0	0	0
T14	43059	0	0	0
T25	0	5	0	0
T29	58097	0	0	0
T30	2396	0	0	0
T31	1043	0	0	0
T32	390270	0	0	0
T49	1221	0	0	0
T50	0	3	0	0
T75	0	5	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	5	0	0
T158	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	324	0	0
T10	16902	5	0	0
T11	101638	0	0	0
T12	840088	0	0	0
T13	852215	0	0	0
T14	10024	0	0	0
T25	0	5	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	367858	0	0	0
T33	710298	0	0	0
T50	0	3	0	0
T75	0	5	0	0
T97	65082	0	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	5	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T5,T8,T12
1	0	Covered	T5,T8,T12
1	1	Covered	T5,T8,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T12
1	0	Covered	T5,T8,T12
1	1	Covered	T5,T8,T12

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	452397478	2031	0	0
SrcPulseCheck_M	144653629	2031	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2031	0	0
T5	324561	4	0	0
T6	62218	0	0	0
T7	1486	0	0	0
T8	145929	14	0	0
T9	21048	0	0	0
T10	11838	0	0	0
T11	714665	0	0	0
T12	513381	3	0	0
T13	0	11	0	0
T15	0	18	0	0
T26	0	1	0	0
T29	58097	0	0	0
T32	0	6	0	0
T33	0	8	0	0
T47	0	2	0	0
T48	0	6	0	0
T49	1221	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	2031	0	0
T5	150292	4	0	0
T6	28384	0	0	0
T8	687807	14	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3	0	0
T13	852215	11	0	0
T15	0	18	0	0
T26	0	1	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	6	0	0
T33	0	8	0	0
T47	0	2	0	0
T48	0	6	0	0