Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454754723	2711014	0	0
DepthKnown_A	454754723	454616629	0	0
RvalidKnown_A	454754723	454616629	0	0
WreadyKnown_A	454754723	454616629	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	2711014	0	0
T1	63935	1671	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	1663	0	0
T5	324561	8328	0	0
T6	62218	0	0	0
T7	1486	0	0	0
T8	145929	10835	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	1667	0	0
T12	0	6654	0	0
T13	0	8319	0	0
T14	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454754723	2881227	0	0
DepthKnown_A	454754723	454616629	0	0
RvalidKnown_A	454754723	454616629	0	0
WreadyKnown_A	454754723	454616629	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	2881227	0	0
T1	63935	840	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	7971	0	0
T6	62218	0	0	0
T7	1486	0	0	0
T8	145929	22189	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	836	0	0
T12	0	17680	0	0
T13	0	13772	0	0
T14	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454754723	181755	0	0
DepthKnown_A	454754723	454616629	0	0
RvalidKnown_A	454754723	454616629	0	0
WreadyKnown_A	454754723	454616629	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	181755	0	0
T5	324561	75	0	0
T6	62218	250	0	0
T7	1486	0	0	0
T8	145929	474	0	0
T9	21048	0	0	0
T10	11838	0	0	0
T11	714665	0	0	0
T12	513381	1230	0	0
T13	0	742	0	0
T29	58097	0	0	0
T30	0	16	0	0
T32	0	1207	0	0
T33	0	923	0	0
T47	0	128	0	0
T48	0	609	0	0
T49	1221	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454754723	392675	0	0
DepthKnown_A	454754723	454616629	0	0
RvalidKnown_A	454754723	454616629	0	0
WreadyKnown_A	454754723	454616629	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	392675	0	0
T5	324561	344	0	0
T6	62218	250	0	0
T7	1486	0	0	0
T8	145929	2071	0	0
T9	21048	0	0	0
T10	11838	0	0	0
T11	714665	0	0	0
T12	513381	5839	0	0
T13	0	1985	0	0
T29	58097	0	0	0
T30	0	16	0	0
T32	0	1207	0	0
T33	0	4134	0	0
T47	0	617	0	0
T48	0	2562	0	0
T49	1221	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454754723	6186885	0	0
DepthKnown_A	454754723	454616629	0	0
RvalidKnown_A	454754723	454616629	0	0
WreadyKnown_A	454754723	454616629	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	6186885	0	0
T1	63935	2479	0	0
T2	1357	7	0	0
T3	13041	70	0	0
T4	112218	69	0	0
T5	324561	1184	0	0
T6	62218	1585	0	0
T7	1486	47	0	0
T8	145929	2835	0	0
T9	21048	61	0	0
T10	11838	302	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454754723	12084627	0	0
DepthKnown_A	454754723	454616629	0	0
RvalidKnown_A	454754723	454616629	0	0
WreadyKnown_A	454754723	454616629	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	12084627	0	0
T1	63935	10557	0	0
T2	1357	7	0	0
T3	13041	70	0	0
T4	112218	69	0	0
T5	324561	4124	0	0
T6	62218	1565	0	0
T7	1486	47	0	0
T8	145929	12296	0	0
T9	21048	61	0	0
T10	11838	302	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454754723	454616629	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0