Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T30
1	0	Covered	T6,T12,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T12
1	0	Unreachable
1	1	Covered	T6,T12,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T12
1	0	Covered	T5,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T5,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	741704736	595678586	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	741704736	3496020	0	0
GntImpliesValid_A	741704736	3496020	0	0
GrantKnown_A	741704736	595678586	0	0
IdxKnown_A	741704736	595678586	0	0
IndexIsCorrect_A	741704736	3496020	0	0
LockArbDecision_A	741704736	0	0	0
NoReadyValidNoGrant_A	741704736	0	0	0
ReadyAndValidImplyGrant_A	741704736	3496020	0	0
ReqAndReadyImplyGrant_A	741704736	3496020	0	0
ReqImpliesValid_A	741704736	3496020	0	0
ReqStaysHighUntilGranted0_M	741704736	0	0	0
RoundRobin_A	741704736	5	0	976
ValidKnown_A	741704736	595678586	0	0
gen_data_port_assertion.DataFlow_A	741704736	3496020	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	595678586	0	0
T1	123845	123786	0	0
T2	1357	1293	0	0
T3	35315	23845	0	0
T4	431866	272034	0	0
T5	625145	472870	0	0
T6	118986	89292	0	0
T7	1486	1436	0	0
T8	1521543	831007	0	0
T9	167048	93617	0	0
T10	45642	28645	0	0
T11	203276	101638	0	0
T12	1680176	831397	0	0
T13	0	845543	0	0
T14	0	10024	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	3496020	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	474853	5384	0	0
T6	118986	1736	0	0
T7	1486	0	0	0
T8	1521543	10680	0	0
T9	167048	832	0	0
T10	45642	832	0	0
T11	203276	832	0	0
T12	1680176	19102	0	0
T13	1704430	6733	0	0
T14	10024	0	0	0
T15	0	16104	0	0
T26	0	257	0	0
T29	234764	0	0	0
T30	2480	112	0	0
T32	0	7130	0	0
T33	0	4994	0	0
T47	0	1028	0	0
T48	0	5671	0	0
T52	0	431	0	0
T53	0	1001	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	3496020	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	474853	5384	0	0
T6	118986	1736	0	0
T7	1486	0	0	0
T8	1521543	10680	0	0
T9	167048	832	0	0
T10	45642	832	0	0
T11	203276	832	0	0
T12	1680176	19102	0	0
T13	1704430	6733	0	0
T14	10024	0	0	0
T15	0	16104	0	0
T26	0	257	0	0
T29	234764	0	0	0
T30	2480	112	0	0
T32	0	7130	0	0
T33	0	4994	0	0
T47	0	1028	0	0
T48	0	5671	0	0
T52	0	431	0	0
T53	0	1001	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	595678586	0	0
T1	123845	123786	0	0
T2	1357	1293	0	0
T3	35315	23845	0	0
T4	431866	272034	0	0
T5	625145	472870	0	0
T6	118986	89292	0	0
T7	1486	1436	0	0
T8	1521543	831007	0	0
T9	167048	93617	0	0
T10	45642	28645	0	0
T11	203276	101638	0	0
T12	1680176	831397	0	0
T13	0	845543	0	0
T14	0	10024	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	595678586	0	0
T1	123845	123786	0	0
T2	1357	1293	0	0
T3	35315	23845	0	0
T4	431866	272034	0	0
T5	625145	472870	0	0
T6	118986	89292	0	0
T7	1486	1436	0	0
T8	1521543	831007	0	0
T9	167048	93617	0	0
T10	45642	28645	0	0
T11	203276	101638	0	0
T12	1680176	831397	0	0
T13	0	845543	0	0
T14	0	10024	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	3496020	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	474853	5384	0	0
T6	118986	1736	0	0
T7	1486	0	0	0
T8	1521543	10680	0	0
T9	167048	832	0	0
T10	45642	832	0	0
T11	203276	832	0	0
T12	1680176	19102	0	0
T13	1704430	6733	0	0
T14	10024	0	0	0
T15	0	16104	0	0
T26	0	257	0	0
T29	234764	0	0	0
T30	2480	112	0	0
T32	0	7130	0	0
T33	0	4994	0	0
T47	0	1028	0	0
T48	0	5671	0	0
T52	0	431	0	0
T53	0	1001	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	3496020	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	474853	5384	0	0
T6	118986	1736	0	0
T7	1486	0	0	0
T8	1521543	10680	0	0
T9	167048	832	0	0
T10	45642	832	0	0
T11	203276	832	0	0
T12	1680176	19102	0	0
T13	1704430	6733	0	0
T14	10024	0	0	0
T15	0	16104	0	0
T26	0	257	0	0
T29	234764	0	0	0
T30	2480	112	0	0
T32	0	7130	0	0
T33	0	4994	0	0
T47	0	1028	0	0
T48	0	5671	0	0
T52	0	431	0	0
T53	0	1001	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	3496020	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	474853	5384	0	0
T6	118986	1736	0	0
T7	1486	0	0	0
T8	1521543	10680	0	0
T9	167048	832	0	0
T10	45642	832	0	0
T11	203276	832	0	0
T12	1680176	19102	0	0
T13	1704430	6733	0	0
T14	10024	0	0	0
T15	0	16104	0	0
T26	0	257	0	0
T29	234764	0	0	0
T30	2480	112	0	0
T32	0	7130	0	0
T33	0	4994	0	0
T47	0	1028	0	0
T48	0	5671	0	0
T52	0	431	0	0
T53	0	1001	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	3496020	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	474853	5384	0	0
T6	118986	1736	0	0
T7	1486	0	0	0
T8	1521543	10680	0	0
T9	167048	832	0	0
T10	45642	832	0	0
T11	203276	832	0	0
T12	1680176	19102	0	0
T13	1704430	6733	0	0
T14	10024	0	0	0
T15	0	16104	0	0
T26	0	257	0	0
T29	234764	0	0	0
T30	2480	112	0	0
T32	0	7130	0	0
T33	0	4994	0	0
T47	0	1028	0	0
T48	0	5671	0	0
T52	0	431	0	0
T53	0	1001	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	5	0	976
T36	0	1	0	0
T48	289571	1	0	1
T50	202492	0	0	1
T52	50390	0	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	9857	0	0	1
T58	89220	0	0	1
T59	1342	0	0	1
T60	1789	0	0	1
T61	1051	0	0	1
T62	38247	0	0	1
T63	1024	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	595678586	0	0
T1	123845	123786	0	0
T2	1357	1293	0	0
T3	35315	23845	0	0
T4	431866	272034	0	0
T5	625145	472870	0	0
T6	118986	89292	0	0
T7	1486	1436	0	0
T8	1521543	831007	0	0
T9	167048	93617	0	0
T10	45642	28645	0	0
T11	203276	101638	0	0
T12	1680176	831397	0	0
T13	0	845543	0	0
T14	0	10024	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741704736	3496020	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	474853	5384	0	0
T6	118986	1736	0	0
T7	1486	0	0	0
T8	1521543	10680	0	0
T9	167048	832	0	0
T10	45642	832	0	0
T11	203276	832	0	0
T12	1680176	19102	0	0
T13	1704430	6733	0	0
T14	10024	0	0	0
T15	0	16104	0	0
T26	0	257	0	0
T29	234764	0	0	0
T30	2480	112	0	0
T32	0	7130	0	0
T33	0	4994	0	0
T47	0	1028	0	0
T48	0	5671	0	0
T52	0	431	0	0
T53	0	1001	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T30
1	0	Covered	T6,T12,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T12
1	0	Unreachable
1	1	Covered	T6,T12,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T12,T30
0	0	1	Unreachable
0	0	0	Covered	T3,T6,T12

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144653629	28743337	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	144653629	621376	0	0
GntImpliesValid_A	144653629	621376	0	0
GrantKnown_A	144653629	28743337	0	0
IdxKnown_A	144653629	28743337	0	0
IndexIsCorrect_A	144653629	621376	0	0
LockArbDecision_A	144653629	0	0	0
NoReadyValidNoGrant_A	144653629	0	0	0
ReadyAndValidImplyGrant_A	144653629	621376	0	0
ReqAndReadyImplyGrant_A	144653629	621376	0	0
ReqImpliesValid_A	144653629	621376	0	0
ReqStaysHighUntilGranted0_M	144653629	0	0	0
RoundRobin_A	144653629	0	0	0
ValidKnown_A	144653629	28743337	0	0
gen_data_port_assertion.DataFlow_A	144653629	621376	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	28743337	0	0
T3	11137	10864	0	0
T4	159824	0	0	0
T5	150292	0	0	0
T6	28384	27152	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	494488	0	0
T13	0	194328	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	621376	0	0
T6	28384	1245	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	7296	0	0
T13	852215	1715	0	0
T14	10024	0	0	0
T15	0	7759	0	0
T29	117382	0	0	0
T30	1240	80	0	0
T32	0	6474	0	0
T33	0	2979	0	0
T48	0	2455	0	0
T52	0	431	0	0
T53	0	1001	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	621376	0	0
T6	28384	1245	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	7296	0	0
T13	852215	1715	0	0
T14	10024	0	0	0
T15	0	7759	0	0
T29	117382	0	0	0
T30	1240	80	0	0
T32	0	6474	0	0
T33	0	2979	0	0
T48	0	2455	0	0
T52	0	431	0	0
T53	0	1001	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	28743337	0	0
T3	11137	10864	0	0
T4	159824	0	0	0
T5	150292	0	0	0
T6	28384	27152	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	494488	0	0
T13	0	194328	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	28743337	0	0
T3	11137	10864	0	0
T4	159824	0	0	0
T5	150292	0	0	0
T6	28384	27152	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	494488	0	0
T13	0	194328	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	621376	0	0
T6	28384	1245	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	7296	0	0
T13	852215	1715	0	0
T14	10024	0	0	0
T15	0	7759	0	0
T29	117382	0	0	0
T30	1240	80	0	0
T32	0	6474	0	0
T33	0	2979	0	0
T48	0	2455	0	0
T52	0	431	0	0
T53	0	1001	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	621376	0	0
T6	28384	1245	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	7296	0	0
T13	852215	1715	0	0
T14	10024	0	0	0
T15	0	7759	0	0
T29	117382	0	0	0
T30	1240	80	0	0
T32	0	6474	0	0
T33	0	2979	0	0
T48	0	2455	0	0
T52	0	431	0	0
T53	0	1001	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	621376	0	0
T6	28384	1245	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	7296	0	0
T13	852215	1715	0	0
T14	10024	0	0	0
T15	0	7759	0	0
T29	117382	0	0	0
T30	1240	80	0	0
T32	0	6474	0	0
T33	0	2979	0	0
T48	0	2455	0	0
T52	0	431	0	0
T53	0	1001	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	621376	0	0
T6	28384	1245	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	7296	0	0
T13	852215	1715	0	0
T14	10024	0	0	0
T15	0	7759	0	0
T29	117382	0	0	0
T30	1240	80	0	0
T32	0	6474	0	0
T33	0	2979	0	0
T48	0	2455	0	0
T52	0	431	0	0
T53	0	1001	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	28743337	0	0
T3	11137	10864	0	0
T4	159824	0	0	0
T5	150292	0	0	0
T6	28384	27152	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	494488	0	0
T13	0	194328	0	0
T29	117382	112456	0	0
T30	0	1240	0	0
T32	0	259968	0	0
T33	0	137728	0	0
T34	0	17272	0	0
T35	0	74328	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	621376	0	0
T6	28384	1245	0	0
T8	687807	0	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	7296	0	0
T13	852215	1715	0	0
T14	10024	0	0	0
T15	0	7759	0	0
T29	117382	0	0	0
T30	1240	80	0	0
T32	0	6474	0	0
T33	0	2979	0	0
T48	0	2455	0	0
T52	0	431	0	0
T53	0	1001	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T12
1	0	Covered	T5,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T5,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144653629	114628268	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	144653629	736169	0	0
GntImpliesValid_A	144653629	736169	0	0
GrantKnown_A	144653629	114628268	0	0
IdxKnown_A	144653629	114628268	0	0
IndexIsCorrect_A	144653629	736169	0	0
LockArbDecision_A	144653629	0	0	0
NoReadyValidNoGrant_A	144653629	0	0	0
ReadyAndValidImplyGrant_A	144653629	736169	0	0
ReqAndReadyImplyGrant_A	144653629	736169	0	0
ReqImpliesValid_A	144653629	736169	0	0
ReqStaysHighUntilGranted0_M	144653629	0	0	0
RoundRobin_A	144653629	0	0	0
ValidKnown_A	144653629	114628268	0	0
gen_data_port_assertion.DataFlow_A	144653629	736169	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	114628268	0	0
T1	59910	59910	0	0
T3	11137	0	0	0
T4	159824	159824	0	0
T5	150292	148393	0	0
T6	28384	0	0	0
T8	687807	685083	0	0
T9	73000	72638	0	0
T10	16902	16902	0	0
T11	101638	101638	0	0
T12	840088	336909	0	0
T13	0	651215	0	0
T14	0	10024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	736169	0	0
T5	150292	309	0	0
T6	28384	0	0	0
T8	687807	2693	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3002	0	0
T13	852215	5018	0	0
T15	0	8345	0	0
T26	0	257	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	656	0	0
T33	0	2015	0	0
T47	0	1028	0	0
T48	0	3216	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	736169	0	0
T5	150292	309	0	0
T6	28384	0	0	0
T8	687807	2693	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3002	0	0
T13	852215	5018	0	0
T15	0	8345	0	0
T26	0	257	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	656	0	0
T33	0	2015	0	0
T47	0	1028	0	0
T48	0	3216	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	114628268	0	0
T1	59910	59910	0	0
T3	11137	0	0	0
T4	159824	159824	0	0
T5	150292	148393	0	0
T6	28384	0	0	0
T8	687807	685083	0	0
T9	73000	72638	0	0
T10	16902	16902	0	0
T11	101638	101638	0	0
T12	840088	336909	0	0
T13	0	651215	0	0
T14	0	10024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	114628268	0	0
T1	59910	59910	0	0
T3	11137	0	0	0
T4	159824	159824	0	0
T5	150292	148393	0	0
T6	28384	0	0	0
T8	687807	685083	0	0
T9	73000	72638	0	0
T10	16902	16902	0	0
T11	101638	101638	0	0
T12	840088	336909	0	0
T13	0	651215	0	0
T14	0	10024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	736169	0	0
T5	150292	309	0	0
T6	28384	0	0	0
T8	687807	2693	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3002	0	0
T13	852215	5018	0	0
T15	0	8345	0	0
T26	0	257	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	656	0	0
T33	0	2015	0	0
T47	0	1028	0	0
T48	0	3216	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	736169	0	0
T5	150292	309	0	0
T6	28384	0	0	0
T8	687807	2693	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3002	0	0
T13	852215	5018	0	0
T15	0	8345	0	0
T26	0	257	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	656	0	0
T33	0	2015	0	0
T47	0	1028	0	0
T48	0	3216	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	736169	0	0
T5	150292	309	0	0
T6	28384	0	0	0
T8	687807	2693	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3002	0	0
T13	852215	5018	0	0
T15	0	8345	0	0
T26	0	257	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	656	0	0
T33	0	2015	0	0
T47	0	1028	0	0
T48	0	3216	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	736169	0	0
T5	150292	309	0	0
T6	28384	0	0	0
T8	687807	2693	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3002	0	0
T13	852215	5018	0	0
T15	0	8345	0	0
T26	0	257	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	656	0	0
T33	0	2015	0	0
T47	0	1028	0	0
T48	0	3216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	114628268	0	0
T1	59910	59910	0	0
T3	11137	0	0	0
T4	159824	159824	0	0
T5	150292	148393	0	0
T6	28384	0	0	0
T8	687807	685083	0	0
T9	73000	72638	0	0
T10	16902	16902	0	0
T11	101638	101638	0	0
T12	840088	336909	0	0
T13	0	651215	0	0
T14	0	10024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144653629	736169	0	0
T5	150292	309	0	0
T6	28384	0	0	0
T8	687807	2693	0	0
T9	73000	0	0	0
T10	16902	0	0	0
T11	101638	0	0	0
T12	840088	3002	0	0
T13	852215	5018	0	0
T15	0	8345	0	0
T26	0	257	0	0
T29	117382	0	0	0
T30	1240	0	0	0
T32	0	656	0	0
T33	0	2015	0	0
T47	0	1028	0	0
T48	0	3216	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452397478	452306981	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	452397478	2138475	0	0
GntImpliesValid_A	452397478	2138475	0	0
GrantKnown_A	452397478	452306981	0	0
IdxKnown_A	452397478	452306981	0	0
IndexIsCorrect_A	452397478	2138475	0	0
LockArbDecision_A	452397478	0	0	0
NoReadyValidNoGrant_A	452397478	0	0	0
ReadyAndValidImplyGrant_A	452397478	2138475	0	0
ReqAndReadyImplyGrant_A	452397478	2138475	0	0
ReqImpliesValid_A	452397478	2138475	0	0
ReqStaysHighUntilGranted0_M	452397478	0	0	0
RoundRobin_A	452397478	5	0	976
ValidKnown_A	452397478	452306981	0	0
gen_data_port_assertion.DataFlow_A	452397478	2138475	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	452306981	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2138475	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	5075	0	0
T6	62218	491	0	0
T7	1486	0	0	0
T8	145929	7987	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	832	0	0
T12	0	8804	0	0
T30	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2138475	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	5075	0	0
T6	62218	491	0	0
T7	1486	0	0	0
T8	145929	7987	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	832	0	0
T12	0	8804	0	0
T30	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	452306981	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	452306981	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2138475	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	5075	0	0
T6	62218	491	0	0
T7	1486	0	0	0
T8	145929	7987	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	832	0	0
T12	0	8804	0	0
T30	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2138475	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	5075	0	0
T6	62218	491	0	0
T7	1486	0	0	0
T8	145929	7987	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	832	0	0
T12	0	8804	0	0
T30	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2138475	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	5075	0	0
T6	62218	491	0	0
T7	1486	0	0	0
T8	145929	7987	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	832	0	0
T12	0	8804	0	0
T30	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2138475	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	5075	0	0
T6	62218	491	0	0
T7	1486	0	0	0
T8	145929	7987	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	832	0	0
T12	0	8804	0	0
T30	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	5	0	976
T36	0	1	0	0
T48	289571	1	0	1
T50	202492	0	0	1
T52	50390	0	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	9857	0	0	1
T58	89220	0	0	1
T59	1342	0	0	1
T60	1789	0	0	1
T61	1051	0	0	1
T62	38247	0	0	1
T63	1024	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	452306981	0	0
T1	63935	63876	0	0
T2	1357	1293	0	0
T3	13041	12981	0	0
T4	112218	112210	0	0
T5	324561	324477	0	0
T6	62218	62140	0	0
T7	1486	1436	0	0
T8	145929	145924	0	0
T9	21048	20979	0	0
T10	11838	11743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452397478	2138475	0	0
T1	63935	832	0	0
T2	1357	0	0	0
T3	13041	0	0	0
T4	112218	832	0	0
T5	324561	5075	0	0
T6	62218	491	0	0
T7	1486	0	0	0
T8	145929	7987	0	0
T9	21048	832	0	0
T10	11838	832	0	0
T11	0	832	0	0
T12	0	8804	0	0
T30	0	32	0	0