Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
3473 |
0 |
0 |
T98 |
13833 |
133 |
0 |
0 |
T99 |
10882 |
1 |
0 |
0 |
T100 |
28451 |
3 |
0 |
0 |
T101 |
5561 |
220 |
0 |
0 |
T102 |
5138 |
2 |
0 |
0 |
T103 |
102042 |
4 |
0 |
0 |
T104 |
4339 |
14 |
0 |
0 |
T105 |
4058 |
11 |
0 |
0 |
T125 |
29645 |
5 |
0 |
0 |
T126 |
16028 |
9 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1585 |
0 |
0 |
T82 |
2082 |
7 |
0 |
0 |
T103 |
102042 |
141 |
0 |
0 |
T126 |
16028 |
23 |
0 |
0 |
T127 |
34403 |
37 |
0 |
0 |
T128 |
63814 |
47 |
0 |
0 |
T131 |
9715 |
11 |
0 |
0 |
T138 |
11200 |
3 |
0 |
0 |
T159 |
96521 |
101 |
0 |
0 |
T160 |
102449 |
106 |
0 |
0 |
T161 |
99347 |
119 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1318 |
0 |
0 |
T103 |
102042 |
148 |
0 |
0 |
T115 |
21157 |
1 |
0 |
0 |
T126 |
16028 |
25 |
0 |
0 |
T127 |
34403 |
40 |
0 |
0 |
T128 |
63814 |
26 |
0 |
0 |
T131 |
9715 |
3 |
0 |
0 |
T138 |
11200 |
7 |
0 |
0 |
T159 |
96521 |
61 |
0 |
0 |
T160 |
102449 |
125 |
0 |
0 |
T161 |
99347 |
99 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1932 |
0 |
0 |
T82 |
2082 |
1 |
0 |
0 |
T103 |
102042 |
245 |
0 |
0 |
T115 |
21157 |
2 |
0 |
0 |
T126 |
16028 |
42 |
0 |
0 |
T127 |
34403 |
76 |
0 |
0 |
T128 |
63814 |
90 |
0 |
0 |
T131 |
9715 |
8 |
0 |
0 |
T138 |
11200 |
17 |
0 |
0 |
T159 |
96521 |
147 |
0 |
0 |
T160 |
102449 |
185 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
9171 |
0 |
0 |
T82 |
2082 |
3 |
0 |
0 |
T103 |
102042 |
2046 |
0 |
0 |
T115 |
21157 |
4 |
0 |
0 |
T126 |
16028 |
245 |
0 |
0 |
T127 |
34403 |
383 |
0 |
0 |
T128 |
63814 |
681 |
0 |
0 |
T131 |
9715 |
146 |
0 |
0 |
T138 |
11200 |
266 |
0 |
0 |
T159 |
96521 |
908 |
0 |
0 |
T160 |
102449 |
1182 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
10896 |
0 |
0 |
T82 |
2082 |
3 |
0 |
0 |
T103 |
102042 |
1624 |
0 |
0 |
T112 |
16802 |
4 |
0 |
0 |
T126 |
16028 |
152 |
0 |
0 |
T127 |
34403 |
536 |
0 |
0 |
T128 |
63814 |
454 |
0 |
0 |
T131 |
9715 |
181 |
0 |
0 |
T138 |
11200 |
141 |
0 |
0 |
T159 |
96521 |
773 |
0 |
0 |
T160 |
102449 |
1850 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
11011 |
0 |
0 |
T82 |
2082 |
4 |
0 |
0 |
T103 |
102042 |
1802 |
0 |
0 |
T126 |
16028 |
28 |
0 |
0 |
T127 |
34403 |
966 |
0 |
0 |
T128 |
63814 |
791 |
0 |
0 |
T131 |
9715 |
78 |
0 |
0 |
T138 |
11200 |
114 |
0 |
0 |
T159 |
96521 |
1175 |
0 |
0 |
T160 |
102449 |
1539 |
0 |
0 |
T161 |
99347 |
1757 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
12180 |
0 |
0 |
T103 |
102042 |
2565 |
0 |
0 |
T126 |
16028 |
131 |
0 |
0 |
T127 |
34403 |
499 |
0 |
0 |
T128 |
63814 |
762 |
0 |
0 |
T131 |
9715 |
155 |
0 |
0 |
T138 |
11200 |
251 |
0 |
0 |
T159 |
96521 |
1367 |
0 |
0 |
T160 |
102449 |
1913 |
0 |
0 |
T161 |
99347 |
1860 |
0 |
0 |
T162 |
13684 |
69 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
11173 |
0 |
0 |
T103 |
102042 |
1541 |
0 |
0 |
T116 |
17708 |
6 |
0 |
0 |
T126 |
16028 |
379 |
0 |
0 |
T127 |
34403 |
802 |
0 |
0 |
T128 |
63814 |
643 |
0 |
0 |
T131 |
9715 |
75 |
0 |
0 |
T138 |
11200 |
146 |
0 |
0 |
T159 |
96521 |
821 |
0 |
0 |
T160 |
102449 |
2134 |
0 |
0 |
T161 |
99347 |
2152 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
10943 |
0 |
0 |
T82 |
2082 |
3 |
0 |
0 |
T103 |
102042 |
2202 |
0 |
0 |
T126 |
16028 |
287 |
0 |
0 |
T127 |
34403 |
655 |
0 |
0 |
T128 |
63814 |
702 |
0 |
0 |
T131 |
9715 |
131 |
0 |
0 |
T138 |
11200 |
239 |
0 |
0 |
T159 |
96521 |
718 |
0 |
0 |
T160 |
102449 |
1840 |
0 |
0 |
T161 |
99347 |
2172 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
10162 |
0 |
0 |
T82 |
2082 |
3 |
0 |
0 |
T103 |
102042 |
2101 |
0 |
0 |
T126 |
16028 |
138 |
0 |
0 |
T127 |
34403 |
680 |
0 |
0 |
T128 |
63814 |
723 |
0 |
0 |
T131 |
9715 |
7 |
0 |
0 |
T138 |
11200 |
132 |
0 |
0 |
T159 |
96521 |
1049 |
0 |
0 |
T160 |
102449 |
1274 |
0 |
0 |
T161 |
99347 |
1908 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
10382 |
0 |
0 |
T82 |
2082 |
8 |
0 |
0 |
T103 |
102042 |
1861 |
0 |
0 |
T126 |
16028 |
374 |
0 |
0 |
T127 |
34403 |
356 |
0 |
0 |
T128 |
63814 |
544 |
0 |
0 |
T131 |
9715 |
46 |
0 |
0 |
T138 |
11200 |
7 |
0 |
0 |
T159 |
96521 |
1070 |
0 |
0 |
T160 |
102449 |
1738 |
0 |
0 |
T161 |
99347 |
2394 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5500 |
0 |
0 |
T82 |
2082 |
8 |
0 |
0 |
T103 |
102042 |
884 |
0 |
0 |
T126 |
16028 |
26 |
0 |
0 |
T127 |
34403 |
277 |
0 |
0 |
T128 |
63814 |
383 |
0 |
0 |
T131 |
9715 |
39 |
0 |
0 |
T138 |
11200 |
90 |
0 |
0 |
T159 |
96521 |
407 |
0 |
0 |
T160 |
102449 |
804 |
0 |
0 |
T161 |
99347 |
975 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5047 |
0 |
0 |
T103 |
102042 |
903 |
0 |
0 |
T126 |
16028 |
102 |
0 |
0 |
T127 |
34403 |
288 |
0 |
0 |
T128 |
63814 |
277 |
0 |
0 |
T131 |
9715 |
14 |
0 |
0 |
T138 |
11200 |
161 |
0 |
0 |
T159 |
96521 |
346 |
0 |
0 |
T160 |
102449 |
770 |
0 |
0 |
T161 |
99347 |
763 |
0 |
0 |
T162 |
13684 |
50 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4892 |
0 |
0 |
T103 |
102042 |
914 |
0 |
0 |
T126 |
16028 |
60 |
0 |
0 |
T127 |
34403 |
261 |
0 |
0 |
T128 |
63814 |
248 |
0 |
0 |
T131 |
9715 |
38 |
0 |
0 |
T138 |
11200 |
144 |
0 |
0 |
T159 |
96521 |
343 |
0 |
0 |
T160 |
102449 |
860 |
0 |
0 |
T161 |
99347 |
613 |
0 |
0 |
T162 |
13684 |
37 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4985 |
0 |
0 |
T98 |
13833 |
1 |
0 |
0 |
T103 |
102042 |
787 |
0 |
0 |
T126 |
16028 |
133 |
0 |
0 |
T127 |
34403 |
216 |
0 |
0 |
T128 |
63814 |
339 |
0 |
0 |
T131 |
9715 |
45 |
0 |
0 |
T138 |
11200 |
66 |
0 |
0 |
T159 |
96521 |
407 |
0 |
0 |
T160 |
102449 |
715 |
0 |
0 |
T161 |
99347 |
729 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4842 |
0 |
0 |
T103 |
102042 |
604 |
0 |
0 |
T111 |
11528 |
2 |
0 |
0 |
T126 |
16028 |
126 |
0 |
0 |
T127 |
34403 |
200 |
0 |
0 |
T128 |
63814 |
252 |
0 |
0 |
T131 |
9715 |
7 |
0 |
0 |
T138 |
11200 |
105 |
0 |
0 |
T159 |
96521 |
391 |
0 |
0 |
T160 |
102449 |
694 |
0 |
0 |
T161 |
99347 |
743 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4594 |
0 |
0 |
T82 |
2082 |
6 |
0 |
0 |
T103 |
102042 |
638 |
0 |
0 |
T126 |
16028 |
17 |
0 |
0 |
T127 |
34403 |
199 |
0 |
0 |
T128 |
63814 |
160 |
0 |
0 |
T131 |
9715 |
67 |
0 |
0 |
T138 |
11200 |
88 |
0 |
0 |
T159 |
96521 |
441 |
0 |
0 |
T160 |
102449 |
732 |
0 |
0 |
T161 |
99347 |
764 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5327 |
0 |
0 |
T82 |
2082 |
1 |
0 |
0 |
T103 |
102042 |
939 |
0 |
0 |
T116 |
17708 |
7 |
0 |
0 |
T126 |
16028 |
79 |
0 |
0 |
T127 |
34403 |
368 |
0 |
0 |
T128 |
63814 |
388 |
0 |
0 |
T131 |
9715 |
76 |
0 |
0 |
T138 |
11200 |
48 |
0 |
0 |
T159 |
96521 |
382 |
0 |
0 |
T160 |
102449 |
952 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5618 |
0 |
0 |
T82 |
2082 |
1 |
0 |
0 |
T103 |
102042 |
817 |
0 |
0 |
T126 |
16028 |
23 |
0 |
0 |
T127 |
34403 |
371 |
0 |
0 |
T128 |
63814 |
354 |
0 |
0 |
T131 |
9715 |
26 |
0 |
0 |
T138 |
11200 |
53 |
0 |
0 |
T159 |
96521 |
425 |
0 |
0 |
T160 |
102449 |
875 |
0 |
0 |
T161 |
99347 |
1067 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4834 |
0 |
0 |
T82 |
2082 |
8 |
0 |
0 |
T103 |
102042 |
536 |
0 |
0 |
T126 |
16028 |
64 |
0 |
0 |
T127 |
34403 |
291 |
0 |
0 |
T128 |
63814 |
220 |
0 |
0 |
T131 |
9715 |
2 |
0 |
0 |
T138 |
11200 |
80 |
0 |
0 |
T159 |
96521 |
424 |
0 |
0 |
T160 |
102449 |
854 |
0 |
0 |
T161 |
99347 |
781 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4311 |
0 |
0 |
T103 |
102042 |
769 |
0 |
0 |
T126 |
16028 |
20 |
0 |
0 |
T127 |
34403 |
219 |
0 |
0 |
T128 |
63814 |
343 |
0 |
0 |
T131 |
9715 |
26 |
0 |
0 |
T138 |
11200 |
107 |
0 |
0 |
T159 |
96521 |
404 |
0 |
0 |
T160 |
102449 |
542 |
0 |
0 |
T161 |
99347 |
351 |
0 |
0 |
T162 |
13684 |
76 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5517 |
0 |
0 |
T82 |
2082 |
4 |
0 |
0 |
T103 |
102042 |
968 |
0 |
0 |
T126 |
16028 |
26 |
0 |
0 |
T127 |
34403 |
407 |
0 |
0 |
T128 |
63814 |
297 |
0 |
0 |
T131 |
9715 |
39 |
0 |
0 |
T138 |
11200 |
106 |
0 |
0 |
T159 |
96521 |
482 |
0 |
0 |
T160 |
102449 |
687 |
0 |
0 |
T161 |
99347 |
857 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5287 |
0 |
0 |
T82 |
2082 |
5 |
0 |
0 |
T103 |
102042 |
1117 |
0 |
0 |
T126 |
16028 |
55 |
0 |
0 |
T127 |
34403 |
156 |
0 |
0 |
T128 |
63814 |
221 |
0 |
0 |
T131 |
9715 |
51 |
0 |
0 |
T138 |
11200 |
86 |
0 |
0 |
T159 |
96521 |
405 |
0 |
0 |
T160 |
102449 |
738 |
0 |
0 |
T161 |
99347 |
834 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5137 |
0 |
0 |
T103 |
102042 |
1148 |
0 |
0 |
T126 |
16028 |
91 |
0 |
0 |
T127 |
34403 |
301 |
0 |
0 |
T128 |
63814 |
200 |
0 |
0 |
T131 |
9715 |
72 |
0 |
0 |
T138 |
11200 |
9 |
0 |
0 |
T159 |
96521 |
321 |
0 |
0 |
T160 |
102449 |
696 |
0 |
0 |
T161 |
99347 |
961 |
0 |
0 |
T162 |
13684 |
26 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4613 |
0 |
0 |
T82 |
2082 |
3 |
0 |
0 |
T103 |
102042 |
768 |
0 |
0 |
T126 |
16028 |
64 |
0 |
0 |
T127 |
34403 |
301 |
0 |
0 |
T128 |
63814 |
277 |
0 |
0 |
T131 |
9715 |
21 |
0 |
0 |
T138 |
11200 |
54 |
0 |
0 |
T159 |
96521 |
508 |
0 |
0 |
T160 |
102449 |
638 |
0 |
0 |
T161 |
99347 |
492 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4648 |
0 |
0 |
T82 |
2082 |
2 |
0 |
0 |
T103 |
102042 |
484 |
0 |
0 |
T115 |
21157 |
1 |
0 |
0 |
T126 |
16028 |
107 |
0 |
0 |
T127 |
34403 |
240 |
0 |
0 |
T128 |
63814 |
344 |
0 |
0 |
T131 |
9715 |
30 |
0 |
0 |
T138 |
11200 |
88 |
0 |
0 |
T159 |
96521 |
433 |
0 |
0 |
T160 |
102449 |
701 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5455 |
0 |
0 |
T103 |
102042 |
916 |
0 |
0 |
T116 |
17708 |
8 |
0 |
0 |
T126 |
16028 |
105 |
0 |
0 |
T127 |
34403 |
329 |
0 |
0 |
T128 |
63814 |
272 |
0 |
0 |
T131 |
9715 |
49 |
0 |
0 |
T138 |
11200 |
54 |
0 |
0 |
T159 |
96521 |
474 |
0 |
0 |
T160 |
102449 |
846 |
0 |
0 |
T161 |
99347 |
766 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5273 |
0 |
0 |
T82 |
2082 |
6 |
0 |
0 |
T103 |
102042 |
774 |
0 |
0 |
T126 |
16028 |
135 |
0 |
0 |
T127 |
34403 |
448 |
0 |
0 |
T128 |
63814 |
363 |
0 |
0 |
T131 |
9715 |
81 |
0 |
0 |
T138 |
11200 |
166 |
0 |
0 |
T159 |
96521 |
486 |
0 |
0 |
T160 |
102449 |
713 |
0 |
0 |
T161 |
99347 |
760 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5511 |
0 |
0 |
T82 |
2082 |
7 |
0 |
0 |
T103 |
102042 |
1034 |
0 |
0 |
T126 |
16028 |
167 |
0 |
0 |
T127 |
34403 |
289 |
0 |
0 |
T128 |
63814 |
431 |
0 |
0 |
T131 |
9715 |
42 |
0 |
0 |
T138 |
11200 |
79 |
0 |
0 |
T159 |
96521 |
454 |
0 |
0 |
T160 |
102449 |
810 |
0 |
0 |
T161 |
99347 |
845 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5627 |
0 |
0 |
T103 |
102042 |
1056 |
0 |
0 |
T126 |
16028 |
131 |
0 |
0 |
T127 |
34403 |
405 |
0 |
0 |
T128 |
63814 |
246 |
0 |
0 |
T131 |
9715 |
25 |
0 |
0 |
T138 |
11200 |
79 |
0 |
0 |
T159 |
96521 |
529 |
0 |
0 |
T160 |
102449 |
919 |
0 |
0 |
T161 |
99347 |
913 |
0 |
0 |
T162 |
13684 |
48 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5449 |
0 |
0 |
T103 |
102042 |
1127 |
0 |
0 |
T126 |
16028 |
110 |
0 |
0 |
T127 |
34403 |
277 |
0 |
0 |
T128 |
63814 |
357 |
0 |
0 |
T131 |
9715 |
91 |
0 |
0 |
T138 |
11200 |
11 |
0 |
0 |
T159 |
96521 |
443 |
0 |
0 |
T160 |
102449 |
716 |
0 |
0 |
T161 |
99347 |
735 |
0 |
0 |
T162 |
13684 |
15 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5052 |
0 |
0 |
T82 |
2082 |
4 |
0 |
0 |
T103 |
102042 |
846 |
0 |
0 |
T126 |
16028 |
70 |
0 |
0 |
T127 |
34403 |
211 |
0 |
0 |
T128 |
63814 |
238 |
0 |
0 |
T131 |
9715 |
26 |
0 |
0 |
T138 |
11200 |
72 |
0 |
0 |
T159 |
96521 |
471 |
0 |
0 |
T160 |
102449 |
606 |
0 |
0 |
T161 |
99347 |
940 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5294 |
0 |
0 |
T103 |
102042 |
854 |
0 |
0 |
T126 |
16028 |
70 |
0 |
0 |
T127 |
34403 |
335 |
0 |
0 |
T128 |
63814 |
237 |
0 |
0 |
T131 |
9715 |
53 |
0 |
0 |
T138 |
11200 |
130 |
0 |
0 |
T159 |
96521 |
413 |
0 |
0 |
T160 |
102449 |
820 |
0 |
0 |
T161 |
99347 |
716 |
0 |
0 |
T162 |
13684 |
45 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4903 |
0 |
0 |
T82 |
2082 |
7 |
0 |
0 |
T103 |
102042 |
585 |
0 |
0 |
T115 |
21157 |
6 |
0 |
0 |
T126 |
16028 |
77 |
0 |
0 |
T127 |
34403 |
291 |
0 |
0 |
T128 |
63814 |
249 |
0 |
0 |
T131 |
9715 |
77 |
0 |
0 |
T138 |
11200 |
50 |
0 |
0 |
T159 |
96521 |
471 |
0 |
0 |
T160 |
102449 |
804 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
5339 |
0 |
0 |
T82 |
2082 |
5 |
0 |
0 |
T103 |
102042 |
848 |
0 |
0 |
T126 |
16028 |
151 |
0 |
0 |
T127 |
34403 |
238 |
0 |
0 |
T128 |
63814 |
329 |
0 |
0 |
T131 |
9715 |
18 |
0 |
0 |
T138 |
11200 |
98 |
0 |
0 |
T159 |
96521 |
490 |
0 |
0 |
T160 |
102449 |
866 |
0 |
0 |
T161 |
99347 |
813 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1637 |
0 |
0 |
T103 |
102042 |
148 |
0 |
0 |
T126 |
16028 |
7 |
0 |
0 |
T127 |
34403 |
65 |
0 |
0 |
T128 |
63814 |
65 |
0 |
0 |
T131 |
9715 |
13 |
0 |
0 |
T138 |
11200 |
13 |
0 |
0 |
T159 |
96521 |
69 |
0 |
0 |
T160 |
102449 |
142 |
0 |
0 |
T161 |
99347 |
185 |
0 |
0 |
T162 |
13684 |
6 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1722 |
0 |
0 |
T103 |
102042 |
168 |
0 |
0 |
T115 |
21157 |
4 |
0 |
0 |
T126 |
16028 |
29 |
0 |
0 |
T127 |
34403 |
66 |
0 |
0 |
T128 |
63814 |
47 |
0 |
0 |
T131 |
9715 |
8 |
0 |
0 |
T138 |
11200 |
19 |
0 |
0 |
T159 |
96521 |
114 |
0 |
0 |
T160 |
102449 |
183 |
0 |
0 |
T161 |
99347 |
199 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1624 |
0 |
0 |
T82 |
2082 |
3 |
0 |
0 |
T103 |
102042 |
176 |
0 |
0 |
T126 |
16028 |
43 |
0 |
0 |
T127 |
34403 |
46 |
0 |
0 |
T128 |
63814 |
86 |
0 |
0 |
T131 |
9715 |
16 |
0 |
0 |
T138 |
11200 |
11 |
0 |
0 |
T159 |
96521 |
74 |
0 |
0 |
T160 |
102449 |
149 |
0 |
0 |
T161 |
99347 |
168 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1720 |
0 |
0 |
T103 |
102042 |
174 |
0 |
0 |
T126 |
16028 |
16 |
0 |
0 |
T127 |
34403 |
67 |
0 |
0 |
T128 |
63814 |
45 |
0 |
0 |
T131 |
9715 |
5 |
0 |
0 |
T138 |
11200 |
10 |
0 |
0 |
T159 |
96521 |
82 |
0 |
0 |
T160 |
102449 |
190 |
0 |
0 |
T161 |
99347 |
192 |
0 |
0 |
T162 |
13684 |
11 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
2359 |
0 |
0 |
T82 |
2082 |
2 |
0 |
0 |
T103 |
102042 |
323 |
0 |
0 |
T126 |
16028 |
60 |
0 |
0 |
T127 |
34403 |
116 |
0 |
0 |
T128 |
63814 |
113 |
0 |
0 |
T131 |
9715 |
3 |
0 |
0 |
T138 |
11200 |
25 |
0 |
0 |
T159 |
96521 |
140 |
0 |
0 |
T160 |
102449 |
263 |
0 |
0 |
T161 |
99347 |
283 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
4533 |
0 |
0 |
T16 |
243980 |
21 |
0 |
0 |
T36 |
0 |
40 |
0 |
0 |
T67 |
835230 |
0 |
0 |
0 |
T154 |
99310 |
0 |
0 |
0 |
T163 |
0 |
14 |
0 |
0 |
T164 |
0 |
19 |
0 |
0 |
T165 |
0 |
40 |
0 |
0 |
T166 |
0 |
55 |
0 |
0 |
T167 |
0 |
51 |
0 |
0 |
T168 |
0 |
5 |
0 |
0 |
T169 |
0 |
2 |
0 |
0 |
T170 |
0 |
56 |
0 |
0 |
T171 |
636143 |
0 |
0 |
0 |
T172 |
9823 |
0 |
0 |
0 |
T173 |
1614 |
0 |
0 |
0 |
T174 |
231367 |
0 |
0 |
0 |
T175 |
10371 |
0 |
0 |
0 |
T176 |
2924 |
0 |
0 |
0 |
T177 |
77052 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1696 |
0 |
0 |
T103 |
102042 |
181 |
0 |
0 |
T126 |
16028 |
19 |
0 |
0 |
T127 |
34403 |
74 |
0 |
0 |
T128 |
63814 |
28 |
0 |
0 |
T138 |
11200 |
17 |
0 |
0 |
T159 |
96521 |
66 |
0 |
0 |
T160 |
102449 |
163 |
0 |
0 |
T161 |
99347 |
155 |
0 |
0 |
T162 |
13684 |
13 |
0 |
0 |
T178 |
12707 |
36 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1748 |
0 |
0 |
T103 |
102042 |
182 |
0 |
0 |
T116 |
17708 |
7 |
0 |
0 |
T126 |
16028 |
39 |
0 |
0 |
T127 |
34403 |
64 |
0 |
0 |
T128 |
63814 |
69 |
0 |
0 |
T131 |
9715 |
2 |
0 |
0 |
T138 |
11200 |
14 |
0 |
0 |
T159 |
96521 |
97 |
0 |
0 |
T160 |
102449 |
177 |
0 |
0 |
T161 |
99347 |
188 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1470 |
0 |
0 |
T103 |
102042 |
138 |
0 |
0 |
T126 |
16028 |
22 |
0 |
0 |
T127 |
34403 |
48 |
0 |
0 |
T128 |
63814 |
37 |
0 |
0 |
T131 |
9715 |
9 |
0 |
0 |
T138 |
11200 |
8 |
0 |
0 |
T159 |
96521 |
79 |
0 |
0 |
T160 |
102449 |
122 |
0 |
0 |
T161 |
99347 |
103 |
0 |
0 |
T162 |
13684 |
9 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1510 |
0 |
0 |
T82 |
2082 |
4 |
0 |
0 |
T103 |
102042 |
107 |
0 |
0 |
T126 |
16028 |
19 |
0 |
0 |
T127 |
34403 |
45 |
0 |
0 |
T128 |
63814 |
49 |
0 |
0 |
T131 |
9715 |
1 |
0 |
0 |
T138 |
11200 |
11 |
0 |
0 |
T159 |
96521 |
77 |
0 |
0 |
T160 |
102449 |
135 |
0 |
0 |
T161 |
99347 |
115 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1321 |
0 |
0 |
T82 |
2082 |
5 |
0 |
0 |
T103 |
102042 |
84 |
0 |
0 |
T112 |
16802 |
1 |
0 |
0 |
T126 |
16028 |
12 |
0 |
0 |
T127 |
34403 |
46 |
0 |
0 |
T128 |
63814 |
44 |
0 |
0 |
T131 |
9715 |
6 |
0 |
0 |
T138 |
11200 |
8 |
0 |
0 |
T159 |
96521 |
50 |
0 |
0 |
T160 |
102449 |
99 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1367 |
0 |
0 |
T103 |
102042 |
90 |
0 |
0 |
T126 |
16028 |
22 |
0 |
0 |
T127 |
34403 |
35 |
0 |
0 |
T128 |
63814 |
51 |
0 |
0 |
T131 |
9715 |
8 |
0 |
0 |
T138 |
11200 |
9 |
0 |
0 |
T159 |
96521 |
68 |
0 |
0 |
T160 |
102449 |
74 |
0 |
0 |
T161 |
99347 |
109 |
0 |
0 |
T162 |
13684 |
9 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
2278 |
0 |
0 |
T103 |
102042 |
298 |
0 |
0 |
T126 |
16028 |
46 |
0 |
0 |
T127 |
34403 |
78 |
0 |
0 |
T128 |
63814 |
113 |
0 |
0 |
T131 |
9715 |
9 |
0 |
0 |
T138 |
11200 |
37 |
0 |
0 |
T159 |
96521 |
175 |
0 |
0 |
T160 |
102449 |
223 |
0 |
0 |
T161 |
99347 |
258 |
0 |
0 |
T162 |
13684 |
31 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1425 |
0 |
0 |
T103 |
102042 |
114 |
0 |
0 |
T111 |
11528 |
2 |
0 |
0 |
T126 |
16028 |
20 |
0 |
0 |
T127 |
34403 |
58 |
0 |
0 |
T128 |
63814 |
50 |
0 |
0 |
T131 |
9715 |
4 |
0 |
0 |
T138 |
11200 |
17 |
0 |
0 |
T159 |
96521 |
71 |
0 |
0 |
T160 |
102449 |
127 |
0 |
0 |
T161 |
99347 |
117 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
2641 |
0 |
0 |
T82 |
2082 |
1 |
0 |
0 |
T103 |
102042 |
303 |
0 |
0 |
T126 |
16028 |
23 |
0 |
0 |
T127 |
34403 |
150 |
0 |
0 |
T128 |
63814 |
107 |
0 |
0 |
T131 |
9715 |
59 |
0 |
0 |
T138 |
11200 |
22 |
0 |
0 |
T159 |
96521 |
222 |
0 |
0 |
T160 |
102449 |
309 |
0 |
0 |
T161 |
99347 |
376 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1890 |
0 |
0 |
T82 |
2082 |
2 |
0 |
0 |
T103 |
102042 |
210 |
0 |
0 |
T116 |
17708 |
2 |
0 |
0 |
T126 |
16028 |
30 |
0 |
0 |
T127 |
34403 |
78 |
0 |
0 |
T128 |
63814 |
72 |
0 |
0 |
T131 |
9715 |
9 |
0 |
0 |
T138 |
11200 |
22 |
0 |
0 |
T159 |
96521 |
106 |
0 |
0 |
T160 |
102449 |
170 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1426 |
0 |
0 |
T82 |
2082 |
1 |
0 |
0 |
T103 |
102042 |
120 |
0 |
0 |
T126 |
16028 |
16 |
0 |
0 |
T127 |
34403 |
37 |
0 |
0 |
T128 |
63814 |
49 |
0 |
0 |
T131 |
9715 |
10 |
0 |
0 |
T138 |
11200 |
14 |
0 |
0 |
T159 |
96521 |
78 |
0 |
0 |
T160 |
102449 |
104 |
0 |
0 |
T161 |
99347 |
99 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1408 |
0 |
0 |
T103 |
102042 |
123 |
0 |
0 |
T126 |
16028 |
23 |
0 |
0 |
T127 |
34403 |
25 |
0 |
0 |
T128 |
63814 |
39 |
0 |
0 |
T131 |
9715 |
4 |
0 |
0 |
T138 |
11200 |
13 |
0 |
0 |
T159 |
96521 |
91 |
0 |
0 |
T160 |
102449 |
105 |
0 |
0 |
T161 |
99347 |
96 |
0 |
0 |
T162 |
13684 |
17 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1362 |
0 |
0 |
T103 |
102042 |
102 |
0 |
0 |
T126 |
16028 |
23 |
0 |
0 |
T127 |
34403 |
43 |
0 |
0 |
T128 |
63814 |
35 |
0 |
0 |
T131 |
9715 |
9 |
0 |
0 |
T138 |
11200 |
4 |
0 |
0 |
T159 |
96521 |
85 |
0 |
0 |
T160 |
102449 |
124 |
0 |
0 |
T161 |
99347 |
120 |
0 |
0 |
T162 |
13684 |
10 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1324 |
0 |
0 |
T103 |
102042 |
112 |
0 |
0 |
T126 |
16028 |
29 |
0 |
0 |
T127 |
34403 |
40 |
0 |
0 |
T128 |
63814 |
47 |
0 |
0 |
T131 |
9715 |
12 |
0 |
0 |
T138 |
11200 |
25 |
0 |
0 |
T159 |
96521 |
53 |
0 |
0 |
T160 |
102449 |
101 |
0 |
0 |
T161 |
99347 |
104 |
0 |
0 |
T162 |
13684 |
9 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1465 |
0 |
0 |
T103 |
102042 |
105 |
0 |
0 |
T111 |
11528 |
4 |
0 |
0 |
T116 |
17708 |
7 |
0 |
0 |
T126 |
16028 |
37 |
0 |
0 |
T127 |
34403 |
51 |
0 |
0 |
T128 |
63814 |
25 |
0 |
0 |
T131 |
9715 |
7 |
0 |
0 |
T138 |
11200 |
11 |
0 |
0 |
T159 |
96521 |
56 |
0 |
0 |
T160 |
102449 |
123 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
454754723 |
1379 |
0 |
0 |
T103 |
102042 |
96 |
0 |
0 |
T126 |
16028 |
30 |
0 |
0 |
T127 |
34403 |
43 |
0 |
0 |
T128 |
63814 |
38 |
0 |
0 |
T138 |
11200 |
14 |
0 |
0 |
T159 |
96521 |
77 |
0 |
0 |
T160 |
102449 |
85 |
0 |
0 |
T161 |
99347 |
116 |
0 |
0 |
T162 |
13684 |
13 |
0 |
0 |
T178 |
12707 |
26 |
0 |
0 |