Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3386069	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4225142

1

T1

851

T2

110

T3

2066

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4103222	1			T1	2091		T2	101		T3	2384
values[0x0]	1753907	1			T1	414		T2	47		T3	458
values[0x1]	1754082	1			T1	421		T2	53		T3	439

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2406249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5204962

1

T1

1479

T2

163

T3

2313

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28104	1			T1	5		T3	14		T4	1
valid_sources[0x01]	29307	1			T2	13		T3	14		T4	3
valid_sources[0x02]	27610	1			T1	17		T3	23		T4	2
valid_sources[0x03]	26826	1			T1	10		T3	6		T4	8
valid_sources[0x04]	29062	1			T1	6		T3	7		T4	4
valid_sources[0x05]	28922	1			T3	16		T4	3		T6	2
valid_sources[0x06]	26699	1			T1	88		T3	24		T4	5
valid_sources[0x07]	29763	1			T1	28		T3	19		T4	3
valid_sources[0x08]	29907	1			T1	14		T3	7		T6	3
valid_sources[0x09]	27887	1			T3	18		T4	2		T8	6
valid_sources[0x0a]	28561	1			T1	11		T3	22		T4	6
valid_sources[0x0b]	27184	1			T3	21		T4	1		T8	3
valid_sources[0x0c]	28746	1			T3	5		T4	3		T5	1
valid_sources[0x0d]	30221	1			T1	5		T3	19		T4	4
valid_sources[0x0e]	29008	1			T1	4		T3	14		T4	4
valid_sources[0x0f]	28873	1			T3	13		T4	5		T9	7
valid_sources[0x10]	28095	1			T1	4		T3	15		T4	12
valid_sources[0x11]	31410	1			T2	4		T3	16		T6	8
valid_sources[0x12]	31747	1			T1	18		T3	8		T4	5
valid_sources[0x13]	27443	1			T1	12		T3	13		T4	3
valid_sources[0x14]	29509	1			T1	32		T3	8		T4	2
valid_sources[0x15]	28601	1			T3	7		T4	7		T6	1
valid_sources[0x16]	29030	1			T1	36		T3	11		T4	6
valid_sources[0x17]	35889	1			T1	1		T3	6		T4	7
valid_sources[0x18]	27904	1			T3	18		T4	3		T5	1
valid_sources[0x19]	30870	1			T1	32		T3	9		T4	1
valid_sources[0x1a]	26857	1			T1	10		T3	16		T4	1
valid_sources[0x1b]	30910	1			T1	30		T3	15		T4	3
valid_sources[0x1c]	48393	1			T1	25		T3	17		T4	2
valid_sources[0x1d]	26673	1			T1	23		T3	12		T4	4
valid_sources[0x1e]	27944	1			T3	16		T4	4		T8	5
valid_sources[0x1f]	37440	1			T3	8		T6	2		T8	7
valid_sources[0x20]	28061	1			T1	18		T3	8		T6	3
valid_sources[0x21]	29471	1			T1	30		T3	12		T4	7
valid_sources[0x22]	26867	1			T1	5		T3	9		T4	1
valid_sources[0x23]	28891	1			T3	3		T4	4		T6	3
valid_sources[0x24]	26335	1			T1	2		T3	6		T4	4
valid_sources[0x25]	28725	1			T1	15		T3	10		T4	3
valid_sources[0x26]	27254	1			T1	6		T3	15		T8	6
valid_sources[0x27]	32980	1			T1	3		T3	7		T4	3
valid_sources[0x28]	32952	1			T1	9		T3	16		T8	4
valid_sources[0x29]	29537	1			T1	1		T3	9		T4	8
valid_sources[0x2a]	31960	1			T3	17		T4	9		T9	13
valid_sources[0x2b]	30445	1			T1	39		T3	19		T4	7
valid_sources[0x2c]	32549	1			T1	13		T3	18		T4	1
valid_sources[0x2d]	38208	1			T1	11		T3	13		T4	3
valid_sources[0x2e]	29184	1			T3	13		T4	7		T8	3
valid_sources[0x2f]	30468	1			T1	8		T3	13		T4	1
valid_sources[0x30]	26991	1			T1	46		T3	15		T4	1
valid_sources[0x31]	27246	1			T3	12		T4	3		T6	5
valid_sources[0x32]	27103	1			T1	7		T3	12		T9	7
valid_sources[0x33]	29311	1			T1	11		T3	9		T4	2
valid_sources[0x34]	32189	1			T1	28		T3	13		T4	4
valid_sources[0x35]	34286	1			T1	31		T3	12		T4	9
valid_sources[0x36]	27368	1			T3	18		T4	2		T6	2
valid_sources[0x37]	29981	1			T3	15		T4	5		T8	2
valid_sources[0x38]	31089	1			T3	18		T4	1		T8	1
valid_sources[0x39]	29343	1			T3	14		T4	2		T8	2
valid_sources[0x3a]	28641	1			T3	20		T4	1		T8	1
valid_sources[0x3b]	29639	1			T3	13		T4	8		T5	1
valid_sources[0x3c]	30234	1			T1	14		T3	15		T4	7
valid_sources[0x3d]	29100	1			T1	39		T3	12		T4	4
valid_sources[0x3e]	27404	1			T1	8		T2	1		T3	7
valid_sources[0x3f]	28556	1			T3	7		T4	1		T8	1
valid_sources[0x40]	30175	1			T1	35		T2	4		T3	15
valid_sources[0x41]	28689	1			T1	38		T3	10		T4	3
valid_sources[0x42]	28603	1			T3	12		T6	1		T8	2
valid_sources[0x43]	27370	1			T1	14		T3	6		T4	1
valid_sources[0x44]	28268	1			T1	26		T3	17		T4	6
valid_sources[0x45]	26985	1			T1	46		T3	13		T6	1
valid_sources[0x46]	32942	1			T1	12		T2	5		T3	8
valid_sources[0x47]	29041	1			T3	13		T4	4		T8	2
valid_sources[0x48]	26119	1			T3	19		T4	5		T5	1
valid_sources[0x49]	29661	1			T2	1		T3	18		T4	2
valid_sources[0x4a]	29856	1			T1	15		T2	2		T3	3
valid_sources[0x4b]	27897	1			T3	11		T4	1		T5	1
valid_sources[0x4c]	29924	1			T1	19		T3	10		T4	1
valid_sources[0x4d]	30595	1			T1	16		T3	12		T4	3
valid_sources[0x4e]	28540	1			T1	8		T3	13		T4	1
valid_sources[0x4f]	28264	1			T1	9		T3	7		T4	1
valid_sources[0x50]	28524	1			T1	5		T3	7		T4	3
valid_sources[0x51]	28840	1			T1	5		T3	17		T4	2
valid_sources[0x52]	34270	1			T1	35		T2	14		T3	17
valid_sources[0x53]	27123	1			T1	11		T3	14		T4	4
valid_sources[0x54]	29420	1			T1	8		T3	10		T4	5
valid_sources[0x55]	30975	1			T3	15		T4	7		T8	3
valid_sources[0x56]	25962	1			T1	6		T3	9		T4	4
valid_sources[0x57]	31449	1			T1	23		T3	16		T4	3
valid_sources[0x58]	27218	1			T3	18		T5	1		T6	2
valid_sources[0x59]	31959	1			T1	22		T2	13		T3	11
valid_sources[0x5a]	27680	1			T1	19		T3	30		T4	12
valid_sources[0x5b]	32128	1			T1	11		T3	6		T4	5
valid_sources[0x5c]	28876	1			T2	3		T3	14		T4	3
valid_sources[0x5d]	31315	1			T1	3		T2	1		T3	16
valid_sources[0x5e]	27767	1			T3	8		T4	3		T6	4
valid_sources[0x5f]	27554	1			T1	13		T3	8		T4	3
valid_sources[0x60]	28756	1			T3	4		T4	1		T5	1
valid_sources[0x61]	41849	1			T1	12		T3	10		T4	2
valid_sources[0x62]	29910	1			T1	7		T3	13		T4	2
valid_sources[0x63]	30935	1			T1	8		T3	7		T8	5
valid_sources[0x64]	29143	1			T3	12		T4	7		T8	2
valid_sources[0x65]	28257	1			T3	10		T4	5		T6	2
valid_sources[0x66]	29396	1			T1	21		T3	14		T5	318
valid_sources[0x67]	28199	1			T1	14		T2	2		T3	9
valid_sources[0x68]	30570	1			T1	11		T3	28		T4	3
valid_sources[0x69]	28695	1			T1	22		T3	11		T4	8
valid_sources[0x6a]	29047	1			T1	3		T3	8		T4	9
valid_sources[0x6b]	28940	1			T1	23		T2	5		T3	5
valid_sources[0x6c]	31084	1			T1	15		T3	25		T4	4
valid_sources[0x6d]	28287	1			T1	11		T3	6		T4	3
valid_sources[0x6e]	28217	1			T1	4		T3	2		T4	5
valid_sources[0x6f]	26647	1			T3	4		T4	7		T8	9
valid_sources[0x70]	32127	1			T1	3		T3	9		T4	2
valid_sources[0x71]	27779	1			T3	16		T4	6		T5	416
valid_sources[0x72]	27135	1			T1	4		T3	17		T4	1
valid_sources[0x73]	27469	1			T1	17		T2	10		T3	7
valid_sources[0x74]	29503	1			T1	5		T3	13		T4	1
valid_sources[0x75]	27304	1			T1	29		T3	13		T4	1
valid_sources[0x76]	33555	1			T3	9		T4	2		T8	2
valid_sources[0x77]	26507	1			T3	8		T4	6		T8	6
valid_sources[0x78]	26652	1			T3	21		T4	10		T5	2
valid_sources[0x79]	26967	1			T3	14		T4	3		T8	6
valid_sources[0x7a]	33764	1			T3	23		T4	6		T6	3
valid_sources[0x7b]	30030	1			T3	7		T4	4		T8	3
valid_sources[0x7c]	29795	1			T1	22		T3	7		T4	3
valid_sources[0x7d]	29137	1			T3	4		T4	6		T6	1
valid_sources[0x7e]	31406	1			T3	22		T4	9		T6	3
valid_sources[0x7f]	28418	1			T1	12		T3	12		T4	1
valid_sources[0x80]	30345	1			T3	7		T4	1		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1031074

1

T1

226

T2

10

T3

1175

values[0x0]

all_enables

biggest_size

1608742

1

T1

329

T2

47

T3

457

values[0x1]

all_enables

biggest_size

1585326

1

T1

296

T2

53

T3

434