Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3409913

1

T1

2075

T3

1215

T4

25

full_word

4224445

1

T1

851

T3

2066

T4

898

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7633998	1			T1	2926		T3	3281		T4	923
auto[TlIntgErrCmd]	125	1			T98	10		T99	13		T100	3
auto[TlIntgErrData]	119	1			T98	4		T99	3		T100	3
auto[TlIntgErrBoth]	116	1			T98	6		T99	4		T100	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4106740

1

T1

2091

T3

2384

T4

38

auto[1]

3527618

1

T1

835

T3

897

T4

885

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3075331	1			T1	1865		T3	1209		T4	20
auto[TlIntgErrNone]	partial	auto[1]	334259	1			T1	210		T3	6		T4	5
auto[TlIntgErrNone]	full_word	auto[0]	1031242	1			T1	226		T3	1175		T4	18
auto[TlIntgErrNone]	full_word	auto[1]	3193166	1			T1	625		T3	891		T4	880
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T98	6		T99	3		T100	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T98	3		T99	8		T100	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T98	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T99	2		T188	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T98	3		T100	3		T101	6
auto[TlIntgErrData]	partial	auto[1]	50	1			T99	2		T101	2		T117	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T99	1		T117	1		T188	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T98	1		T101	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T98	4		T99	4		T100	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T98	1		T100	2		T101	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T101	2		T190	1		T191	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T98	1		T101	1		T117	1