Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Unreachable
1	1	Covered	T1,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	722133768	574698929	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	722133768	3673938	0	0
GntImpliesValid_A	722133768	3673938	0	0
GrantKnown_A	722133768	574698929	0	0
IdxKnown_A	722133768	574698929	0	0
IndexIsCorrect_A	722133768	3673938	0	0
LockArbDecision_A	722133768	0	0	0
NoReadyValidNoGrant_A	722133768	0	0	0
ReadyAndValidImplyGrant_A	722133768	3673938	0	0
ReqAndReadyImplyGrant_A	722133768	3673938	0	0
ReqImpliesValid_A	722133768	3673938	0	0
ReqStaysHighUntilGranted0_M	722133768	0	0	0
RoundRobin_A	722133768	2	0	976
ValidKnown_A	722133768	574698929	0	0
gen_data_port_assertion.DataFlow_A	722133768	3673938	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	574698929	0	0
T1	174970	174318	0	0
T2	2226	2163	0	0
T3	61954	53502	0	0
T4	16615	14195	0	0
T5	454832	284568	0	0
T6	343236	308389	0	0
T7	1098	1014	0	0
T8	738304	664375	0	0
T9	484950	278817	0	0
T10	13352	11772	0	0
T11	233708	114635	0	0
T12	95776	47888	0	0
T13	567963	560215	0	0
T14	0	692542	0	0
T15	0	605939	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	3673938	0	0
T1	174970	1620	0	0
T2	2226	200	0	0
T3	53602	832	0	0
T4	16615	844	0	0
T5	454832	5712	0	0
T6	343236	0	0	0
T7	1098	0	0	0
T8	738304	832	0	0
T9	484950	2797	0	0
T10	13352	143	0	0
T11	233708	4231	0	0
T12	95776	832	0	0
T13	567963	9698	0	0
T14	695694	8302	0	0
T15	0	7566	0	0
T16	0	3584	0	0
T17	0	26739	0	0
T18	0	3087	0	0
T26	0	2854	0	0
T28	0	2220	0	0
T29	0	3445	0	0
T52	0	2534	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	3673938	0	0
T1	174970	1620	0	0
T2	2226	200	0	0
T3	53602	832	0	0
T4	16615	844	0	0
T5	454832	5712	0	0
T6	343236	0	0	0
T7	1098	0	0	0
T8	738304	832	0	0
T9	484950	2797	0	0
T10	13352	143	0	0
T11	233708	4231	0	0
T12	95776	832	0	0
T13	567963	9698	0	0
T14	695694	8302	0	0
T15	0	7566	0	0
T16	0	3584	0	0
T17	0	26739	0	0
T18	0	3087	0	0
T26	0	2854	0	0
T28	0	2220	0	0
T29	0	3445	0	0
T52	0	2534	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	574698929	0	0
T1	174970	174318	0	0
T2	2226	2163	0	0
T3	61954	53502	0	0
T4	16615	14195	0	0
T5	454832	284568	0	0
T6	343236	308389	0	0
T7	1098	1014	0	0
T8	738304	664375	0	0
T9	484950	278817	0	0
T10	13352	11772	0	0
T11	233708	114635	0	0
T12	95776	47888	0	0
T13	567963	560215	0	0
T14	0	692542	0	0
T15	0	605939	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	574698929	0	0
T1	174970	174318	0	0
T2	2226	2163	0	0
T3	61954	53502	0	0
T4	16615	14195	0	0
T5	454832	284568	0	0
T6	343236	308389	0	0
T7	1098	1014	0	0
T8	738304	664375	0	0
T9	484950	278817	0	0
T10	13352	11772	0	0
T11	233708	114635	0	0
T12	95776	47888	0	0
T13	567963	560215	0	0
T14	0	692542	0	0
T15	0	605939	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	3673938	0	0
T1	174970	1620	0	0
T2	2226	200	0	0
T3	53602	832	0	0
T4	16615	844	0	0
T5	454832	5712	0	0
T6	343236	0	0	0
T7	1098	0	0	0
T8	738304	832	0	0
T9	484950	2797	0	0
T10	13352	143	0	0
T11	233708	4231	0	0
T12	95776	832	0	0
T13	567963	9698	0	0
T14	695694	8302	0	0
T15	0	7566	0	0
T16	0	3584	0	0
T17	0	26739	0	0
T18	0	3087	0	0
T26	0	2854	0	0
T28	0	2220	0	0
T29	0	3445	0	0
T52	0	2534	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	3673938	0	0
T1	174970	1620	0	0
T2	2226	200	0	0
T3	53602	832	0	0
T4	16615	844	0	0
T5	454832	5712	0	0
T6	343236	0	0	0
T7	1098	0	0	0
T8	738304	832	0	0
T9	484950	2797	0	0
T10	13352	143	0	0
T11	233708	4231	0	0
T12	95776	832	0	0
T13	567963	9698	0	0
T14	695694	8302	0	0
T15	0	7566	0	0
T16	0	3584	0	0
T17	0	26739	0	0
T18	0	3087	0	0
T26	0	2854	0	0
T28	0	2220	0	0
T29	0	3445	0	0
T52	0	2534	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	3673938	0	0
T1	174970	1620	0	0
T2	2226	200	0	0
T3	53602	832	0	0
T4	16615	844	0	0
T5	454832	5712	0	0
T6	343236	0	0	0
T7	1098	0	0	0
T8	738304	832	0	0
T9	484950	2797	0	0
T10	13352	143	0	0
T11	233708	4231	0	0
T12	95776	832	0	0
T13	567963	9698	0	0
T14	695694	8302	0	0
T15	0	7566	0	0
T16	0	3584	0	0
T17	0	26739	0	0
T18	0	3087	0	0
T26	0	2854	0	0
T28	0	2220	0	0
T29	0	3445	0	0
T52	0	2534	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	3673938	0	0
T1	174970	1620	0	0
T2	2226	200	0	0
T3	53602	832	0	0
T4	16615	844	0	0
T5	454832	5712	0	0
T6	343236	0	0	0
T7	1098	0	0	0
T8	738304	832	0	0
T9	484950	2797	0	0
T10	13352	143	0	0
T11	233708	4231	0	0
T12	95776	832	0	0
T13	567963	9698	0	0
T14	695694	8302	0	0
T15	0	7566	0	0
T16	0	3584	0	0
T17	0	26739	0	0
T18	0	3087	0	0
T26	0	2854	0	0
T28	0	2220	0	0
T29	0	3445	0	0
T52	0	2534	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	2	0	976
T53	714239	1	0	1
T54	0	1	0	0
T55	746276	0	0	1
T56	1093	0	0	1
T57	142073	0	0	1
T58	317812	0	0	1
T59	387025	0	0	1
T60	5259	0	0	1
T61	3266	0	0	1
T62	59715	0	0	1
T63	5885	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	574698929	0	0
T1	174970	174318	0	0
T2	2226	2163	0	0
T3	61954	53502	0	0
T4	16615	14195	0	0
T5	454832	284568	0	0
T6	343236	308389	0	0
T7	1098	1014	0	0
T8	738304	664375	0	0
T9	484950	278817	0	0
T10	13352	11772	0	0
T11	233708	114635	0	0
T12	95776	47888	0	0
T13	567963	560215	0	0
T14	0	692542	0	0
T15	0	605939	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	722133768	3673938	0	0
T1	174970	1620	0	0
T2	2226	200	0	0
T3	53602	832	0	0
T4	16615	844	0	0
T5	454832	5712	0	0
T6	343236	0	0	0
T7	1098	0	0	0
T8	738304	832	0	0
T9	484950	2797	0	0
T10	13352	143	0	0
T11	233708	4231	0	0
T12	95776	832	0	0
T13	567963	9698	0	0
T14	695694	8302	0	0
T15	0	7566	0	0
T16	0	3584	0	0
T17	0	26739	0	0
T18	0	3087	0	0
T26	0	2854	0	0
T28	0	2220	0	0
T29	0	3445	0	0
T52	0	2534	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Unreachable
1	1	Covered	T1,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T10,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145971906	27887823	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	145971906	598730	0	0
GntImpliesValid_A	145971906	598730	0	0
GrantKnown_A	145971906	27887823	0	0
IdxKnown_A	145971906	27887823	0	0
IndexIsCorrect_A	145971906	598730	0	0
LockArbDecision_A	145971906	0	0	0
NoReadyValidNoGrant_A	145971906	0	0	0
ReadyAndValidImplyGrant_A	145971906	598730	0	0
ReqAndReadyImplyGrant_A	145971906	598730	0	0
ReqImpliesValid_A	145971906	598730	0	0
ReqStaysHighUntilGranted0_M	145971906	0	0	0
RoundRobin_A	145971906	0	0	0
ValidKnown_A	145971906	27887823	0	0
gen_data_port_assertion.DataFlow_A	145971906	598730	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	27887823	0	0
T1	28838	28272	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	33168	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	1480	0	0
T11	116854	114632	0	0
T12	47888	0	0	0
T13	0	103096	0	0
T14	0	35376	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	598730	0	0
T1	28838	1083	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	105	0	0
T11	116854	2814	0	0
T12	47888	0	0	0
T13	0	5178	0	0
T14	0	1071	0	0
T16	0	2999	0	0
T17	0	12641	0	0
T18	0	3087	0	0
T29	0	3445	0	0
T52	0	2534	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	598730	0	0
T1	28838	1083	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	105	0	0
T11	116854	2814	0	0
T12	47888	0	0	0
T13	0	5178	0	0
T14	0	1071	0	0
T16	0	2999	0	0
T17	0	12641	0	0
T18	0	3087	0	0
T29	0	3445	0	0
T52	0	2534	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	27887823	0	0
T1	28838	28272	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	33168	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	1480	0	0
T11	116854	114632	0	0
T12	47888	0	0	0
T13	0	103096	0	0
T14	0	35376	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	27887823	0	0
T1	28838	28272	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	33168	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	1480	0	0
T11	116854	114632	0	0
T12	47888	0	0	0
T13	0	103096	0	0
T14	0	35376	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	598730	0	0
T1	28838	1083	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	105	0	0
T11	116854	2814	0	0
T12	47888	0	0	0
T13	0	5178	0	0
T14	0	1071	0	0
T16	0	2999	0	0
T17	0	12641	0	0
T18	0	3087	0	0
T29	0	3445	0	0
T52	0	2534	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	598730	0	0
T1	28838	1083	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	105	0	0
T11	116854	2814	0	0
T12	47888	0	0	0
T13	0	5178	0	0
T14	0	1071	0	0
T16	0	2999	0	0
T17	0	12641	0	0
T18	0	3087	0	0
T29	0	3445	0	0
T52	0	2534	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	598730	0	0
T1	28838	1083	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	105	0	0
T11	116854	2814	0	0
T12	47888	0	0	0
T13	0	5178	0	0
T14	0	1071	0	0
T16	0	2999	0	0
T17	0	12641	0	0
T18	0	3087	0	0
T29	0	3445	0	0
T52	0	2534	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	598730	0	0
T1	28838	1083	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	105	0	0
T11	116854	2814	0	0
T12	47888	0	0	0
T13	0	5178	0	0
T14	0	1071	0	0
T16	0	2999	0	0
T17	0	12641	0	0
T18	0	3087	0	0
T29	0	3445	0	0
T52	0	2534	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	27887823	0	0
T1	28838	28272	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	33168	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	1480	0	0
T11	116854	114632	0	0
T12	47888	0	0	0
T13	0	103096	0	0
T14	0	35376	0	0
T16	0	261472	0	0
T17	0	352112	0	0
T18	0	203080	0	0
T29	0	176368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	598730	0	0
T1	28838	1083	0	0
T3	8352	0	0	0
T4	2320	0	0	0
T5	167612	0	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	0	0	0
T10	1480	105	0	0
T11	116854	2814	0	0
T12	47888	0	0	0
T13	0	5178	0	0
T14	0	1071	0	0
T16	0	2999	0	0
T17	0	12641	0	0
T18	0	3087	0	0
T29	0	3445	0	0
T52	0	2534	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T9
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145971906	116712474	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	145971906	774474	0	0
GntImpliesValid_A	145971906	774474	0	0
GrantKnown_A	145971906	116712474	0	0
IdxKnown_A	145971906	116712474	0	0
IndexIsCorrect_A	145971906	774474	0	0
LockArbDecision_A	145971906	0	0	0
NoReadyValidNoGrant_A	145971906	0	0	0
ReadyAndValidImplyGrant_A	145971906	774474	0	0
ReqAndReadyImplyGrant_A	145971906	774474	0	0
ReqImpliesValid_A	145971906	774474	0	0
ReqStaysHighUntilGranted0_M	145971906	0	0	0
RoundRobin_A	145971906	0	0	0
ValidKnown_A	145971906	116712474	0	0
gen_data_port_assertion.DataFlow_A	145971906	774474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	116712474	0	0
T3	8352	8352	0	0
T4	2320	2320	0	0
T5	167612	164965	0	0
T6	33977	0	0	0
T8	73334	72828	0	0
T9	204274	202490	0	0
T10	1480	0	0	0
T11	116854	3	0	0
T12	47888	47888	0	0
T13	567963	457119	0	0
T14	0	657166	0	0
T15	0	605939	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	774474	0	0
T4	2320	8	0	0
T5	167612	1288	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	238	0	0
T10	1480	0	0	0
T11	116854	0	0	0
T12	47888	0	0	0
T13	567963	4520	0	0
T14	695694	7231	0	0
T15	0	7566	0	0
T16	0	585	0	0
T17	0	14098	0	0
T26	0	2854	0	0
T28	0	2220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	774474	0	0
T4	2320	8	0	0
T5	167612	1288	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	238	0	0
T10	1480	0	0	0
T11	116854	0	0	0
T12	47888	0	0	0
T13	567963	4520	0	0
T14	695694	7231	0	0
T15	0	7566	0	0
T16	0	585	0	0
T17	0	14098	0	0
T26	0	2854	0	0
T28	0	2220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	116712474	0	0
T3	8352	8352	0	0
T4	2320	2320	0	0
T5	167612	164965	0	0
T6	33977	0	0	0
T8	73334	72828	0	0
T9	204274	202490	0	0
T10	1480	0	0	0
T11	116854	3	0	0
T12	47888	47888	0	0
T13	567963	457119	0	0
T14	0	657166	0	0
T15	0	605939	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	116712474	0	0
T3	8352	8352	0	0
T4	2320	2320	0	0
T5	167612	164965	0	0
T6	33977	0	0	0
T8	73334	72828	0	0
T9	204274	202490	0	0
T10	1480	0	0	0
T11	116854	3	0	0
T12	47888	47888	0	0
T13	567963	457119	0	0
T14	0	657166	0	0
T15	0	605939	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	774474	0	0
T4	2320	8	0	0
T5	167612	1288	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	238	0	0
T10	1480	0	0	0
T11	116854	0	0	0
T12	47888	0	0	0
T13	567963	4520	0	0
T14	695694	7231	0	0
T15	0	7566	0	0
T16	0	585	0	0
T17	0	14098	0	0
T26	0	2854	0	0
T28	0	2220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	774474	0	0
T4	2320	8	0	0
T5	167612	1288	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	238	0	0
T10	1480	0	0	0
T11	116854	0	0	0
T12	47888	0	0	0
T13	567963	4520	0	0
T14	695694	7231	0	0
T15	0	7566	0	0
T16	0	585	0	0
T17	0	14098	0	0
T26	0	2854	0	0
T28	0	2220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	774474	0	0
T4	2320	8	0	0
T5	167612	1288	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	238	0	0
T10	1480	0	0	0
T11	116854	0	0	0
T12	47888	0	0	0
T13	567963	4520	0	0
T14	695694	7231	0	0
T15	0	7566	0	0
T16	0	585	0	0
T17	0	14098	0	0
T26	0	2854	0	0
T28	0	2220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	774474	0	0
T4	2320	8	0	0
T5	167612	1288	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	238	0	0
T10	1480	0	0	0
T11	116854	0	0	0
T12	47888	0	0	0
T13	567963	4520	0	0
T14	695694	7231	0	0
T15	0	7566	0	0
T16	0	585	0	0
T17	0	14098	0	0
T26	0	2854	0	0
T28	0	2220	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	116712474	0	0
T3	8352	8352	0	0
T4	2320	2320	0	0
T5	167612	164965	0	0
T6	33977	0	0	0
T8	73334	72828	0	0
T9	204274	202490	0	0
T10	1480	0	0	0
T11	116854	3	0	0
T12	47888	47888	0	0
T13	567963	457119	0	0
T14	0	657166	0	0
T15	0	605939	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145971906	774474	0	0
T4	2320	8	0	0
T5	167612	1288	0	0
T6	33977	0	0	0
T8	73334	0	0	0
T9	204274	238	0	0
T10	1480	0	0	0
T11	116854	0	0	0
T12	47888	0	0	0
T13	567963	4520	0	0
T14	695694	7231	0	0
T15	0	7566	0	0
T16	0	585	0	0
T17	0	14098	0	0
T26	0	2854	0	0
T28	0	2220	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430189956	430098632	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	430189956	2300734	0	0
GntImpliesValid_A	430189956	2300734	0	0
GrantKnown_A	430189956	430098632	0	0
IdxKnown_A	430189956	430098632	0	0
IndexIsCorrect_A	430189956	2300734	0	0
LockArbDecision_A	430189956	0	0	0
NoReadyValidNoGrant_A	430189956	0	0	0
ReadyAndValidImplyGrant_A	430189956	2300734	0	0
ReqAndReadyImplyGrant_A	430189956	2300734	0	0
ReqImpliesValid_A	430189956	2300734	0	0
ReqStaysHighUntilGranted0_M	430189956	0	0	0
RoundRobin_A	430189956	2	0	976
ValidKnown_A	430189956	430098632	0	0
gen_data_port_assertion.DataFlow_A	430189956	2300734	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	430098632	0	0
T1	146132	146046	0	0
T2	2226	2163	0	0
T3	45250	45150	0	0
T4	11975	11875	0	0
T5	119608	119603	0	0
T6	275282	275221	0	0
T7	1098	1014	0	0
T8	591636	591547	0	0
T9	76402	76327	0	0
T10	10392	10292	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2300734	0	0
T1	146132	537	0	0
T2	2226	200	0	0
T3	45250	832	0	0
T4	11975	836	0	0
T5	119608	4424	0	0
T6	275282	0	0	0
T7	1098	0	0	0
T8	591636	832	0	0
T9	76402	2559	0	0
T10	10392	38	0	0
T11	0	1417	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2300734	0	0
T1	146132	537	0	0
T2	2226	200	0	0
T3	45250	832	0	0
T4	11975	836	0	0
T5	119608	4424	0	0
T6	275282	0	0	0
T7	1098	0	0	0
T8	591636	832	0	0
T9	76402	2559	0	0
T10	10392	38	0	0
T11	0	1417	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	430098632	0	0
T1	146132	146046	0	0
T2	2226	2163	0	0
T3	45250	45150	0	0
T4	11975	11875	0	0
T5	119608	119603	0	0
T6	275282	275221	0	0
T7	1098	1014	0	0
T8	591636	591547	0	0
T9	76402	76327	0	0
T10	10392	10292	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	430098632	0	0
T1	146132	146046	0	0
T2	2226	2163	0	0
T3	45250	45150	0	0
T4	11975	11875	0	0
T5	119608	119603	0	0
T6	275282	275221	0	0
T7	1098	1014	0	0
T8	591636	591547	0	0
T9	76402	76327	0	0
T10	10392	10292	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2300734	0	0
T1	146132	537	0	0
T2	2226	200	0	0
T3	45250	832	0	0
T4	11975	836	0	0
T5	119608	4424	0	0
T6	275282	0	0	0
T7	1098	0	0	0
T8	591636	832	0	0
T9	76402	2559	0	0
T10	10392	38	0	0
T11	0	1417	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2300734	0	0
T1	146132	537	0	0
T2	2226	200	0	0
T3	45250	832	0	0
T4	11975	836	0	0
T5	119608	4424	0	0
T6	275282	0	0	0
T7	1098	0	0	0
T8	591636	832	0	0
T9	76402	2559	0	0
T10	10392	38	0	0
T11	0	1417	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2300734	0	0
T1	146132	537	0	0
T2	2226	200	0	0
T3	45250	832	0	0
T4	11975	836	0	0
T5	119608	4424	0	0
T6	275282	0	0	0
T7	1098	0	0	0
T8	591636	832	0	0
T9	76402	2559	0	0
T10	10392	38	0	0
T11	0	1417	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2300734	0	0
T1	146132	537	0	0
T2	2226	200	0	0
T3	45250	832	0	0
T4	11975	836	0	0
T5	119608	4424	0	0
T6	275282	0	0	0
T7	1098	0	0	0
T8	591636	832	0	0
T9	76402	2559	0	0
T10	10392	38	0	0
T11	0	1417	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2	0	976
T53	714239	1	0	1
T54	0	1	0	0
T55	746276	0	0	1
T56	1093	0	0	1
T57	142073	0	0	1
T58	317812	0	0	1
T59	387025	0	0	1
T60	5259	0	0	1
T61	3266	0	0	1
T62	59715	0	0	1
T63	5885	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	430098632	0	0
T1	146132	146046	0	0
T2	2226	2163	0	0
T3	45250	45150	0	0
T4	11975	11875	0	0
T5	119608	119603	0	0
T6	275282	275221	0	0
T7	1098	1014	0	0
T8	591636	591547	0	0
T9	76402	76327	0	0
T10	10392	10292	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430189956	2300734	0	0
T1	146132	537	0	0
T2	2226	200	0	0
T3	45250	832	0	0
T4	11975	836	0	0
T5	119608	4424	0	0
T6	275282	0	0	0
T7	1098	0	0	0
T8	591636	832	0	0
T9	76402	2559	0	0
T10	10392	38	0	0
T11	0	1417	0	0
T12	0	832	0	0