Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3676 | 
0 | 
0 | 
| T95 | 
6541 | 
2 | 
0 | 
0 | 
| T96 | 
9563 | 
4 | 
0 | 
0 | 
| T97 | 
4632 | 
1 | 
0 | 
0 | 
| T98 | 
19603 | 
2 | 
0 | 
0 | 
| T99 | 
65553 | 
5 | 
0 | 
0 | 
| T100 | 
26343 | 
1 | 
0 | 
0 | 
| T101 | 
78770 | 
3 | 
0 | 
0 | 
| T102 | 
3028 | 
64 | 
0 | 
0 | 
| T112 | 
10582 | 
3 | 
0 | 
0 | 
| T113 | 
10330 | 
3 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1231 | 
0 | 
0 | 
| T95 | 
6541 | 
12 | 
0 | 
0 | 
| T96 | 
9563 | 
20 | 
0 | 
0 | 
| T99 | 
65553 | 
69 | 
0 | 
0 | 
| T112 | 
10582 | 
14 | 
0 | 
0 | 
| T113 | 
10330 | 
17 | 
0 | 
0 | 
| T116 | 
6152 | 
7 | 
0 | 
0 | 
| T124 | 
7511 | 
9 | 
0 | 
0 | 
| T159 | 
234054 | 
375 | 
0 | 
0 | 
| T160 | 
19866 | 
55 | 
0 | 
0 | 
| T161 | 
21624 | 
51 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1365 | 
0 | 
0 | 
| T95 | 
6541 | 
10 | 
0 | 
0 | 
| T96 | 
9563 | 
16 | 
0 | 
0 | 
| T99 | 
65553 | 
64 | 
0 | 
0 | 
| T112 | 
10582 | 
12 | 
0 | 
0 | 
| T113 | 
10330 | 
17 | 
0 | 
0 | 
| T116 | 
6152 | 
5 | 
0 | 
0 | 
| T124 | 
7511 | 
5 | 
0 | 
0 | 
| T159 | 
234054 | 
444 | 
0 | 
0 | 
| T160 | 
19866 | 
83 | 
0 | 
0 | 
| T161 | 
21624 | 
73 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1529 | 
0 | 
0 | 
| T95 | 
6541 | 
14 | 
0 | 
0 | 
| T96 | 
9563 | 
34 | 
0 | 
0 | 
| T99 | 
65553 | 
147 | 
0 | 
0 | 
| T112 | 
10582 | 
22 | 
0 | 
0 | 
| T113 | 
10330 | 
16 | 
0 | 
0 | 
| T116 | 
6152 | 
5 | 
0 | 
0 | 
| T124 | 
7511 | 
9 | 
0 | 
0 | 
| T159 | 
234054 | 
365 | 
0 | 
0 | 
| T160 | 
19866 | 
62 | 
0 | 
0 | 
| T161 | 
21624 | 
49 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
5140 | 
0 | 
0 | 
| T95 | 
6541 | 
102 | 
0 | 
0 | 
| T96 | 
9563 | 
19 | 
0 | 
0 | 
| T99 | 
65553 | 
639 | 
0 | 
0 | 
| T112 | 
10582 | 
271 | 
0 | 
0 | 
| T113 | 
10330 | 
107 | 
0 | 
0 | 
| T116 | 
6152 | 
130 | 
0 | 
0 | 
| T124 | 
7511 | 
228 | 
0 | 
0 | 
| T159 | 
234054 | 
391 | 
0 | 
0 | 
| T160 | 
19866 | 
80 | 
0 | 
0 | 
| T161 | 
21624 | 
64 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
6168 | 
0 | 
0 | 
| T95 | 
6541 | 
126 | 
0 | 
0 | 
| T96 | 
9563 | 
147 | 
0 | 
0 | 
| T99 | 
65553 | 
1204 | 
0 | 
0 | 
| T112 | 
10582 | 
232 | 
0 | 
0 | 
| T113 | 
10330 | 
143 | 
0 | 
0 | 
| T116 | 
6152 | 
107 | 
0 | 
0 | 
| T124 | 
7511 | 
15 | 
0 | 
0 | 
| T159 | 
234054 | 
455 | 
0 | 
0 | 
| T160 | 
19866 | 
113 | 
0 | 
0 | 
| T161 | 
21624 | 
76 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
5748 | 
0 | 
0 | 
| T95 | 
6541 | 
8 | 
0 | 
0 | 
| T96 | 
9563 | 
93 | 
0 | 
0 | 
| T99 | 
65553 | 
1114 | 
0 | 
0 | 
| T112 | 
10582 | 
17 | 
0 | 
0 | 
| T113 | 
10330 | 
114 | 
0 | 
0 | 
| T116 | 
6152 | 
11 | 
0 | 
0 | 
| T124 | 
7511 | 
73 | 
0 | 
0 | 
| T159 | 
234054 | 
431 | 
0 | 
0 | 
| T160 | 
19866 | 
96 | 
0 | 
0 | 
| T161 | 
21624 | 
50 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
6950 | 
0 | 
0 | 
| T95 | 
6541 | 
125 | 
0 | 
0 | 
| T96 | 
9563 | 
232 | 
0 | 
0 | 
| T99 | 
65553 | 
1478 | 
0 | 
0 | 
| T112 | 
10582 | 
156 | 
0 | 
0 | 
| T113 | 
10330 | 
126 | 
0 | 
0 | 
| T116 | 
6152 | 
138 | 
0 | 
0 | 
| T124 | 
7511 | 
9 | 
0 | 
0 | 
| T159 | 
234054 | 
368 | 
0 | 
0 | 
| T160 | 
19866 | 
75 | 
0 | 
0 | 
| T161 | 
21624 | 
128 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
6046 | 
0 | 
0 | 
| T95 | 
6541 | 
1 | 
0 | 
0 | 
| T96 | 
9563 | 
111 | 
0 | 
0 | 
| T99 | 
65553 | 
1167 | 
0 | 
0 | 
| T112 | 
10582 | 
117 | 
0 | 
0 | 
| T113 | 
10330 | 
147 | 
0 | 
0 | 
| T116 | 
6152 | 
119 | 
0 | 
0 | 
| T124 | 
7511 | 
113 | 
0 | 
0 | 
| T159 | 
234054 | 
420 | 
0 | 
0 | 
| T160 | 
19866 | 
85 | 
0 | 
0 | 
| T161 | 
21624 | 
47 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
5947 | 
0 | 
0 | 
| T95 | 
6541 | 
123 | 
0 | 
0 | 
| T96 | 
9563 | 
23 | 
0 | 
0 | 
| T99 | 
65553 | 
1256 | 
0 | 
0 | 
| T112 | 
10582 | 
259 | 
0 | 
0 | 
| T113 | 
10330 | 
129 | 
0 | 
0 | 
| T116 | 
6152 | 
141 | 
0 | 
0 | 
| T124 | 
7511 | 
135 | 
0 | 
0 | 
| T159 | 
234054 | 
444 | 
0 | 
0 | 
| T160 | 
19866 | 
17 | 
0 | 
0 | 
| T161 | 
21624 | 
90 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
5438 | 
0 | 
0 | 
| T95 | 
6541 | 
3 | 
0 | 
0 | 
| T96 | 
9563 | 
8 | 
0 | 
0 | 
| T99 | 
65553 | 
1439 | 
0 | 
0 | 
| T112 | 
10582 | 
20 | 
0 | 
0 | 
| T113 | 
10330 | 
154 | 
0 | 
0 | 
| T116 | 
6152 | 
7 | 
0 | 
0 | 
| T124 | 
7511 | 
9 | 
0 | 
0 | 
| T159 | 
234054 | 
423 | 
0 | 
0 | 
| T160 | 
19866 | 
85 | 
0 | 
0 | 
| T161 | 
21624 | 
122 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
6341 | 
0 | 
0 | 
| T95 | 
6541 | 
4 | 
0 | 
0 | 
| T96 | 
9563 | 
235 | 
0 | 
0 | 
| T99 | 
65553 | 
1117 | 
0 | 
0 | 
| T112 | 
10582 | 
13 | 
0 | 
0 | 
| T113 | 
10330 | 
241 | 
0 | 
0 | 
| T116 | 
6152 | 
10 | 
0 | 
0 | 
| T124 | 
7511 | 
114 | 
0 | 
0 | 
| T159 | 
234054 | 
367 | 
0 | 
0 | 
| T160 | 
19866 | 
81 | 
0 | 
0 | 
| T161 | 
21624 | 
41 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2911 | 
0 | 
0 | 
| T95 | 
6541 | 
9 | 
0 | 
0 | 
| T96 | 
9563 | 
73 | 
0 | 
0 | 
| T99 | 
65553 | 
602 | 
0 | 
0 | 
| T112 | 
10582 | 
7 | 
0 | 
0 | 
| T113 | 
10330 | 
17 | 
0 | 
0 | 
| T116 | 
6152 | 
4 | 
0 | 
0 | 
| T124 | 
7511 | 
45 | 
0 | 
0 | 
| T159 | 
234054 | 
373 | 
0 | 
0 | 
| T160 | 
19866 | 
32 | 
0 | 
0 | 
| T161 | 
21624 | 
24 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3369 | 
0 | 
0 | 
| T95 | 
6541 | 
15 | 
0 | 
0 | 
| T96 | 
9563 | 
18 | 
0 | 
0 | 
| T99 | 
65553 | 
653 | 
0 | 
0 | 
| T112 | 
10582 | 
69 | 
0 | 
0 | 
| T113 | 
10330 | 
103 | 
0 | 
0 | 
| T116 | 
6152 | 
28 | 
0 | 
0 | 
| T124 | 
7511 | 
56 | 
0 | 
0 | 
| T159 | 
234054 | 
417 | 
0 | 
0 | 
| T160 | 
19866 | 
65 | 
0 | 
0 | 
| T161 | 
21624 | 
73 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3061 | 
0 | 
0 | 
| T95 | 
6541 | 
49 | 
0 | 
0 | 
| T96 | 
9563 | 
108 | 
0 | 
0 | 
| T99 | 
65553 | 
399 | 
0 | 
0 | 
| T112 | 
10582 | 
101 | 
0 | 
0 | 
| T113 | 
10330 | 
75 | 
0 | 
0 | 
| T116 | 
6152 | 
43 | 
0 | 
0 | 
| T124 | 
7511 | 
56 | 
0 | 
0 | 
| T159 | 
234054 | 
371 | 
0 | 
0 | 
| T160 | 
19866 | 
80 | 
0 | 
0 | 
| T161 | 
21624 | 
80 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3108 | 
0 | 
0 | 
| T95 | 
6541 | 
4 | 
0 | 
0 | 
| T96 | 
9563 | 
41 | 
0 | 
0 | 
| T99 | 
65553 | 
457 | 
0 | 
0 | 
| T112 | 
10582 | 
85 | 
0 | 
0 | 
| T113 | 
10330 | 
76 | 
0 | 
0 | 
| T116 | 
6152 | 
59 | 
0 | 
0 | 
| T124 | 
7511 | 
52 | 
0 | 
0 | 
| T159 | 
234054 | 
370 | 
0 | 
0 | 
| T160 | 
19866 | 
84 | 
0 | 
0 | 
| T161 | 
21624 | 
83 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3216 | 
0 | 
0 | 
| T95 | 
6541 | 
10 | 
0 | 
0 | 
| T96 | 
9563 | 
29 | 
0 | 
0 | 
| T99 | 
65553 | 
538 | 
0 | 
0 | 
| T112 | 
10582 | 
98 | 
0 | 
0 | 
| T113 | 
10330 | 
79 | 
0 | 
0 | 
| T116 | 
6152 | 
7 | 
0 | 
0 | 
| T124 | 
7511 | 
101 | 
0 | 
0 | 
| T159 | 
234054 | 
432 | 
0 | 
0 | 
| T160 | 
19866 | 
71 | 
0 | 
0 | 
| T161 | 
21624 | 
64 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3478 | 
0 | 
0 | 
| T95 | 
6541 | 
67 | 
0 | 
0 | 
| T96 | 
9563 | 
79 | 
0 | 
0 | 
| T99 | 
65553 | 
767 | 
0 | 
0 | 
| T112 | 
10582 | 
108 | 
0 | 
0 | 
| T113 | 
10330 | 
52 | 
0 | 
0 | 
| T116 | 
6152 | 
48 | 
0 | 
0 | 
| T124 | 
7511 | 
93 | 
0 | 
0 | 
| T159 | 
234054 | 
431 | 
0 | 
0 | 
| T160 | 
19866 | 
49 | 
0 | 
0 | 
| T161 | 
21624 | 
71 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3360 | 
0 | 
0 | 
| T95 | 
6541 | 
35 | 
0 | 
0 | 
| T96 | 
9563 | 
101 | 
0 | 
0 | 
| T99 | 
65553 | 
708 | 
0 | 
0 | 
| T112 | 
10582 | 
22 | 
0 | 
0 | 
| T113 | 
10330 | 
47 | 
0 | 
0 | 
| T116 | 
6152 | 
60 | 
0 | 
0 | 
| T124 | 
7511 | 
61 | 
0 | 
0 | 
| T159 | 
234054 | 
429 | 
0 | 
0 | 
| T160 | 
19866 | 
138 | 
0 | 
0 | 
| T161 | 
21624 | 
50 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3064 | 
0 | 
0 | 
| T95 | 
6541 | 
41 | 
0 | 
0 | 
| T96 | 
9563 | 
67 | 
0 | 
0 | 
| T99 | 
65553 | 
371 | 
0 | 
0 | 
| T112 | 
10582 | 
56 | 
0 | 
0 | 
| T113 | 
10330 | 
16 | 
0 | 
0 | 
| T116 | 
6152 | 
59 | 
0 | 
0 | 
| T124 | 
7511 | 
99 | 
0 | 
0 | 
| T159 | 
234054 | 
406 | 
0 | 
0 | 
| T160 | 
19866 | 
32 | 
0 | 
0 | 
| T161 | 
21624 | 
54 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3309 | 
0 | 
0 | 
| T95 | 
6541 | 
52 | 
0 | 
0 | 
| T96 | 
9563 | 
69 | 
0 | 
0 | 
| T99 | 
65553 | 
405 | 
0 | 
0 | 
| T112 | 
10582 | 
132 | 
0 | 
0 | 
| T113 | 
10330 | 
130 | 
0 | 
0 | 
| T116 | 
6152 | 
10 | 
0 | 
0 | 
| T124 | 
7511 | 
46 | 
0 | 
0 | 
| T159 | 
234054 | 
369 | 
0 | 
0 | 
| T160 | 
19866 | 
103 | 
0 | 
0 | 
| T161 | 
21624 | 
75 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2987 | 
0 | 
0 | 
| T95 | 
6541 | 
12 | 
0 | 
0 | 
| T96 | 
9563 | 
62 | 
0 | 
0 | 
| T99 | 
65553 | 
500 | 
0 | 
0 | 
| T112 | 
10582 | 
96 | 
0 | 
0 | 
| T113 | 
10330 | 
11 | 
0 | 
0 | 
| T116 | 
6152 | 
42 | 
0 | 
0 | 
| T124 | 
7511 | 
84 | 
0 | 
0 | 
| T159 | 
234054 | 
395 | 
0 | 
0 | 
| T160 | 
19866 | 
19 | 
0 | 
0 | 
| T161 | 
21624 | 
66 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3409 | 
0 | 
0 | 
| T95 | 
6541 | 
45 | 
0 | 
0 | 
| T96 | 
9563 | 
45 | 
0 | 
0 | 
| T99 | 
65553 | 
674 | 
0 | 
0 | 
| T112 | 
10582 | 
70 | 
0 | 
0 | 
| T113 | 
10330 | 
133 | 
0 | 
0 | 
| T116 | 
6152 | 
9 | 
0 | 
0 | 
| T124 | 
7511 | 
99 | 
0 | 
0 | 
| T159 | 
234054 | 
383 | 
0 | 
0 | 
| T160 | 
19866 | 
120 | 
0 | 
0 | 
| T161 | 
21624 | 
41 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3418 | 
0 | 
0 | 
| T95 | 
6541 | 
76 | 
0 | 
0 | 
| T96 | 
9563 | 
110 | 
0 | 
0 | 
| T99 | 
65553 | 
493 | 
0 | 
0 | 
| T112 | 
10582 | 
23 | 
0 | 
0 | 
| T113 | 
10330 | 
18 | 
0 | 
0 | 
| T116 | 
6152 | 
54 | 
0 | 
0 | 
| T124 | 
7511 | 
61 | 
0 | 
0 | 
| T159 | 
234054 | 
412 | 
0 | 
0 | 
| T160 | 
19866 | 
51 | 
0 | 
0 | 
| T161 | 
21624 | 
80 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3123 | 
0 | 
0 | 
| T95 | 
6541 | 
66 | 
0 | 
0 | 
| T96 | 
9563 | 
8 | 
0 | 
0 | 
| T99 | 
65553 | 
534 | 
0 | 
0 | 
| T112 | 
10582 | 
131 | 
0 | 
0 | 
| T113 | 
10330 | 
16 | 
0 | 
0 | 
| T116 | 
6152 | 
10 | 
0 | 
0 | 
| T124 | 
7511 | 
59 | 
0 | 
0 | 
| T159 | 
234054 | 
380 | 
0 | 
0 | 
| T160 | 
19866 | 
35 | 
0 | 
0 | 
| T161 | 
21624 | 
52 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2827 | 
0 | 
0 | 
| T95 | 
6541 | 
10 | 
0 | 
0 | 
| T96 | 
9563 | 
63 | 
0 | 
0 | 
| T99 | 
65553 | 
410 | 
0 | 
0 | 
| T112 | 
10582 | 
120 | 
0 | 
0 | 
| T113 | 
10330 | 
73 | 
0 | 
0 | 
| T116 | 
6152 | 
49 | 
0 | 
0 | 
| T124 | 
7511 | 
6 | 
0 | 
0 | 
| T159 | 
234054 | 
386 | 
0 | 
0 | 
| T160 | 
19866 | 
65 | 
0 | 
0 | 
| T161 | 
21624 | 
132 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3311 | 
0 | 
0 | 
| T95 | 
6541 | 
42 | 
0 | 
0 | 
| T96 | 
9563 | 
4 | 
0 | 
0 | 
| T99 | 
65553 | 
647 | 
0 | 
0 | 
| T112 | 
10582 | 
126 | 
0 | 
0 | 
| T113 | 
10330 | 
21 | 
0 | 
0 | 
| T116 | 
6152 | 
56 | 
0 | 
0 | 
| T124 | 
7511 | 
36 | 
0 | 
0 | 
| T159 | 
234054 | 
476 | 
0 | 
0 | 
| T160 | 
19866 | 
79 | 
0 | 
0 | 
| T161 | 
21624 | 
57 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2816 | 
0 | 
0 | 
| T95 | 
6541 | 
61 | 
0 | 
0 | 
| T96 | 
9563 | 
96 | 
0 | 
0 | 
| T99 | 
65553 | 
394 | 
0 | 
0 | 
| T112 | 
10582 | 
76 | 
0 | 
0 | 
| T113 | 
10330 | 
59 | 
0 | 
0 | 
| T116 | 
6152 | 
14 | 
0 | 
0 | 
| T124 | 
7511 | 
107 | 
0 | 
0 | 
| T159 | 
234054 | 
339 | 
0 | 
0 | 
| T160 | 
19866 | 
59 | 
0 | 
0 | 
| T161 | 
21624 | 
47 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2719 | 
0 | 
0 | 
| T95 | 
6541 | 
12 | 
0 | 
0 | 
| T96 | 
9563 | 
51 | 
0 | 
0 | 
| T99 | 
65553 | 
469 | 
0 | 
0 | 
| T112 | 
10582 | 
20 | 
0 | 
0 | 
| T113 | 
10330 | 
89 | 
0 | 
0 | 
| T116 | 
6152 | 
56 | 
0 | 
0 | 
| T124 | 
7511 | 
16 | 
0 | 
0 | 
| T159 | 
234054 | 
367 | 
0 | 
0 | 
| T160 | 
19866 | 
115 | 
0 | 
0 | 
| T161 | 
21624 | 
80 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3072 | 
0 | 
0 | 
| T95 | 
6541 | 
10 | 
0 | 
0 | 
| T96 | 
9563 | 
18 | 
0 | 
0 | 
| T99 | 
65553 | 
727 | 
0 | 
0 | 
| T112 | 
10582 | 
66 | 
0 | 
0 | 
| T113 | 
10330 | 
56 | 
0 | 
0 | 
| T116 | 
6152 | 
65 | 
0 | 
0 | 
| T124 | 
7511 | 
5 | 
0 | 
0 | 
| T159 | 
234054 | 
401 | 
0 | 
0 | 
| T160 | 
19866 | 
54 | 
0 | 
0 | 
| T161 | 
21624 | 
52 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2975 | 
0 | 
0 | 
| T95 | 
6541 | 
60 | 
0 | 
0 | 
| T96 | 
9563 | 
74 | 
0 | 
0 | 
| T99 | 
65553 | 
563 | 
0 | 
0 | 
| T112 | 
10582 | 
78 | 
0 | 
0 | 
| T113 | 
10330 | 
52 | 
0 | 
0 | 
| T116 | 
6152 | 
41 | 
0 | 
0 | 
| T124 | 
7511 | 
1 | 
0 | 
0 | 
| T159 | 
234054 | 
416 | 
0 | 
0 | 
| T160 | 
19866 | 
75 | 
0 | 
0 | 
| T161 | 
21624 | 
40 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3217 | 
0 | 
0 | 
| T95 | 
6541 | 
10 | 
0 | 
0 | 
| T96 | 
9563 | 
19 | 
0 | 
0 | 
| T99 | 
65553 | 
490 | 
0 | 
0 | 
| T112 | 
10582 | 
113 | 
0 | 
0 | 
| T113 | 
10330 | 
126 | 
0 | 
0 | 
| T116 | 
6152 | 
14 | 
0 | 
0 | 
| T124 | 
7511 | 
3 | 
0 | 
0 | 
| T159 | 
234054 | 
416 | 
0 | 
0 | 
| T160 | 
19866 | 
66 | 
0 | 
0 | 
| T161 | 
21624 | 
63 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3405 | 
0 | 
0 | 
| T95 | 
6541 | 
58 | 
0 | 
0 | 
| T96 | 
9563 | 
45 | 
0 | 
0 | 
| T99 | 
65553 | 
660 | 
0 | 
0 | 
| T112 | 
10582 | 
57 | 
0 | 
0 | 
| T113 | 
10330 | 
58 | 
0 | 
0 | 
| T116 | 
6152 | 
34 | 
0 | 
0 | 
| T124 | 
7511 | 
36 | 
0 | 
0 | 
| T159 | 
234054 | 
445 | 
0 | 
0 | 
| T160 | 
19866 | 
75 | 
0 | 
0 | 
| T161 | 
21624 | 
76 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2996 | 
0 | 
0 | 
| T95 | 
6541 | 
8 | 
0 | 
0 | 
| T96 | 
9563 | 
96 | 
0 | 
0 | 
| T99 | 
65553 | 
528 | 
0 | 
0 | 
| T112 | 
10582 | 
14 | 
0 | 
0 | 
| T113 | 
10330 | 
38 | 
0 | 
0 | 
| T116 | 
6152 | 
49 | 
0 | 
0 | 
| T124 | 
7511 | 
105 | 
0 | 
0 | 
| T159 | 
234054 | 
349 | 
0 | 
0 | 
| T160 | 
19866 | 
42 | 
0 | 
0 | 
| T161 | 
21624 | 
66 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3196 | 
0 | 
0 | 
| T95 | 
6541 | 
59 | 
0 | 
0 | 
| T96 | 
9563 | 
63 | 
0 | 
0 | 
| T99 | 
65553 | 
650 | 
0 | 
0 | 
| T112 | 
10582 | 
73 | 
0 | 
0 | 
| T113 | 
10330 | 
15 | 
0 | 
0 | 
| T116 | 
6152 | 
52 | 
0 | 
0 | 
| T124 | 
7511 | 
11 | 
0 | 
0 | 
| T159 | 
234054 | 
327 | 
0 | 
0 | 
| T160 | 
19866 | 
63 | 
0 | 
0 | 
| T161 | 
21624 | 
6 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
2993 | 
0 | 
0 | 
| T95 | 
6541 | 
58 | 
0 | 
0 | 
| T96 | 
9563 | 
18 | 
0 | 
0 | 
| T99 | 
65553 | 
438 | 
0 | 
0 | 
| T112 | 
10582 | 
66 | 
0 | 
0 | 
| T113 | 
10330 | 
112 | 
0 | 
0 | 
| T116 | 
6152 | 
49 | 
0 | 
0 | 
| T124 | 
7511 | 
44 | 
0 | 
0 | 
| T159 | 
234054 | 
480 | 
0 | 
0 | 
| T160 | 
19866 | 
69 | 
0 | 
0 | 
| T161 | 
21624 | 
75 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1484 | 
0 | 
0 | 
| T95 | 
6541 | 
11 | 
0 | 
0 | 
| T96 | 
9563 | 
18 | 
0 | 
0 | 
| T99 | 
65553 | 
138 | 
0 | 
0 | 
| T112 | 
10582 | 
23 | 
0 | 
0 | 
| T113 | 
10330 | 
40 | 
0 | 
0 | 
| T116 | 
6152 | 
13 | 
0 | 
0 | 
| T124 | 
7511 | 
10 | 
0 | 
0 | 
| T159 | 
234054 | 
450 | 
0 | 
0 | 
| T160 | 
19866 | 
84 | 
0 | 
0 | 
| T161 | 
21624 | 
85 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1484 | 
0 | 
0 | 
| T95 | 
6541 | 
14 | 
0 | 
0 | 
| T96 | 
9563 | 
16 | 
0 | 
0 | 
| T99 | 
65553 | 
118 | 
0 | 
0 | 
| T112 | 
10582 | 
15 | 
0 | 
0 | 
| T113 | 
10330 | 
25 | 
0 | 
0 | 
| T116 | 
6152 | 
14 | 
0 | 
0 | 
| T124 | 
7511 | 
5 | 
0 | 
0 | 
| T159 | 
234054 | 
434 | 
0 | 
0 | 
| T160 | 
19866 | 
20 | 
0 | 
0 | 
| T161 | 
21624 | 
85 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1637 | 
0 | 
0 | 
| T95 | 
6541 | 
2 | 
0 | 
0 | 
| T96 | 
9563 | 
14 | 
0 | 
0 | 
| T99 | 
65553 | 
143 | 
0 | 
0 | 
| T112 | 
10582 | 
12 | 
0 | 
0 | 
| T113 | 
10330 | 
18 | 
0 | 
0 | 
| T116 | 
6152 | 
8 | 
0 | 
0 | 
| T124 | 
7511 | 
16 | 
0 | 
0 | 
| T159 | 
234054 | 
460 | 
0 | 
0 | 
| T160 | 
19866 | 
79 | 
0 | 
0 | 
| T161 | 
21624 | 
99 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1483 | 
0 | 
0 | 
| T95 | 
6541 | 
16 | 
0 | 
0 | 
| T96 | 
9563 | 
16 | 
0 | 
0 | 
| T99 | 
65553 | 
129 | 
0 | 
0 | 
| T112 | 
10582 | 
15 | 
0 | 
0 | 
| T113 | 
10330 | 
26 | 
0 | 
0 | 
| T116 | 
6152 | 
2 | 
0 | 
0 | 
| T124 | 
7511 | 
18 | 
0 | 
0 | 
| T159 | 
234054 | 
372 | 
0 | 
0 | 
| T160 | 
19866 | 
49 | 
0 | 
0 | 
| T161 | 
21624 | 
110 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1845 | 
0 | 
0 | 
| T95 | 
6541 | 
11 | 
0 | 
0 | 
| T96 | 
9563 | 
33 | 
0 | 
0 | 
| T99 | 
65553 | 
187 | 
0 | 
0 | 
| T112 | 
10582 | 
55 | 
0 | 
0 | 
| T113 | 
10330 | 
12 | 
0 | 
0 | 
| T116 | 
6152 | 
14 | 
0 | 
0 | 
| T124 | 
7511 | 
16 | 
0 | 
0 | 
| T159 | 
234054 | 
364 | 
0 | 
0 | 
| T160 | 
19866 | 
108 | 
0 | 
0 | 
| T161 | 
21624 | 
161 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
3249 | 
0 | 
0 | 
| T19 | 
5165 | 
62 | 
0 | 
0 | 
| T31 | 
0 | 
36 | 
0 | 
0 | 
| T32 | 
0 | 
42 | 
0 | 
0 | 
| T39 | 
0 | 
63 | 
0 | 
0 | 
| T65 | 
1112 | 
0 | 
0 | 
0 | 
| T162 | 
0 | 
46 | 
0 | 
0 | 
| T163 | 
0 | 
66 | 
0 | 
0 | 
| T164 | 
0 | 
2 | 
0 | 
0 | 
| T165 | 
0 | 
40 | 
0 | 
0 | 
| T166 | 
0 | 
39 | 
0 | 
0 | 
| T167 | 
0 | 
19 | 
0 | 
0 | 
| T168 | 
106391 | 
0 | 
0 | 
0 | 
| T169 | 
1487 | 
0 | 
0 | 
0 | 
| T170 | 
473989 | 
0 | 
0 | 
0 | 
| T171 | 
93463 | 
0 | 
0 | 
0 | 
| T172 | 
37821 | 
0 | 
0 | 
0 | 
| T173 | 
287361 | 
0 | 
0 | 
0 | 
| T174 | 
22746 | 
0 | 
0 | 
0 | 
| T175 | 
15591 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1484 | 
0 | 
0 | 
| T95 | 
6541 | 
20 | 
0 | 
0 | 
| T96 | 
9563 | 
16 | 
0 | 
0 | 
| T99 | 
65553 | 
114 | 
0 | 
0 | 
| T112 | 
10582 | 
15 | 
0 | 
0 | 
| T113 | 
10330 | 
18 | 
0 | 
0 | 
| T116 | 
6152 | 
8 | 
0 | 
0 | 
| T124 | 
7511 | 
9 | 
0 | 
0 | 
| T159 | 
234054 | 
436 | 
0 | 
0 | 
| T160 | 
19866 | 
55 | 
0 | 
0 | 
| T161 | 
21624 | 
127 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1558 | 
0 | 
0 | 
| T95 | 
6541 | 
13 | 
0 | 
0 | 
| T96 | 
9563 | 
23 | 
0 | 
0 | 
| T99 | 
65553 | 
128 | 
0 | 
0 | 
| T112 | 
10582 | 
15 | 
0 | 
0 | 
| T113 | 
10330 | 
26 | 
0 | 
0 | 
| T116 | 
6152 | 
15 | 
0 | 
0 | 
| T124 | 
7511 | 
10 | 
0 | 
0 | 
| T159 | 
234054 | 
446 | 
0 | 
0 | 
| T160 | 
19866 | 
52 | 
0 | 
0 | 
| T161 | 
21624 | 
81 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1230 | 
0 | 
0 | 
| T95 | 
6541 | 
9 | 
0 | 
0 | 
| T96 | 
9563 | 
8 | 
0 | 
0 | 
| T99 | 
65553 | 
87 | 
0 | 
0 | 
| T112 | 
10582 | 
16 | 
0 | 
0 | 
| T113 | 
10330 | 
11 | 
0 | 
0 | 
| T116 | 
6152 | 
9 | 
0 | 
0 | 
| T124 | 
7511 | 
2 | 
0 | 
0 | 
| T159 | 
234054 | 
378 | 
0 | 
0 | 
| T160 | 
19866 | 
13 | 
0 | 
0 | 
| T161 | 
21624 | 
26 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1343 | 
0 | 
0 | 
| T95 | 
6541 | 
9 | 
0 | 
0 | 
| T96 | 
9563 | 
19 | 
0 | 
0 | 
| T99 | 
65553 | 
65 | 
0 | 
0 | 
| T112 | 
10582 | 
19 | 
0 | 
0 | 
| T113 | 
10330 | 
22 | 
0 | 
0 | 
| T116 | 
6152 | 
4 | 
0 | 
0 | 
| T124 | 
7511 | 
7 | 
0 | 
0 | 
| T159 | 
234054 | 
382 | 
0 | 
0 | 
| T160 | 
19866 | 
89 | 
0 | 
0 | 
| T161 | 
21624 | 
32 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1278 | 
0 | 
0 | 
| T95 | 
6541 | 
6 | 
0 | 
0 | 
| T96 | 
9563 | 
15 | 
0 | 
0 | 
| T99 | 
65553 | 
69 | 
0 | 
0 | 
| T112 | 
10582 | 
18 | 
0 | 
0 | 
| T113 | 
10330 | 
9 | 
0 | 
0 | 
| T116 | 
6152 | 
4 | 
0 | 
0 | 
| T124 | 
7511 | 
4 | 
0 | 
0 | 
| T159 | 
234054 | 
392 | 
0 | 
0 | 
| T160 | 
19866 | 
48 | 
0 | 
0 | 
| T161 | 
21624 | 
63 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1341 | 
0 | 
0 | 
| T95 | 
6541 | 
3 | 
0 | 
0 | 
| T96 | 
9563 | 
15 | 
0 | 
0 | 
| T99 | 
65553 | 
70 | 
0 | 
0 | 
| T112 | 
10582 | 
16 | 
0 | 
0 | 
| T113 | 
10330 | 
33 | 
0 | 
0 | 
| T116 | 
6152 | 
13 | 
0 | 
0 | 
| T124 | 
7511 | 
9 | 
0 | 
0 | 
| T159 | 
234054 | 
382 | 
0 | 
0 | 
| T160 | 
19866 | 
46 | 
0 | 
0 | 
| T161 | 
21624 | 
52 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1690 | 
0 | 
0 | 
| T95 | 
6541 | 
6 | 
0 | 
0 | 
| T96 | 
9563 | 
13 | 
0 | 
0 | 
| T99 | 
65553 | 
218 | 
0 | 
0 | 
| T112 | 
10582 | 
6 | 
0 | 
0 | 
| T113 | 
10330 | 
30 | 
0 | 
0 | 
| T116 | 
6152 | 
11 | 
0 | 
0 | 
| T124 | 
7511 | 
5 | 
0 | 
0 | 
| T159 | 
234054 | 
399 | 
0 | 
0 | 
| T160 | 
19866 | 
101 | 
0 | 
0 | 
| T161 | 
21624 | 
87 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1266 | 
0 | 
0 | 
| T95 | 
6541 | 
5 | 
0 | 
0 | 
| T96 | 
9563 | 
11 | 
0 | 
0 | 
| T99 | 
65553 | 
71 | 
0 | 
0 | 
| T112 | 
10582 | 
12 | 
0 | 
0 | 
| T113 | 
10330 | 
7 | 
0 | 
0 | 
| T116 | 
6152 | 
1 | 
0 | 
0 | 
| T124 | 
7511 | 
5 | 
0 | 
0 | 
| T159 | 
234054 | 
458 | 
0 | 
0 | 
| T160 | 
19866 | 
72 | 
0 | 
0 | 
| T161 | 
21624 | 
22 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1757 | 
0 | 
0 | 
| T95 | 
6541 | 
23 | 
0 | 
0 | 
| T96 | 
9563 | 
23 | 
0 | 
0 | 
| T99 | 
65553 | 
226 | 
0 | 
0 | 
| T112 | 
10582 | 
20 | 
0 | 
0 | 
| T113 | 
10330 | 
47 | 
0 | 
0 | 
| T116 | 
6152 | 
15 | 
0 | 
0 | 
| T124 | 
7511 | 
16 | 
0 | 
0 | 
| T159 | 
234054 | 
373 | 
0 | 
0 | 
| T160 | 
19866 | 
66 | 
0 | 
0 | 
| T161 | 
21624 | 
53 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1493 | 
0 | 
0 | 
| T95 | 
6541 | 
16 | 
0 | 
0 | 
| T96 | 
9563 | 
27 | 
0 | 
0 | 
| T99 | 
65553 | 
84 | 
0 | 
0 | 
| T112 | 
10582 | 
21 | 
0 | 
0 | 
| T113 | 
10330 | 
23 | 
0 | 
0 | 
| T116 | 
6152 | 
15 | 
0 | 
0 | 
| T124 | 
7511 | 
17 | 
0 | 
0 | 
| T159 | 
234054 | 
414 | 
0 | 
0 | 
| T160 | 
19866 | 
68 | 
0 | 
0 | 
| T161 | 
21624 | 
89 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1278 | 
0 | 
0 | 
| T95 | 
6541 | 
5 | 
0 | 
0 | 
| T96 | 
9563 | 
10 | 
0 | 
0 | 
| T99 | 
65553 | 
76 | 
0 | 
0 | 
| T112 | 
10582 | 
20 | 
0 | 
0 | 
| T113 | 
10330 | 
8 | 
0 | 
0 | 
| T116 | 
6152 | 
8 | 
0 | 
0 | 
| T124 | 
7511 | 
7 | 
0 | 
0 | 
| T159 | 
234054 | 
438 | 
0 | 
0 | 
| T160 | 
19866 | 
49 | 
0 | 
0 | 
| T161 | 
21624 | 
68 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1170 | 
0 | 
0 | 
| T95 | 
6541 | 
7 | 
0 | 
0 | 
| T96 | 
9563 | 
8 | 
0 | 
0 | 
| T99 | 
65553 | 
73 | 
0 | 
0 | 
| T112 | 
10582 | 
17 | 
0 | 
0 | 
| T113 | 
10330 | 
12 | 
0 | 
0 | 
| T116 | 
6152 | 
2 | 
0 | 
0 | 
| T124 | 
7511 | 
8 | 
0 | 
0 | 
| T159 | 
234054 | 
388 | 
0 | 
0 | 
| T160 | 
19866 | 
32 | 
0 | 
0 | 
| T161 | 
21624 | 
10 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1352 | 
0 | 
0 | 
| T95 | 
6541 | 
4 | 
0 | 
0 | 
| T96 | 
9563 | 
19 | 
0 | 
0 | 
| T99 | 
65553 | 
79 | 
0 | 
0 | 
| T112 | 
10582 | 
11 | 
0 | 
0 | 
| T113 | 
10330 | 
19 | 
0 | 
0 | 
| T116 | 
6152 | 
17 | 
0 | 
0 | 
| T124 | 
7511 | 
10 | 
0 | 
0 | 
| T159 | 
234054 | 
407 | 
0 | 
0 | 
| T160 | 
19866 | 
91 | 
0 | 
0 | 
| T161 | 
21624 | 
67 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1356 | 
0 | 
0 | 
| T95 | 
6541 | 
7 | 
0 | 
0 | 
| T96 | 
9563 | 
21 | 
0 | 
0 | 
| T99 | 
65553 | 
60 | 
0 | 
0 | 
| T112 | 
10582 | 
27 | 
0 | 
0 | 
| T113 | 
10330 | 
16 | 
0 | 
0 | 
| T116 | 
6152 | 
8 | 
0 | 
0 | 
| T124 | 
7511 | 
10 | 
0 | 
0 | 
| T159 | 
234054 | 
428 | 
0 | 
0 | 
| T160 | 
19866 | 
65 | 
0 | 
0 | 
| T161 | 
21624 | 
11 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1264 | 
0 | 
0 | 
| T84 | 
3417 | 
10 | 
0 | 
0 | 
| T95 | 
6541 | 
15 | 
0 | 
0 | 
| T96 | 
9563 | 
14 | 
0 | 
0 | 
| T99 | 
65553 | 
67 | 
0 | 
0 | 
| T112 | 
10582 | 
19 | 
0 | 
0 | 
| T113 | 
10330 | 
23 | 
0 | 
0 | 
| T124 | 
7511 | 
12 | 
0 | 
0 | 
| T159 | 
234054 | 
451 | 
0 | 
0 | 
| T160 | 
19866 | 
41 | 
0 | 
0 | 
| T161 | 
21624 | 
27 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
432393533 | 
1229 | 
0 | 
0 | 
| T95 | 
6541 | 
6 | 
0 | 
0 | 
| T96 | 
9563 | 
19 | 
0 | 
0 | 
| T99 | 
65553 | 
66 | 
0 | 
0 | 
| T112 | 
10582 | 
14 | 
0 | 
0 | 
| T113 | 
10330 | 
10 | 
0 | 
0 | 
| T116 | 
6152 | 
2 | 
0 | 
0 | 
| T124 | 
7511 | 
5 | 
0 | 
0 | 
| T159 | 
234054 | 
356 | 
0 | 
0 | 
| T160 | 
19866 | 
69 | 
0 | 
0 | 
| T161 | 
21624 | 
57 | 
0 | 
0 |